intel_dp.c 69 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <linux/export.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "drm_crtc.h"
  33. #include "drm_crtc_helper.h"
  34. #include "intel_drv.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. #include "drm_dp_helper.h"
  38. #define DP_RECEIVER_CAP_SIZE 0xf
  39. #define DP_LINK_STATUS_SIZE 6
  40. #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  41. #define DP_LINK_CONFIGURATION_SIZE 9
  42. struct intel_dp {
  43. struct intel_encoder base;
  44. uint32_t output_reg;
  45. uint32_t DP;
  46. uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
  47. bool has_audio;
  48. enum hdmi_force_audio force_audio;
  49. uint32_t color_range;
  50. int dpms_mode;
  51. uint8_t link_bw;
  52. uint8_t lane_count;
  53. uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  54. struct i2c_adapter adapter;
  55. struct i2c_algo_dp_aux_data algo;
  56. bool is_pch_edp;
  57. uint8_t train_set[4];
  58. int panel_power_up_delay;
  59. int panel_power_down_delay;
  60. int panel_power_cycle_delay;
  61. int backlight_on_delay;
  62. int backlight_off_delay;
  63. struct drm_display_mode *panel_fixed_mode; /* for eDP */
  64. struct delayed_work panel_vdd_work;
  65. bool want_panel_vdd;
  66. };
  67. /**
  68. * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  69. * @intel_dp: DP struct
  70. *
  71. * If a CPU or PCH DP output is attached to an eDP panel, this function
  72. * will return true, and false otherwise.
  73. */
  74. static bool is_edp(struct intel_dp *intel_dp)
  75. {
  76. return intel_dp->base.type == INTEL_OUTPUT_EDP;
  77. }
  78. /**
  79. * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  80. * @intel_dp: DP struct
  81. *
  82. * Returns true if the given DP struct corresponds to a PCH DP port attached
  83. * to an eDP panel, false otherwise. Helpful for determining whether we
  84. * may need FDI resources for a given DP output or not.
  85. */
  86. static bool is_pch_edp(struct intel_dp *intel_dp)
  87. {
  88. return intel_dp->is_pch_edp;
  89. }
  90. /**
  91. * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  92. * @intel_dp: DP struct
  93. *
  94. * Returns true if the given DP struct corresponds to a CPU eDP port.
  95. */
  96. static bool is_cpu_edp(struct intel_dp *intel_dp)
  97. {
  98. return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  99. }
  100. static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  101. {
  102. return container_of(encoder, struct intel_dp, base.base);
  103. }
  104. static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  105. {
  106. return container_of(intel_attached_encoder(connector),
  107. struct intel_dp, base);
  108. }
  109. /**
  110. * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  111. * @encoder: DRM encoder
  112. *
  113. * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
  114. * by intel_display.c.
  115. */
  116. bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  117. {
  118. struct intel_dp *intel_dp;
  119. if (!encoder)
  120. return false;
  121. intel_dp = enc_to_intel_dp(encoder);
  122. return is_pch_edp(intel_dp);
  123. }
  124. static void intel_dp_start_link_train(struct intel_dp *intel_dp);
  125. static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  126. static void intel_dp_link_down(struct intel_dp *intel_dp);
  127. void
  128. intel_edp_link_config(struct intel_encoder *intel_encoder,
  129. int *lane_num, int *link_bw)
  130. {
  131. struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  132. *lane_num = intel_dp->lane_count;
  133. if (intel_dp->link_bw == DP_LINK_BW_1_62)
  134. *link_bw = 162000;
  135. else if (intel_dp->link_bw == DP_LINK_BW_2_7)
  136. *link_bw = 270000;
  137. }
  138. static int
  139. intel_dp_max_lane_count(struct intel_dp *intel_dp)
  140. {
  141. int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
  142. switch (max_lane_count) {
  143. case 1: case 2: case 4:
  144. break;
  145. default:
  146. max_lane_count = 4;
  147. }
  148. return max_lane_count;
  149. }
  150. static int
  151. intel_dp_max_link_bw(struct intel_dp *intel_dp)
  152. {
  153. int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  154. switch (max_link_bw) {
  155. case DP_LINK_BW_1_62:
  156. case DP_LINK_BW_2_7:
  157. break;
  158. default:
  159. max_link_bw = DP_LINK_BW_1_62;
  160. break;
  161. }
  162. return max_link_bw;
  163. }
  164. static int
  165. intel_dp_link_clock(uint8_t link_bw)
  166. {
  167. if (link_bw == DP_LINK_BW_2_7)
  168. return 270000;
  169. else
  170. return 162000;
  171. }
  172. /*
  173. * The units on the numbers in the next two are... bizarre. Examples will
  174. * make it clearer; this one parallels an example in the eDP spec.
  175. *
  176. * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  177. *
  178. * 270000 * 1 * 8 / 10 == 216000
  179. *
  180. * The actual data capacity of that configuration is 2.16Gbit/s, so the
  181. * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
  182. * or equivalently, kilopixels per second - so for 1680x1050R it'd be
  183. * 119000. At 18bpp that's 2142000 kilobits per second.
  184. *
  185. * Thus the strange-looking division by 10 in intel_dp_link_required, to
  186. * get the result in decakilobits instead of kilobits.
  187. */
  188. static int
  189. intel_dp_link_required(int pixel_clock, int bpp)
  190. {
  191. return (pixel_clock * bpp + 9) / 10;
  192. }
  193. static int
  194. intel_dp_max_data_rate(int max_link_clock, int max_lanes)
  195. {
  196. return (max_link_clock * max_lanes * 8) / 10;
  197. }
  198. static bool
  199. intel_dp_adjust_dithering(struct intel_dp *intel_dp,
  200. struct drm_display_mode *mode,
  201. struct drm_display_mode *adjusted_mode)
  202. {
  203. int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
  204. int max_lanes = intel_dp_max_lane_count(intel_dp);
  205. int max_rate, mode_rate;
  206. mode_rate = intel_dp_link_required(mode->clock, 24);
  207. max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
  208. if (mode_rate > max_rate) {
  209. mode_rate = intel_dp_link_required(mode->clock, 18);
  210. if (mode_rate > max_rate)
  211. return false;
  212. if (adjusted_mode)
  213. adjusted_mode->private_flags
  214. |= INTEL_MODE_DP_FORCE_6BPC;
  215. return true;
  216. }
  217. return true;
  218. }
  219. static int
  220. intel_dp_mode_valid(struct drm_connector *connector,
  221. struct drm_display_mode *mode)
  222. {
  223. struct intel_dp *intel_dp = intel_attached_dp(connector);
  224. if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
  225. if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
  226. return MODE_PANEL;
  227. if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
  228. return MODE_PANEL;
  229. }
  230. if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
  231. return MODE_CLOCK_HIGH;
  232. if (mode->clock < 10000)
  233. return MODE_CLOCK_LOW;
  234. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  235. return MODE_H_ILLEGAL;
  236. return MODE_OK;
  237. }
  238. static uint32_t
  239. pack_aux(uint8_t *src, int src_bytes)
  240. {
  241. int i;
  242. uint32_t v = 0;
  243. if (src_bytes > 4)
  244. src_bytes = 4;
  245. for (i = 0; i < src_bytes; i++)
  246. v |= ((uint32_t) src[i]) << ((3-i) * 8);
  247. return v;
  248. }
  249. static void
  250. unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
  251. {
  252. int i;
  253. if (dst_bytes > 4)
  254. dst_bytes = 4;
  255. for (i = 0; i < dst_bytes; i++)
  256. dst[i] = src >> ((3-i) * 8);
  257. }
  258. /* hrawclock is 1/4 the FSB frequency */
  259. static int
  260. intel_hrawclk(struct drm_device *dev)
  261. {
  262. struct drm_i915_private *dev_priv = dev->dev_private;
  263. uint32_t clkcfg;
  264. clkcfg = I915_READ(CLKCFG);
  265. switch (clkcfg & CLKCFG_FSB_MASK) {
  266. case CLKCFG_FSB_400:
  267. return 100;
  268. case CLKCFG_FSB_533:
  269. return 133;
  270. case CLKCFG_FSB_667:
  271. return 166;
  272. case CLKCFG_FSB_800:
  273. return 200;
  274. case CLKCFG_FSB_1067:
  275. return 266;
  276. case CLKCFG_FSB_1333:
  277. return 333;
  278. /* these two are just a guess; one of them might be right */
  279. case CLKCFG_FSB_1600:
  280. case CLKCFG_FSB_1600_ALT:
  281. return 400;
  282. default:
  283. return 133;
  284. }
  285. }
  286. static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
  287. {
  288. struct drm_device *dev = intel_dp->base.base.dev;
  289. struct drm_i915_private *dev_priv = dev->dev_private;
  290. return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
  291. }
  292. static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
  293. {
  294. struct drm_device *dev = intel_dp->base.base.dev;
  295. struct drm_i915_private *dev_priv = dev->dev_private;
  296. return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
  297. }
  298. static void
  299. intel_dp_check_edp(struct intel_dp *intel_dp)
  300. {
  301. struct drm_device *dev = intel_dp->base.base.dev;
  302. struct drm_i915_private *dev_priv = dev->dev_private;
  303. if (!is_edp(intel_dp))
  304. return;
  305. if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
  306. WARN(1, "eDP powered off while attempting aux channel communication.\n");
  307. DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
  308. I915_READ(PCH_PP_STATUS),
  309. I915_READ(PCH_PP_CONTROL));
  310. }
  311. }
  312. static int
  313. intel_dp_aux_ch(struct intel_dp *intel_dp,
  314. uint8_t *send, int send_bytes,
  315. uint8_t *recv, int recv_size)
  316. {
  317. uint32_t output_reg = intel_dp->output_reg;
  318. struct drm_device *dev = intel_dp->base.base.dev;
  319. struct drm_i915_private *dev_priv = dev->dev_private;
  320. uint32_t ch_ctl = output_reg + 0x10;
  321. uint32_t ch_data = ch_ctl + 4;
  322. int i;
  323. int recv_bytes;
  324. uint32_t status;
  325. uint32_t aux_clock_divider;
  326. int try, precharge = 5;
  327. intel_dp_check_edp(intel_dp);
  328. /* The clock divider is based off the hrawclk,
  329. * and would like to run at 2MHz. So, take the
  330. * hrawclk value and divide by 2 and use that
  331. *
  332. * Note that PCH attached eDP panels should use a 125MHz input
  333. * clock divider.
  334. */
  335. if (is_cpu_edp(intel_dp)) {
  336. if (IS_GEN6(dev) || IS_GEN7(dev))
  337. aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
  338. else
  339. aux_clock_divider = 225; /* eDP input clock at 450Mhz */
  340. } else if (HAS_PCH_SPLIT(dev))
  341. aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
  342. else
  343. aux_clock_divider = intel_hrawclk(dev) / 2;
  344. /* Try to wait for any previous AUX channel activity */
  345. for (try = 0; try < 3; try++) {
  346. status = I915_READ(ch_ctl);
  347. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  348. break;
  349. msleep(1);
  350. }
  351. if (try == 3) {
  352. WARN(1, "dp_aux_ch not started status 0x%08x\n",
  353. I915_READ(ch_ctl));
  354. return -EBUSY;
  355. }
  356. /* Must try at least 3 times according to DP spec */
  357. for (try = 0; try < 5; try++) {
  358. /* Load the send data into the aux channel data registers */
  359. for (i = 0; i < send_bytes; i += 4)
  360. I915_WRITE(ch_data + i,
  361. pack_aux(send + i, send_bytes - i));
  362. /* Send the command and wait for it to complete */
  363. I915_WRITE(ch_ctl,
  364. DP_AUX_CH_CTL_SEND_BUSY |
  365. DP_AUX_CH_CTL_TIME_OUT_400us |
  366. (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  367. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  368. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
  369. DP_AUX_CH_CTL_DONE |
  370. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  371. DP_AUX_CH_CTL_RECEIVE_ERROR);
  372. for (;;) {
  373. status = I915_READ(ch_ctl);
  374. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  375. break;
  376. udelay(100);
  377. }
  378. /* Clear done status and any errors */
  379. I915_WRITE(ch_ctl,
  380. status |
  381. DP_AUX_CH_CTL_DONE |
  382. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  383. DP_AUX_CH_CTL_RECEIVE_ERROR);
  384. if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
  385. DP_AUX_CH_CTL_RECEIVE_ERROR))
  386. continue;
  387. if (status & DP_AUX_CH_CTL_DONE)
  388. break;
  389. }
  390. if ((status & DP_AUX_CH_CTL_DONE) == 0) {
  391. DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
  392. return -EBUSY;
  393. }
  394. /* Check for timeout or receive error.
  395. * Timeouts occur when the sink is not connected
  396. */
  397. if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
  398. DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
  399. return -EIO;
  400. }
  401. /* Timeouts occur when the device isn't connected, so they're
  402. * "normal" -- don't fill the kernel log with these */
  403. if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
  404. DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
  405. return -ETIMEDOUT;
  406. }
  407. /* Unload any bytes sent back from the other side */
  408. recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
  409. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
  410. if (recv_bytes > recv_size)
  411. recv_bytes = recv_size;
  412. for (i = 0; i < recv_bytes; i += 4)
  413. unpack_aux(I915_READ(ch_data + i),
  414. recv + i, recv_bytes - i);
  415. return recv_bytes;
  416. }
  417. /* Write data to the aux channel in native mode */
  418. static int
  419. intel_dp_aux_native_write(struct intel_dp *intel_dp,
  420. uint16_t address, uint8_t *send, int send_bytes)
  421. {
  422. int ret;
  423. uint8_t msg[20];
  424. int msg_bytes;
  425. uint8_t ack;
  426. intel_dp_check_edp(intel_dp);
  427. if (send_bytes > 16)
  428. return -1;
  429. msg[0] = AUX_NATIVE_WRITE << 4;
  430. msg[1] = address >> 8;
  431. msg[2] = address & 0xff;
  432. msg[3] = send_bytes - 1;
  433. memcpy(&msg[4], send, send_bytes);
  434. msg_bytes = send_bytes + 4;
  435. for (;;) {
  436. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
  437. if (ret < 0)
  438. return ret;
  439. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  440. break;
  441. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  442. udelay(100);
  443. else
  444. return -EIO;
  445. }
  446. return send_bytes;
  447. }
  448. /* Write a single byte to the aux channel in native mode */
  449. static int
  450. intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
  451. uint16_t address, uint8_t byte)
  452. {
  453. return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
  454. }
  455. /* read bytes from a native aux channel */
  456. static int
  457. intel_dp_aux_native_read(struct intel_dp *intel_dp,
  458. uint16_t address, uint8_t *recv, int recv_bytes)
  459. {
  460. uint8_t msg[4];
  461. int msg_bytes;
  462. uint8_t reply[20];
  463. int reply_bytes;
  464. uint8_t ack;
  465. int ret;
  466. intel_dp_check_edp(intel_dp);
  467. msg[0] = AUX_NATIVE_READ << 4;
  468. msg[1] = address >> 8;
  469. msg[2] = address & 0xff;
  470. msg[3] = recv_bytes - 1;
  471. msg_bytes = 4;
  472. reply_bytes = recv_bytes + 1;
  473. for (;;) {
  474. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
  475. reply, reply_bytes);
  476. if (ret == 0)
  477. return -EPROTO;
  478. if (ret < 0)
  479. return ret;
  480. ack = reply[0];
  481. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
  482. memcpy(recv, reply + 1, ret - 1);
  483. return ret - 1;
  484. }
  485. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  486. udelay(100);
  487. else
  488. return -EIO;
  489. }
  490. }
  491. static int
  492. intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  493. uint8_t write_byte, uint8_t *read_byte)
  494. {
  495. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  496. struct intel_dp *intel_dp = container_of(adapter,
  497. struct intel_dp,
  498. adapter);
  499. uint16_t address = algo_data->address;
  500. uint8_t msg[5];
  501. uint8_t reply[2];
  502. unsigned retry;
  503. int msg_bytes;
  504. int reply_bytes;
  505. int ret;
  506. intel_dp_check_edp(intel_dp);
  507. /* Set up the command byte */
  508. if (mode & MODE_I2C_READ)
  509. msg[0] = AUX_I2C_READ << 4;
  510. else
  511. msg[0] = AUX_I2C_WRITE << 4;
  512. if (!(mode & MODE_I2C_STOP))
  513. msg[0] |= AUX_I2C_MOT << 4;
  514. msg[1] = address >> 8;
  515. msg[2] = address;
  516. switch (mode) {
  517. case MODE_I2C_WRITE:
  518. msg[3] = 0;
  519. msg[4] = write_byte;
  520. msg_bytes = 5;
  521. reply_bytes = 1;
  522. break;
  523. case MODE_I2C_READ:
  524. msg[3] = 0;
  525. msg_bytes = 4;
  526. reply_bytes = 2;
  527. break;
  528. default:
  529. msg_bytes = 3;
  530. reply_bytes = 1;
  531. break;
  532. }
  533. for (retry = 0; retry < 5; retry++) {
  534. ret = intel_dp_aux_ch(intel_dp,
  535. msg, msg_bytes,
  536. reply, reply_bytes);
  537. if (ret < 0) {
  538. DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
  539. return ret;
  540. }
  541. switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
  542. case AUX_NATIVE_REPLY_ACK:
  543. /* I2C-over-AUX Reply field is only valid
  544. * when paired with AUX ACK.
  545. */
  546. break;
  547. case AUX_NATIVE_REPLY_NACK:
  548. DRM_DEBUG_KMS("aux_ch native nack\n");
  549. return -EREMOTEIO;
  550. case AUX_NATIVE_REPLY_DEFER:
  551. udelay(100);
  552. continue;
  553. default:
  554. DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
  555. reply[0]);
  556. return -EREMOTEIO;
  557. }
  558. switch (reply[0] & AUX_I2C_REPLY_MASK) {
  559. case AUX_I2C_REPLY_ACK:
  560. if (mode == MODE_I2C_READ) {
  561. *read_byte = reply[1];
  562. }
  563. return reply_bytes - 1;
  564. case AUX_I2C_REPLY_NACK:
  565. DRM_DEBUG_KMS("aux_i2c nack\n");
  566. return -EREMOTEIO;
  567. case AUX_I2C_REPLY_DEFER:
  568. DRM_DEBUG_KMS("aux_i2c defer\n");
  569. udelay(100);
  570. break;
  571. default:
  572. DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
  573. return -EREMOTEIO;
  574. }
  575. }
  576. DRM_ERROR("too many retries, giving up\n");
  577. return -EREMOTEIO;
  578. }
  579. static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
  580. static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  581. static int
  582. intel_dp_i2c_init(struct intel_dp *intel_dp,
  583. struct intel_connector *intel_connector, const char *name)
  584. {
  585. int ret;
  586. DRM_DEBUG_KMS("i2c_init %s\n", name);
  587. intel_dp->algo.running = false;
  588. intel_dp->algo.address = 0;
  589. intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
  590. memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
  591. intel_dp->adapter.owner = THIS_MODULE;
  592. intel_dp->adapter.class = I2C_CLASS_DDC;
  593. strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
  594. intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
  595. intel_dp->adapter.algo_data = &intel_dp->algo;
  596. intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
  597. ironlake_edp_panel_vdd_on(intel_dp);
  598. ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
  599. ironlake_edp_panel_vdd_off(intel_dp, false);
  600. return ret;
  601. }
  602. static bool
  603. intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
  604. struct drm_display_mode *adjusted_mode)
  605. {
  606. struct drm_device *dev = encoder->dev;
  607. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  608. int lane_count, clock;
  609. int max_lane_count = intel_dp_max_lane_count(intel_dp);
  610. int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
  611. int bpp, mode_rate;
  612. static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
  613. if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
  614. intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
  615. intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
  616. mode, adjusted_mode);
  617. /*
  618. * the mode->clock is used to calculate the Data&Link M/N
  619. * of the pipe. For the eDP the fixed clock should be used.
  620. */
  621. mode->clock = intel_dp->panel_fixed_mode->clock;
  622. }
  623. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  624. return false;
  625. DRM_DEBUG_KMS("DP link computation with max lane count %i "
  626. "max bw %02x pixel clock %iKHz\n",
  627. max_lane_count, bws[max_clock], mode->clock);
  628. if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
  629. return false;
  630. bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
  631. mode_rate = intel_dp_link_required(mode->clock, bpp);
  632. for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
  633. for (clock = 0; clock <= max_clock; clock++) {
  634. int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
  635. if (mode_rate <= link_avail) {
  636. intel_dp->link_bw = bws[clock];
  637. intel_dp->lane_count = lane_count;
  638. adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
  639. DRM_DEBUG_KMS("DP link bw %02x lane "
  640. "count %d clock %d bpp %d\n",
  641. intel_dp->link_bw, intel_dp->lane_count,
  642. adjusted_mode->clock, bpp);
  643. DRM_DEBUG_KMS("DP link bw required %i available %i\n",
  644. mode_rate, link_avail);
  645. return true;
  646. }
  647. }
  648. }
  649. return false;
  650. }
  651. struct intel_dp_m_n {
  652. uint32_t tu;
  653. uint32_t gmch_m;
  654. uint32_t gmch_n;
  655. uint32_t link_m;
  656. uint32_t link_n;
  657. };
  658. static void
  659. intel_reduce_ratio(uint32_t *num, uint32_t *den)
  660. {
  661. while (*num > 0xffffff || *den > 0xffffff) {
  662. *num >>= 1;
  663. *den >>= 1;
  664. }
  665. }
  666. static void
  667. intel_dp_compute_m_n(int bpp,
  668. int nlanes,
  669. int pixel_clock,
  670. int link_clock,
  671. struct intel_dp_m_n *m_n)
  672. {
  673. m_n->tu = 64;
  674. m_n->gmch_m = (pixel_clock * bpp) >> 3;
  675. m_n->gmch_n = link_clock * nlanes;
  676. intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  677. m_n->link_m = pixel_clock;
  678. m_n->link_n = link_clock;
  679. intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
  680. }
  681. void
  682. intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
  683. struct drm_display_mode *adjusted_mode)
  684. {
  685. struct drm_device *dev = crtc->dev;
  686. struct drm_mode_config *mode_config = &dev->mode_config;
  687. struct drm_encoder *encoder;
  688. struct drm_i915_private *dev_priv = dev->dev_private;
  689. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  690. int lane_count = 4;
  691. struct intel_dp_m_n m_n;
  692. int pipe = intel_crtc->pipe;
  693. /*
  694. * Find the lane count in the intel_encoder private
  695. */
  696. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  697. struct intel_dp *intel_dp;
  698. if (encoder->crtc != crtc)
  699. continue;
  700. intel_dp = enc_to_intel_dp(encoder);
  701. if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
  702. intel_dp->base.type == INTEL_OUTPUT_EDP)
  703. {
  704. lane_count = intel_dp->lane_count;
  705. break;
  706. }
  707. }
  708. /*
  709. * Compute the GMCH and Link ratios. The '3' here is
  710. * the number of bytes_per_pixel post-LUT, which we always
  711. * set up for 8-bits of R/G/B, or 3 bytes total.
  712. */
  713. intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
  714. mode->clock, adjusted_mode->clock, &m_n);
  715. if (HAS_PCH_SPLIT(dev)) {
  716. I915_WRITE(TRANSDATA_M1(pipe),
  717. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  718. m_n.gmch_m);
  719. I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
  720. I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
  721. I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
  722. } else {
  723. I915_WRITE(PIPE_GMCH_DATA_M(pipe),
  724. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  725. m_n.gmch_m);
  726. I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
  727. I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
  728. I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
  729. }
  730. }
  731. static void ironlake_edp_pll_on(struct drm_encoder *encoder);
  732. static void ironlake_edp_pll_off(struct drm_encoder *encoder);
  733. static void
  734. intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
  735. struct drm_display_mode *adjusted_mode)
  736. {
  737. struct drm_device *dev = encoder->dev;
  738. struct drm_i915_private *dev_priv = dev->dev_private;
  739. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  740. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  741. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  742. /* Turn on the eDP PLL if needed */
  743. if (is_edp(intel_dp)) {
  744. if (!is_pch_edp(intel_dp))
  745. ironlake_edp_pll_on(encoder);
  746. else
  747. ironlake_edp_pll_off(encoder);
  748. }
  749. /*
  750. * There are four kinds of DP registers:
  751. *
  752. * IBX PCH
  753. * SNB CPU
  754. * IVB CPU
  755. * CPT PCH
  756. *
  757. * IBX PCH and CPU are the same for almost everything,
  758. * except that the CPU DP PLL is configured in this
  759. * register
  760. *
  761. * CPT PCH is quite different, having many bits moved
  762. * to the TRANS_DP_CTL register instead. That
  763. * configuration happens (oddly) in ironlake_pch_enable
  764. */
  765. /* Preserve the BIOS-computed detected bit. This is
  766. * supposed to be read-only.
  767. */
  768. intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
  769. intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  770. /* Handle DP bits in common between all three register formats */
  771. intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  772. switch (intel_dp->lane_count) {
  773. case 1:
  774. intel_dp->DP |= DP_PORT_WIDTH_1;
  775. break;
  776. case 2:
  777. intel_dp->DP |= DP_PORT_WIDTH_2;
  778. break;
  779. case 4:
  780. intel_dp->DP |= DP_PORT_WIDTH_4;
  781. break;
  782. }
  783. if (intel_dp->has_audio) {
  784. DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
  785. pipe_name(intel_crtc->pipe));
  786. intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
  787. intel_write_eld(encoder, adjusted_mode);
  788. }
  789. memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
  790. intel_dp->link_configuration[0] = intel_dp->link_bw;
  791. intel_dp->link_configuration[1] = intel_dp->lane_count;
  792. intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
  793. /*
  794. * Check for DPCD version > 1.1 and enhanced framing support
  795. */
  796. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  797. (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
  798. intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  799. }
  800. /* Split out the IBX/CPU vs CPT settings */
  801. if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
  802. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  803. intel_dp->DP |= DP_SYNC_HS_HIGH;
  804. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  805. intel_dp->DP |= DP_SYNC_VS_HIGH;
  806. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  807. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  808. intel_dp->DP |= DP_ENHANCED_FRAMING;
  809. intel_dp->DP |= intel_crtc->pipe << 29;
  810. /* don't miss out required setting for eDP */
  811. intel_dp->DP |= DP_PLL_ENABLE;
  812. if (adjusted_mode->clock < 200000)
  813. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  814. else
  815. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  816. } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
  817. intel_dp->DP |= intel_dp->color_range;
  818. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  819. intel_dp->DP |= DP_SYNC_HS_HIGH;
  820. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  821. intel_dp->DP |= DP_SYNC_VS_HIGH;
  822. intel_dp->DP |= DP_LINK_TRAIN_OFF;
  823. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  824. intel_dp->DP |= DP_ENHANCED_FRAMING;
  825. if (intel_crtc->pipe == 1)
  826. intel_dp->DP |= DP_PIPEB_SELECT;
  827. if (is_cpu_edp(intel_dp)) {
  828. /* don't miss out required setting for eDP */
  829. intel_dp->DP |= DP_PLL_ENABLE;
  830. if (adjusted_mode->clock < 200000)
  831. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  832. else
  833. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  834. }
  835. } else {
  836. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  837. }
  838. }
  839. #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  840. #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
  841. #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  842. #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  843. #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
  844. #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  845. static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
  846. u32 mask,
  847. u32 value)
  848. {
  849. struct drm_device *dev = intel_dp->base.base.dev;
  850. struct drm_i915_private *dev_priv = dev->dev_private;
  851. DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
  852. mask, value,
  853. I915_READ(PCH_PP_STATUS),
  854. I915_READ(PCH_PP_CONTROL));
  855. if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
  856. DRM_ERROR("Panel status timeout: status %08x control %08x\n",
  857. I915_READ(PCH_PP_STATUS),
  858. I915_READ(PCH_PP_CONTROL));
  859. }
  860. }
  861. static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
  862. {
  863. DRM_DEBUG_KMS("Wait for panel power on\n");
  864. ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
  865. }
  866. static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
  867. {
  868. DRM_DEBUG_KMS("Wait for panel power off time\n");
  869. ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
  870. }
  871. static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
  872. {
  873. DRM_DEBUG_KMS("Wait for panel power cycle\n");
  874. ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
  875. }
  876. /* Read the current pp_control value, unlocking the register if it
  877. * is locked
  878. */
  879. static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
  880. {
  881. u32 control = I915_READ(PCH_PP_CONTROL);
  882. control &= ~PANEL_UNLOCK_MASK;
  883. control |= PANEL_UNLOCK_REGS;
  884. return control;
  885. }
  886. static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
  887. {
  888. struct drm_device *dev = intel_dp->base.base.dev;
  889. struct drm_i915_private *dev_priv = dev->dev_private;
  890. u32 pp;
  891. if (!is_edp(intel_dp))
  892. return;
  893. DRM_DEBUG_KMS("Turn eDP VDD on\n");
  894. WARN(intel_dp->want_panel_vdd,
  895. "eDP VDD already requested on\n");
  896. intel_dp->want_panel_vdd = true;
  897. if (ironlake_edp_have_panel_vdd(intel_dp)) {
  898. DRM_DEBUG_KMS("eDP VDD already on\n");
  899. return;
  900. }
  901. if (!ironlake_edp_have_panel_power(intel_dp))
  902. ironlake_wait_panel_power_cycle(intel_dp);
  903. pp = ironlake_get_pp_control(dev_priv);
  904. pp |= EDP_FORCE_VDD;
  905. I915_WRITE(PCH_PP_CONTROL, pp);
  906. POSTING_READ(PCH_PP_CONTROL);
  907. DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
  908. I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
  909. /*
  910. * If the panel wasn't on, delay before accessing aux channel
  911. */
  912. if (!ironlake_edp_have_panel_power(intel_dp)) {
  913. DRM_DEBUG_KMS("eDP was not running\n");
  914. msleep(intel_dp->panel_power_up_delay);
  915. }
  916. }
  917. static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
  918. {
  919. struct drm_device *dev = intel_dp->base.base.dev;
  920. struct drm_i915_private *dev_priv = dev->dev_private;
  921. u32 pp;
  922. if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
  923. pp = ironlake_get_pp_control(dev_priv);
  924. pp &= ~EDP_FORCE_VDD;
  925. I915_WRITE(PCH_PP_CONTROL, pp);
  926. POSTING_READ(PCH_PP_CONTROL);
  927. /* Make sure sequencer is idle before allowing subsequent activity */
  928. DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
  929. I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
  930. msleep(intel_dp->panel_power_down_delay);
  931. }
  932. }
  933. static void ironlake_panel_vdd_work(struct work_struct *__work)
  934. {
  935. struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
  936. struct intel_dp, panel_vdd_work);
  937. struct drm_device *dev = intel_dp->base.base.dev;
  938. mutex_lock(&dev->mode_config.mutex);
  939. ironlake_panel_vdd_off_sync(intel_dp);
  940. mutex_unlock(&dev->mode_config.mutex);
  941. }
  942. static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
  943. {
  944. if (!is_edp(intel_dp))
  945. return;
  946. DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
  947. WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
  948. intel_dp->want_panel_vdd = false;
  949. if (sync) {
  950. ironlake_panel_vdd_off_sync(intel_dp);
  951. } else {
  952. /*
  953. * Queue the timer to fire a long
  954. * time from now (relative to the power down delay)
  955. * to keep the panel power up across a sequence of operations
  956. */
  957. schedule_delayed_work(&intel_dp->panel_vdd_work,
  958. msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
  959. }
  960. }
  961. static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
  962. {
  963. struct drm_device *dev = intel_dp->base.base.dev;
  964. struct drm_i915_private *dev_priv = dev->dev_private;
  965. u32 pp;
  966. if (!is_edp(intel_dp))
  967. return;
  968. DRM_DEBUG_KMS("Turn eDP power on\n");
  969. if (ironlake_edp_have_panel_power(intel_dp)) {
  970. DRM_DEBUG_KMS("eDP power already on\n");
  971. return;
  972. }
  973. ironlake_wait_panel_power_cycle(intel_dp);
  974. pp = ironlake_get_pp_control(dev_priv);
  975. if (IS_GEN5(dev)) {
  976. /* ILK workaround: disable reset around power sequence */
  977. pp &= ~PANEL_POWER_RESET;
  978. I915_WRITE(PCH_PP_CONTROL, pp);
  979. POSTING_READ(PCH_PP_CONTROL);
  980. }
  981. pp |= POWER_TARGET_ON;
  982. if (!IS_GEN5(dev))
  983. pp |= PANEL_POWER_RESET;
  984. I915_WRITE(PCH_PP_CONTROL, pp);
  985. POSTING_READ(PCH_PP_CONTROL);
  986. ironlake_wait_panel_on(intel_dp);
  987. if (IS_GEN5(dev)) {
  988. pp |= PANEL_POWER_RESET; /* restore panel reset bit */
  989. I915_WRITE(PCH_PP_CONTROL, pp);
  990. POSTING_READ(PCH_PP_CONTROL);
  991. }
  992. }
  993. static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
  994. {
  995. struct drm_device *dev = intel_dp->base.base.dev;
  996. struct drm_i915_private *dev_priv = dev->dev_private;
  997. u32 pp;
  998. if (!is_edp(intel_dp))
  999. return;
  1000. DRM_DEBUG_KMS("Turn eDP power off\n");
  1001. WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
  1002. pp = ironlake_get_pp_control(dev_priv);
  1003. pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
  1004. I915_WRITE(PCH_PP_CONTROL, pp);
  1005. POSTING_READ(PCH_PP_CONTROL);
  1006. ironlake_wait_panel_off(intel_dp);
  1007. }
  1008. static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
  1009. {
  1010. struct drm_device *dev = intel_dp->base.base.dev;
  1011. struct drm_i915_private *dev_priv = dev->dev_private;
  1012. u32 pp;
  1013. if (!is_edp(intel_dp))
  1014. return;
  1015. DRM_DEBUG_KMS("\n");
  1016. /*
  1017. * If we enable the backlight right away following a panel power
  1018. * on, we may see slight flicker as the panel syncs with the eDP
  1019. * link. So delay a bit to make sure the image is solid before
  1020. * allowing it to appear.
  1021. */
  1022. msleep(intel_dp->backlight_on_delay);
  1023. pp = ironlake_get_pp_control(dev_priv);
  1024. pp |= EDP_BLC_ENABLE;
  1025. I915_WRITE(PCH_PP_CONTROL, pp);
  1026. POSTING_READ(PCH_PP_CONTROL);
  1027. }
  1028. static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
  1029. {
  1030. struct drm_device *dev = intel_dp->base.base.dev;
  1031. struct drm_i915_private *dev_priv = dev->dev_private;
  1032. u32 pp;
  1033. if (!is_edp(intel_dp))
  1034. return;
  1035. DRM_DEBUG_KMS("\n");
  1036. pp = ironlake_get_pp_control(dev_priv);
  1037. pp &= ~EDP_BLC_ENABLE;
  1038. I915_WRITE(PCH_PP_CONTROL, pp);
  1039. POSTING_READ(PCH_PP_CONTROL);
  1040. msleep(intel_dp->backlight_off_delay);
  1041. }
  1042. static void ironlake_edp_pll_on(struct drm_encoder *encoder)
  1043. {
  1044. struct drm_device *dev = encoder->dev;
  1045. struct drm_i915_private *dev_priv = dev->dev_private;
  1046. u32 dpa_ctl;
  1047. DRM_DEBUG_KMS("\n");
  1048. dpa_ctl = I915_READ(DP_A);
  1049. dpa_ctl |= DP_PLL_ENABLE;
  1050. I915_WRITE(DP_A, dpa_ctl);
  1051. POSTING_READ(DP_A);
  1052. udelay(200);
  1053. }
  1054. static void ironlake_edp_pll_off(struct drm_encoder *encoder)
  1055. {
  1056. struct drm_device *dev = encoder->dev;
  1057. struct drm_i915_private *dev_priv = dev->dev_private;
  1058. u32 dpa_ctl;
  1059. dpa_ctl = I915_READ(DP_A);
  1060. dpa_ctl &= ~DP_PLL_ENABLE;
  1061. I915_WRITE(DP_A, dpa_ctl);
  1062. POSTING_READ(DP_A);
  1063. udelay(200);
  1064. }
  1065. /* If the sink supports it, try to set the power state appropriately */
  1066. static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
  1067. {
  1068. int ret, i;
  1069. /* Should have a valid DPCD by this point */
  1070. if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
  1071. return;
  1072. if (mode != DRM_MODE_DPMS_ON) {
  1073. ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
  1074. DP_SET_POWER_D3);
  1075. if (ret != 1)
  1076. DRM_DEBUG_DRIVER("failed to write sink power state\n");
  1077. } else {
  1078. /*
  1079. * When turning on, we need to retry for 1ms to give the sink
  1080. * time to wake up.
  1081. */
  1082. for (i = 0; i < 3; i++) {
  1083. ret = intel_dp_aux_native_write_1(intel_dp,
  1084. DP_SET_POWER,
  1085. DP_SET_POWER_D0);
  1086. if (ret == 1)
  1087. break;
  1088. msleep(1);
  1089. }
  1090. }
  1091. }
  1092. static void intel_dp_prepare(struct drm_encoder *encoder)
  1093. {
  1094. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  1095. /* Make sure the panel is off before trying to change the mode. But also
  1096. * ensure that we have vdd while we switch off the panel. */
  1097. ironlake_edp_panel_vdd_on(intel_dp);
  1098. ironlake_edp_backlight_off(intel_dp);
  1099. ironlake_edp_panel_off(intel_dp);
  1100. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1101. intel_dp_link_down(intel_dp);
  1102. ironlake_edp_panel_vdd_off(intel_dp, false);
  1103. }
  1104. static void intel_dp_commit(struct drm_encoder *encoder)
  1105. {
  1106. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  1107. struct drm_device *dev = encoder->dev;
  1108. struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
  1109. ironlake_edp_panel_vdd_on(intel_dp);
  1110. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1111. intel_dp_start_link_train(intel_dp);
  1112. ironlake_edp_panel_on(intel_dp);
  1113. ironlake_edp_panel_vdd_off(intel_dp, true);
  1114. intel_dp_complete_link_train(intel_dp);
  1115. ironlake_edp_backlight_on(intel_dp);
  1116. intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
  1117. if (HAS_PCH_CPT(dev))
  1118. intel_cpt_verify_modeset(dev, intel_crtc->pipe);
  1119. }
  1120. static void
  1121. intel_dp_dpms(struct drm_encoder *encoder, int mode)
  1122. {
  1123. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  1124. struct drm_device *dev = encoder->dev;
  1125. struct drm_i915_private *dev_priv = dev->dev_private;
  1126. uint32_t dp_reg = I915_READ(intel_dp->output_reg);
  1127. if (mode != DRM_MODE_DPMS_ON) {
  1128. /* Switching the panel off requires vdd. */
  1129. ironlake_edp_panel_vdd_on(intel_dp);
  1130. ironlake_edp_backlight_off(intel_dp);
  1131. ironlake_edp_panel_off(intel_dp);
  1132. intel_dp_sink_dpms(intel_dp, mode);
  1133. intel_dp_link_down(intel_dp);
  1134. ironlake_edp_panel_vdd_off(intel_dp, false);
  1135. if (is_cpu_edp(intel_dp))
  1136. ironlake_edp_pll_off(encoder);
  1137. } else {
  1138. if (is_cpu_edp(intel_dp))
  1139. ironlake_edp_pll_on(encoder);
  1140. ironlake_edp_panel_vdd_on(intel_dp);
  1141. intel_dp_sink_dpms(intel_dp, mode);
  1142. if (!(dp_reg & DP_PORT_EN)) {
  1143. intel_dp_start_link_train(intel_dp);
  1144. ironlake_edp_panel_on(intel_dp);
  1145. ironlake_edp_panel_vdd_off(intel_dp, true);
  1146. intel_dp_complete_link_train(intel_dp);
  1147. } else
  1148. ironlake_edp_panel_vdd_off(intel_dp, false);
  1149. ironlake_edp_backlight_on(intel_dp);
  1150. }
  1151. intel_dp->dpms_mode = mode;
  1152. }
  1153. /*
  1154. * Native read with retry for link status and receiver capability reads for
  1155. * cases where the sink may still be asleep.
  1156. */
  1157. static bool
  1158. intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
  1159. uint8_t *recv, int recv_bytes)
  1160. {
  1161. int ret, i;
  1162. /*
  1163. * Sinks are *supposed* to come up within 1ms from an off state,
  1164. * but we're also supposed to retry 3 times per the spec.
  1165. */
  1166. for (i = 0; i < 3; i++) {
  1167. ret = intel_dp_aux_native_read(intel_dp, address, recv,
  1168. recv_bytes);
  1169. if (ret == recv_bytes)
  1170. return true;
  1171. msleep(1);
  1172. }
  1173. return false;
  1174. }
  1175. /*
  1176. * Fetch AUX CH registers 0x202 - 0x207 which contain
  1177. * link status information
  1178. */
  1179. static bool
  1180. intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1181. {
  1182. return intel_dp_aux_native_read_retry(intel_dp,
  1183. DP_LANE0_1_STATUS,
  1184. link_status,
  1185. DP_LINK_STATUS_SIZE);
  1186. }
  1187. static uint8_t
  1188. intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  1189. int r)
  1190. {
  1191. return link_status[r - DP_LANE0_1_STATUS];
  1192. }
  1193. static uint8_t
  1194. intel_get_adjust_request_voltage(uint8_t adjust_request[2],
  1195. int lane)
  1196. {
  1197. int s = ((lane & 1) ?
  1198. DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
  1199. DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
  1200. uint8_t l = adjust_request[lane>>1];
  1201. return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
  1202. }
  1203. static uint8_t
  1204. intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
  1205. int lane)
  1206. {
  1207. int s = ((lane & 1) ?
  1208. DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
  1209. DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
  1210. uint8_t l = adjust_request[lane>>1];
  1211. return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
  1212. }
  1213. #if 0
  1214. static char *voltage_names[] = {
  1215. "0.4V", "0.6V", "0.8V", "1.2V"
  1216. };
  1217. static char *pre_emph_names[] = {
  1218. "0dB", "3.5dB", "6dB", "9.5dB"
  1219. };
  1220. static char *link_train_names[] = {
  1221. "pattern 1", "pattern 2", "idle", "off"
  1222. };
  1223. #endif
  1224. /*
  1225. * These are source-specific values; current Intel hardware supports
  1226. * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  1227. */
  1228. static uint8_t
  1229. intel_dp_voltage_max(struct intel_dp *intel_dp)
  1230. {
  1231. struct drm_device *dev = intel_dp->base.base.dev;
  1232. if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
  1233. return DP_TRAIN_VOLTAGE_SWING_800;
  1234. else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
  1235. return DP_TRAIN_VOLTAGE_SWING_1200;
  1236. else
  1237. return DP_TRAIN_VOLTAGE_SWING_800;
  1238. }
  1239. static uint8_t
  1240. intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
  1241. {
  1242. struct drm_device *dev = intel_dp->base.base.dev;
  1243. if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
  1244. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1245. case DP_TRAIN_VOLTAGE_SWING_400:
  1246. return DP_TRAIN_PRE_EMPHASIS_6;
  1247. case DP_TRAIN_VOLTAGE_SWING_600:
  1248. case DP_TRAIN_VOLTAGE_SWING_800:
  1249. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1250. default:
  1251. return DP_TRAIN_PRE_EMPHASIS_0;
  1252. }
  1253. } else {
  1254. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1255. case DP_TRAIN_VOLTAGE_SWING_400:
  1256. return DP_TRAIN_PRE_EMPHASIS_6;
  1257. case DP_TRAIN_VOLTAGE_SWING_600:
  1258. return DP_TRAIN_PRE_EMPHASIS_6;
  1259. case DP_TRAIN_VOLTAGE_SWING_800:
  1260. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1261. case DP_TRAIN_VOLTAGE_SWING_1200:
  1262. default:
  1263. return DP_TRAIN_PRE_EMPHASIS_0;
  1264. }
  1265. }
  1266. }
  1267. static void
  1268. intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1269. {
  1270. uint8_t v = 0;
  1271. uint8_t p = 0;
  1272. int lane;
  1273. uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
  1274. uint8_t voltage_max;
  1275. uint8_t preemph_max;
  1276. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1277. uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
  1278. uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
  1279. if (this_v > v)
  1280. v = this_v;
  1281. if (this_p > p)
  1282. p = this_p;
  1283. }
  1284. voltage_max = intel_dp_voltage_max(intel_dp);
  1285. if (v >= voltage_max)
  1286. v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  1287. preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  1288. if (p >= preemph_max)
  1289. p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  1290. for (lane = 0; lane < 4; lane++)
  1291. intel_dp->train_set[lane] = v | p;
  1292. }
  1293. static uint32_t
  1294. intel_dp_signal_levels(uint8_t train_set)
  1295. {
  1296. uint32_t signal_levels = 0;
  1297. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1298. case DP_TRAIN_VOLTAGE_SWING_400:
  1299. default:
  1300. signal_levels |= DP_VOLTAGE_0_4;
  1301. break;
  1302. case DP_TRAIN_VOLTAGE_SWING_600:
  1303. signal_levels |= DP_VOLTAGE_0_6;
  1304. break;
  1305. case DP_TRAIN_VOLTAGE_SWING_800:
  1306. signal_levels |= DP_VOLTAGE_0_8;
  1307. break;
  1308. case DP_TRAIN_VOLTAGE_SWING_1200:
  1309. signal_levels |= DP_VOLTAGE_1_2;
  1310. break;
  1311. }
  1312. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  1313. case DP_TRAIN_PRE_EMPHASIS_0:
  1314. default:
  1315. signal_levels |= DP_PRE_EMPHASIS_0;
  1316. break;
  1317. case DP_TRAIN_PRE_EMPHASIS_3_5:
  1318. signal_levels |= DP_PRE_EMPHASIS_3_5;
  1319. break;
  1320. case DP_TRAIN_PRE_EMPHASIS_6:
  1321. signal_levels |= DP_PRE_EMPHASIS_6;
  1322. break;
  1323. case DP_TRAIN_PRE_EMPHASIS_9_5:
  1324. signal_levels |= DP_PRE_EMPHASIS_9_5;
  1325. break;
  1326. }
  1327. return signal_levels;
  1328. }
  1329. /* Gen6's DP voltage swing and pre-emphasis control */
  1330. static uint32_t
  1331. intel_gen6_edp_signal_levels(uint8_t train_set)
  1332. {
  1333. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1334. DP_TRAIN_PRE_EMPHASIS_MASK);
  1335. switch (signal_levels) {
  1336. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1337. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1338. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1339. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1340. return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
  1341. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1342. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1343. return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
  1344. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1345. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1346. return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
  1347. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1348. case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
  1349. return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
  1350. default:
  1351. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1352. "0x%x\n", signal_levels);
  1353. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1354. }
  1355. }
  1356. /* Gen7's DP voltage swing and pre-emphasis control */
  1357. static uint32_t
  1358. intel_gen7_edp_signal_levels(uint8_t train_set)
  1359. {
  1360. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1361. DP_TRAIN_PRE_EMPHASIS_MASK);
  1362. switch (signal_levels) {
  1363. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1364. return EDP_LINK_TRAIN_400MV_0DB_IVB;
  1365. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1366. return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
  1367. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1368. return EDP_LINK_TRAIN_400MV_6DB_IVB;
  1369. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1370. return EDP_LINK_TRAIN_600MV_0DB_IVB;
  1371. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1372. return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
  1373. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1374. return EDP_LINK_TRAIN_800MV_0DB_IVB;
  1375. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1376. return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
  1377. default:
  1378. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1379. "0x%x\n", signal_levels);
  1380. return EDP_LINK_TRAIN_500MV_0DB_IVB;
  1381. }
  1382. }
  1383. static uint8_t
  1384. intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  1385. int lane)
  1386. {
  1387. int s = (lane & 1) * 4;
  1388. uint8_t l = link_status[lane>>1];
  1389. return (l >> s) & 0xf;
  1390. }
  1391. /* Check for clock recovery is done on all channels */
  1392. static bool
  1393. intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
  1394. {
  1395. int lane;
  1396. uint8_t lane_status;
  1397. for (lane = 0; lane < lane_count; lane++) {
  1398. lane_status = intel_get_lane_status(link_status, lane);
  1399. if ((lane_status & DP_LANE_CR_DONE) == 0)
  1400. return false;
  1401. }
  1402. return true;
  1403. }
  1404. /* Check to see if channel eq is done on all channels */
  1405. #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
  1406. DP_LANE_CHANNEL_EQ_DONE|\
  1407. DP_LANE_SYMBOL_LOCKED)
  1408. static bool
  1409. intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1410. {
  1411. uint8_t lane_align;
  1412. uint8_t lane_status;
  1413. int lane;
  1414. lane_align = intel_dp_link_status(link_status,
  1415. DP_LANE_ALIGN_STATUS_UPDATED);
  1416. if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  1417. return false;
  1418. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1419. lane_status = intel_get_lane_status(link_status, lane);
  1420. if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
  1421. return false;
  1422. }
  1423. return true;
  1424. }
  1425. static bool
  1426. intel_dp_set_link_train(struct intel_dp *intel_dp,
  1427. uint32_t dp_reg_value,
  1428. uint8_t dp_train_pat)
  1429. {
  1430. struct drm_device *dev = intel_dp->base.base.dev;
  1431. struct drm_i915_private *dev_priv = dev->dev_private;
  1432. int ret;
  1433. I915_WRITE(intel_dp->output_reg, dp_reg_value);
  1434. POSTING_READ(intel_dp->output_reg);
  1435. intel_dp_aux_native_write_1(intel_dp,
  1436. DP_TRAINING_PATTERN_SET,
  1437. dp_train_pat);
  1438. ret = intel_dp_aux_native_write(intel_dp,
  1439. DP_TRAINING_LANE0_SET,
  1440. intel_dp->train_set,
  1441. intel_dp->lane_count);
  1442. if (ret != intel_dp->lane_count)
  1443. return false;
  1444. return true;
  1445. }
  1446. /* Enable corresponding port and start training pattern 1 */
  1447. static void
  1448. intel_dp_start_link_train(struct intel_dp *intel_dp)
  1449. {
  1450. struct drm_device *dev = intel_dp->base.base.dev;
  1451. struct drm_i915_private *dev_priv = dev->dev_private;
  1452. struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
  1453. int i;
  1454. uint8_t voltage;
  1455. bool clock_recovery = false;
  1456. int voltage_tries, loop_tries;
  1457. u32 reg;
  1458. uint32_t DP = intel_dp->DP;
  1459. /*
  1460. * On CPT we have to enable the port in training pattern 1, which
  1461. * will happen below in intel_dp_set_link_train. Otherwise, enable
  1462. * the port and wait for it to become active.
  1463. */
  1464. if (!HAS_PCH_CPT(dev)) {
  1465. I915_WRITE(intel_dp->output_reg, intel_dp->DP);
  1466. POSTING_READ(intel_dp->output_reg);
  1467. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1468. }
  1469. /* Write the link configuration data */
  1470. intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
  1471. intel_dp->link_configuration,
  1472. DP_LINK_CONFIGURATION_SIZE);
  1473. DP |= DP_PORT_EN;
  1474. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
  1475. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  1476. else
  1477. DP &= ~DP_LINK_TRAIN_MASK;
  1478. memset(intel_dp->train_set, 0, 4);
  1479. voltage = 0xff;
  1480. voltage_tries = 0;
  1481. loop_tries = 0;
  1482. clock_recovery = false;
  1483. for (;;) {
  1484. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  1485. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1486. uint32_t signal_levels;
  1487. if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
  1488. signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
  1489. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
  1490. } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
  1491. signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
  1492. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
  1493. } else {
  1494. signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
  1495. DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
  1496. DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
  1497. }
  1498. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
  1499. reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
  1500. else
  1501. reg = DP | DP_LINK_TRAIN_PAT_1;
  1502. if (!intel_dp_set_link_train(intel_dp, reg,
  1503. DP_TRAINING_PATTERN_1 |
  1504. DP_LINK_SCRAMBLING_DISABLE))
  1505. break;
  1506. /* Set training pattern 1 */
  1507. udelay(100);
  1508. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  1509. DRM_ERROR("failed to get link status\n");
  1510. break;
  1511. }
  1512. if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  1513. DRM_DEBUG_KMS("clock recovery OK\n");
  1514. clock_recovery = true;
  1515. break;
  1516. }
  1517. /* Check to see if we've tried the max voltage */
  1518. for (i = 0; i < intel_dp->lane_count; i++)
  1519. if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  1520. break;
  1521. if (i == intel_dp->lane_count) {
  1522. ++loop_tries;
  1523. if (loop_tries == 5) {
  1524. DRM_DEBUG_KMS("too many full retries, give up\n");
  1525. break;
  1526. }
  1527. memset(intel_dp->train_set, 0, 4);
  1528. voltage_tries = 0;
  1529. continue;
  1530. }
  1531. /* Check to see if we've tried the same voltage 5 times */
  1532. if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  1533. ++voltage_tries;
  1534. if (voltage_tries == 5) {
  1535. DRM_DEBUG_KMS("too many voltage retries, give up\n");
  1536. break;
  1537. }
  1538. } else
  1539. voltage_tries = 0;
  1540. voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  1541. /* Compute new intel_dp->train_set as requested by target */
  1542. intel_get_adjust_train(intel_dp, link_status);
  1543. }
  1544. intel_dp->DP = DP;
  1545. }
  1546. static void
  1547. intel_dp_complete_link_train(struct intel_dp *intel_dp)
  1548. {
  1549. struct drm_device *dev = intel_dp->base.base.dev;
  1550. struct drm_i915_private *dev_priv = dev->dev_private;
  1551. bool channel_eq = false;
  1552. int tries, cr_tries;
  1553. u32 reg;
  1554. uint32_t DP = intel_dp->DP;
  1555. /* channel equalization */
  1556. tries = 0;
  1557. cr_tries = 0;
  1558. channel_eq = false;
  1559. for (;;) {
  1560. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  1561. uint32_t signal_levels;
  1562. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1563. if (cr_tries > 5) {
  1564. DRM_ERROR("failed to train DP, aborting\n");
  1565. intel_dp_link_down(intel_dp);
  1566. break;
  1567. }
  1568. if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
  1569. signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
  1570. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
  1571. } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
  1572. signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
  1573. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
  1574. } else {
  1575. signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
  1576. DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
  1577. }
  1578. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
  1579. reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
  1580. else
  1581. reg = DP | DP_LINK_TRAIN_PAT_2;
  1582. /* channel eq pattern */
  1583. if (!intel_dp_set_link_train(intel_dp, reg,
  1584. DP_TRAINING_PATTERN_2 |
  1585. DP_LINK_SCRAMBLING_DISABLE))
  1586. break;
  1587. udelay(400);
  1588. if (!intel_dp_get_link_status(intel_dp, link_status))
  1589. break;
  1590. /* Make sure clock is still ok */
  1591. if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  1592. intel_dp_start_link_train(intel_dp);
  1593. cr_tries++;
  1594. continue;
  1595. }
  1596. if (intel_channel_eq_ok(intel_dp, link_status)) {
  1597. channel_eq = true;
  1598. break;
  1599. }
  1600. /* Try 5 times, then try clock recovery if that fails */
  1601. if (tries > 5) {
  1602. intel_dp_link_down(intel_dp);
  1603. intel_dp_start_link_train(intel_dp);
  1604. tries = 0;
  1605. cr_tries++;
  1606. continue;
  1607. }
  1608. /* Compute new intel_dp->train_set as requested by target */
  1609. intel_get_adjust_train(intel_dp, link_status);
  1610. ++tries;
  1611. }
  1612. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
  1613. reg = DP | DP_LINK_TRAIN_OFF_CPT;
  1614. else
  1615. reg = DP | DP_LINK_TRAIN_OFF;
  1616. I915_WRITE(intel_dp->output_reg, reg);
  1617. POSTING_READ(intel_dp->output_reg);
  1618. intel_dp_aux_native_write_1(intel_dp,
  1619. DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
  1620. }
  1621. static void
  1622. intel_dp_link_down(struct intel_dp *intel_dp)
  1623. {
  1624. struct drm_device *dev = intel_dp->base.base.dev;
  1625. struct drm_i915_private *dev_priv = dev->dev_private;
  1626. uint32_t DP = intel_dp->DP;
  1627. if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
  1628. return;
  1629. DRM_DEBUG_KMS("\n");
  1630. if (is_edp(intel_dp)) {
  1631. DP &= ~DP_PLL_ENABLE;
  1632. I915_WRITE(intel_dp->output_reg, DP);
  1633. POSTING_READ(intel_dp->output_reg);
  1634. udelay(100);
  1635. }
  1636. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
  1637. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  1638. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
  1639. } else {
  1640. DP &= ~DP_LINK_TRAIN_MASK;
  1641. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
  1642. }
  1643. POSTING_READ(intel_dp->output_reg);
  1644. msleep(17);
  1645. if (is_edp(intel_dp)) {
  1646. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
  1647. DP |= DP_LINK_TRAIN_OFF_CPT;
  1648. else
  1649. DP |= DP_LINK_TRAIN_OFF;
  1650. }
  1651. if (!HAS_PCH_CPT(dev) &&
  1652. I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
  1653. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  1654. /* Hardware workaround: leaving our transcoder select
  1655. * set to transcoder B while it's off will prevent the
  1656. * corresponding HDMI output on transcoder A.
  1657. *
  1658. * Combine this with another hardware workaround:
  1659. * transcoder select bit can only be cleared while the
  1660. * port is enabled.
  1661. */
  1662. DP &= ~DP_PIPEB_SELECT;
  1663. I915_WRITE(intel_dp->output_reg, DP);
  1664. /* Changes to enable or select take place the vblank
  1665. * after being written.
  1666. */
  1667. if (crtc == NULL) {
  1668. /* We can arrive here never having been attached
  1669. * to a CRTC, for instance, due to inheriting
  1670. * random state from the BIOS.
  1671. *
  1672. * If the pipe is not running, play safe and
  1673. * wait for the clocks to stabilise before
  1674. * continuing.
  1675. */
  1676. POSTING_READ(intel_dp->output_reg);
  1677. msleep(50);
  1678. } else
  1679. intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
  1680. }
  1681. DP &= ~DP_AUDIO_OUTPUT_ENABLE;
  1682. I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
  1683. POSTING_READ(intel_dp->output_reg);
  1684. msleep(intel_dp->panel_power_down_delay);
  1685. }
  1686. static bool
  1687. intel_dp_get_dpcd(struct intel_dp *intel_dp)
  1688. {
  1689. if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
  1690. sizeof(intel_dp->dpcd)) &&
  1691. (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
  1692. return true;
  1693. }
  1694. return false;
  1695. }
  1696. static void
  1697. intel_dp_probe_oui(struct intel_dp *intel_dp)
  1698. {
  1699. u8 buf[3];
  1700. if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  1701. return;
  1702. ironlake_edp_panel_vdd_on(intel_dp);
  1703. if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
  1704. DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
  1705. buf[0], buf[1], buf[2]);
  1706. if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
  1707. DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
  1708. buf[0], buf[1], buf[2]);
  1709. ironlake_edp_panel_vdd_off(intel_dp, false);
  1710. }
  1711. static bool
  1712. intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
  1713. {
  1714. int ret;
  1715. ret = intel_dp_aux_native_read_retry(intel_dp,
  1716. DP_DEVICE_SERVICE_IRQ_VECTOR,
  1717. sink_irq_vector, 1);
  1718. if (!ret)
  1719. return false;
  1720. return true;
  1721. }
  1722. static void
  1723. intel_dp_handle_test_request(struct intel_dp *intel_dp)
  1724. {
  1725. /* NAK by default */
  1726. intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
  1727. }
  1728. /*
  1729. * According to DP spec
  1730. * 5.1.2:
  1731. * 1. Read DPCD
  1732. * 2. Configure link according to Receiver Capabilities
  1733. * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
  1734. * 4. Check link status on receipt of hot-plug interrupt
  1735. */
  1736. static void
  1737. intel_dp_check_link_status(struct intel_dp *intel_dp)
  1738. {
  1739. u8 sink_irq_vector;
  1740. u8 link_status[DP_LINK_STATUS_SIZE];
  1741. if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
  1742. return;
  1743. if (!intel_dp->base.base.crtc)
  1744. return;
  1745. /* Try to read receiver status if the link appears to be up */
  1746. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  1747. intel_dp_link_down(intel_dp);
  1748. return;
  1749. }
  1750. /* Now read the DPCD to see if it's actually running */
  1751. if (!intel_dp_get_dpcd(intel_dp)) {
  1752. intel_dp_link_down(intel_dp);
  1753. return;
  1754. }
  1755. /* Try to read the source of the interrupt */
  1756. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  1757. intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
  1758. /* Clear interrupt source */
  1759. intel_dp_aux_native_write_1(intel_dp,
  1760. DP_DEVICE_SERVICE_IRQ_VECTOR,
  1761. sink_irq_vector);
  1762. if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
  1763. intel_dp_handle_test_request(intel_dp);
  1764. if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
  1765. DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
  1766. }
  1767. if (!intel_channel_eq_ok(intel_dp, link_status)) {
  1768. DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
  1769. drm_get_encoder_name(&intel_dp->base.base));
  1770. intel_dp_start_link_train(intel_dp);
  1771. intel_dp_complete_link_train(intel_dp);
  1772. }
  1773. }
  1774. static enum drm_connector_status
  1775. intel_dp_detect_dpcd(struct intel_dp *intel_dp)
  1776. {
  1777. if (intel_dp_get_dpcd(intel_dp))
  1778. return connector_status_connected;
  1779. return connector_status_disconnected;
  1780. }
  1781. static enum drm_connector_status
  1782. ironlake_dp_detect(struct intel_dp *intel_dp)
  1783. {
  1784. enum drm_connector_status status;
  1785. /* Can't disconnect eDP, but you can close the lid... */
  1786. if (is_edp(intel_dp)) {
  1787. status = intel_panel_detect(intel_dp->base.base.dev);
  1788. if (status == connector_status_unknown)
  1789. status = connector_status_connected;
  1790. return status;
  1791. }
  1792. return intel_dp_detect_dpcd(intel_dp);
  1793. }
  1794. static enum drm_connector_status
  1795. g4x_dp_detect(struct intel_dp *intel_dp)
  1796. {
  1797. struct drm_device *dev = intel_dp->base.base.dev;
  1798. struct drm_i915_private *dev_priv = dev->dev_private;
  1799. uint32_t temp, bit;
  1800. switch (intel_dp->output_reg) {
  1801. case DP_B:
  1802. bit = DPB_HOTPLUG_INT_STATUS;
  1803. break;
  1804. case DP_C:
  1805. bit = DPC_HOTPLUG_INT_STATUS;
  1806. break;
  1807. case DP_D:
  1808. bit = DPD_HOTPLUG_INT_STATUS;
  1809. break;
  1810. default:
  1811. return connector_status_unknown;
  1812. }
  1813. temp = I915_READ(PORT_HOTPLUG_STAT);
  1814. if ((temp & bit) == 0)
  1815. return connector_status_disconnected;
  1816. return intel_dp_detect_dpcd(intel_dp);
  1817. }
  1818. static struct edid *
  1819. intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
  1820. {
  1821. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1822. struct edid *edid;
  1823. ironlake_edp_panel_vdd_on(intel_dp);
  1824. edid = drm_get_edid(connector, adapter);
  1825. ironlake_edp_panel_vdd_off(intel_dp, false);
  1826. return edid;
  1827. }
  1828. static int
  1829. intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
  1830. {
  1831. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1832. int ret;
  1833. ironlake_edp_panel_vdd_on(intel_dp);
  1834. ret = intel_ddc_get_modes(connector, adapter);
  1835. ironlake_edp_panel_vdd_off(intel_dp, false);
  1836. return ret;
  1837. }
  1838. /**
  1839. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
  1840. *
  1841. * \return true if DP port is connected.
  1842. * \return false if DP port is disconnected.
  1843. */
  1844. static enum drm_connector_status
  1845. intel_dp_detect(struct drm_connector *connector, bool force)
  1846. {
  1847. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1848. struct drm_device *dev = intel_dp->base.base.dev;
  1849. enum drm_connector_status status;
  1850. struct edid *edid = NULL;
  1851. intel_dp->has_audio = false;
  1852. if (HAS_PCH_SPLIT(dev))
  1853. status = ironlake_dp_detect(intel_dp);
  1854. else
  1855. status = g4x_dp_detect(intel_dp);
  1856. DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
  1857. intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
  1858. intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
  1859. intel_dp->dpcd[6], intel_dp->dpcd[7]);
  1860. if (status != connector_status_connected)
  1861. return status;
  1862. intel_dp_probe_oui(intel_dp);
  1863. if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
  1864. intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
  1865. } else {
  1866. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  1867. if (edid) {
  1868. intel_dp->has_audio = drm_detect_monitor_audio(edid);
  1869. connector->display_info.raw_edid = NULL;
  1870. kfree(edid);
  1871. }
  1872. }
  1873. return connector_status_connected;
  1874. }
  1875. static int intel_dp_get_modes(struct drm_connector *connector)
  1876. {
  1877. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1878. struct drm_device *dev = intel_dp->base.base.dev;
  1879. struct drm_i915_private *dev_priv = dev->dev_private;
  1880. int ret;
  1881. /* We should parse the EDID data and find out if it has an audio sink
  1882. */
  1883. ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
  1884. if (ret) {
  1885. if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
  1886. struct drm_display_mode *newmode;
  1887. list_for_each_entry(newmode, &connector->probed_modes,
  1888. head) {
  1889. if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
  1890. intel_dp->panel_fixed_mode =
  1891. drm_mode_duplicate(dev, newmode);
  1892. break;
  1893. }
  1894. }
  1895. }
  1896. return ret;
  1897. }
  1898. /* if eDP has no EDID, try to use fixed panel mode from VBT */
  1899. if (is_edp(intel_dp)) {
  1900. /* initialize panel mode from VBT if available for eDP */
  1901. if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
  1902. intel_dp->panel_fixed_mode =
  1903. drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
  1904. if (intel_dp->panel_fixed_mode) {
  1905. intel_dp->panel_fixed_mode->type |=
  1906. DRM_MODE_TYPE_PREFERRED;
  1907. }
  1908. }
  1909. if (intel_dp->panel_fixed_mode) {
  1910. struct drm_display_mode *mode;
  1911. mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
  1912. drm_mode_probed_add(connector, mode);
  1913. return 1;
  1914. }
  1915. }
  1916. return 0;
  1917. }
  1918. static bool
  1919. intel_dp_detect_audio(struct drm_connector *connector)
  1920. {
  1921. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1922. struct edid *edid;
  1923. bool has_audio = false;
  1924. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  1925. if (edid) {
  1926. has_audio = drm_detect_monitor_audio(edid);
  1927. connector->display_info.raw_edid = NULL;
  1928. kfree(edid);
  1929. }
  1930. return has_audio;
  1931. }
  1932. static int
  1933. intel_dp_set_property(struct drm_connector *connector,
  1934. struct drm_property *property,
  1935. uint64_t val)
  1936. {
  1937. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1938. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1939. int ret;
  1940. ret = drm_connector_property_set_value(connector, property, val);
  1941. if (ret)
  1942. return ret;
  1943. if (property == dev_priv->force_audio_property) {
  1944. int i = val;
  1945. bool has_audio;
  1946. if (i == intel_dp->force_audio)
  1947. return 0;
  1948. intel_dp->force_audio = i;
  1949. if (i == HDMI_AUDIO_AUTO)
  1950. has_audio = intel_dp_detect_audio(connector);
  1951. else
  1952. has_audio = (i == HDMI_AUDIO_ON);
  1953. if (has_audio == intel_dp->has_audio)
  1954. return 0;
  1955. intel_dp->has_audio = has_audio;
  1956. goto done;
  1957. }
  1958. if (property == dev_priv->broadcast_rgb_property) {
  1959. if (val == !!intel_dp->color_range)
  1960. return 0;
  1961. intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
  1962. goto done;
  1963. }
  1964. return -EINVAL;
  1965. done:
  1966. if (intel_dp->base.base.crtc) {
  1967. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  1968. drm_crtc_helper_set_mode(crtc, &crtc->mode,
  1969. crtc->x, crtc->y,
  1970. crtc->fb);
  1971. }
  1972. return 0;
  1973. }
  1974. static void
  1975. intel_dp_destroy(struct drm_connector *connector)
  1976. {
  1977. struct drm_device *dev = connector->dev;
  1978. if (intel_dpd_is_edp(dev))
  1979. intel_panel_destroy_backlight(dev);
  1980. drm_sysfs_connector_remove(connector);
  1981. drm_connector_cleanup(connector);
  1982. kfree(connector);
  1983. }
  1984. static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
  1985. {
  1986. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  1987. i2c_del_adapter(&intel_dp->adapter);
  1988. drm_encoder_cleanup(encoder);
  1989. if (is_edp(intel_dp)) {
  1990. cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
  1991. ironlake_panel_vdd_off_sync(intel_dp);
  1992. }
  1993. kfree(intel_dp);
  1994. }
  1995. static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
  1996. .dpms = intel_dp_dpms,
  1997. .mode_fixup = intel_dp_mode_fixup,
  1998. .prepare = intel_dp_prepare,
  1999. .mode_set = intel_dp_mode_set,
  2000. .commit = intel_dp_commit,
  2001. };
  2002. static const struct drm_connector_funcs intel_dp_connector_funcs = {
  2003. .dpms = drm_helper_connector_dpms,
  2004. .detect = intel_dp_detect,
  2005. .fill_modes = drm_helper_probe_single_connector_modes,
  2006. .set_property = intel_dp_set_property,
  2007. .destroy = intel_dp_destroy,
  2008. };
  2009. static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
  2010. .get_modes = intel_dp_get_modes,
  2011. .mode_valid = intel_dp_mode_valid,
  2012. .best_encoder = intel_best_encoder,
  2013. };
  2014. static const struct drm_encoder_funcs intel_dp_enc_funcs = {
  2015. .destroy = intel_dp_encoder_destroy,
  2016. };
  2017. static void
  2018. intel_dp_hot_plug(struct intel_encoder *intel_encoder)
  2019. {
  2020. struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  2021. intel_dp_check_link_status(intel_dp);
  2022. }
  2023. /* Return which DP Port should be selected for Transcoder DP control */
  2024. int
  2025. intel_trans_dp_port_sel(struct drm_crtc *crtc)
  2026. {
  2027. struct drm_device *dev = crtc->dev;
  2028. struct drm_mode_config *mode_config = &dev->mode_config;
  2029. struct drm_encoder *encoder;
  2030. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  2031. struct intel_dp *intel_dp;
  2032. if (encoder->crtc != crtc)
  2033. continue;
  2034. intel_dp = enc_to_intel_dp(encoder);
  2035. if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
  2036. intel_dp->base.type == INTEL_OUTPUT_EDP)
  2037. return intel_dp->output_reg;
  2038. }
  2039. return -1;
  2040. }
  2041. /* check the VBT to see whether the eDP is on DP-D port */
  2042. bool intel_dpd_is_edp(struct drm_device *dev)
  2043. {
  2044. struct drm_i915_private *dev_priv = dev->dev_private;
  2045. struct child_device_config *p_child;
  2046. int i;
  2047. if (!dev_priv->child_dev_num)
  2048. return false;
  2049. for (i = 0; i < dev_priv->child_dev_num; i++) {
  2050. p_child = dev_priv->child_dev + i;
  2051. if (p_child->dvo_port == PORT_IDPD &&
  2052. p_child->device_type == DEVICE_TYPE_eDP)
  2053. return true;
  2054. }
  2055. return false;
  2056. }
  2057. static void
  2058. intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
  2059. {
  2060. intel_attach_force_audio_property(connector);
  2061. intel_attach_broadcast_rgb_property(connector);
  2062. }
  2063. void
  2064. intel_dp_init(struct drm_device *dev, int output_reg)
  2065. {
  2066. struct drm_i915_private *dev_priv = dev->dev_private;
  2067. struct drm_connector *connector;
  2068. struct intel_dp *intel_dp;
  2069. struct intel_encoder *intel_encoder;
  2070. struct intel_connector *intel_connector;
  2071. const char *name = NULL;
  2072. int type;
  2073. intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
  2074. if (!intel_dp)
  2075. return;
  2076. intel_dp->output_reg = output_reg;
  2077. intel_dp->dpms_mode = -1;
  2078. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  2079. if (!intel_connector) {
  2080. kfree(intel_dp);
  2081. return;
  2082. }
  2083. intel_encoder = &intel_dp->base;
  2084. if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
  2085. if (intel_dpd_is_edp(dev))
  2086. intel_dp->is_pch_edp = true;
  2087. if (output_reg == DP_A || is_pch_edp(intel_dp)) {
  2088. type = DRM_MODE_CONNECTOR_eDP;
  2089. intel_encoder->type = INTEL_OUTPUT_EDP;
  2090. } else {
  2091. type = DRM_MODE_CONNECTOR_DisplayPort;
  2092. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  2093. }
  2094. connector = &intel_connector->base;
  2095. drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
  2096. drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
  2097. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2098. if (output_reg == DP_B || output_reg == PCH_DP_B)
  2099. intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
  2100. else if (output_reg == DP_C || output_reg == PCH_DP_C)
  2101. intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
  2102. else if (output_reg == DP_D || output_reg == PCH_DP_D)
  2103. intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
  2104. if (is_edp(intel_dp)) {
  2105. intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
  2106. INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
  2107. ironlake_panel_vdd_work);
  2108. }
  2109. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2110. connector->interlace_allowed = true;
  2111. connector->doublescan_allowed = 0;
  2112. drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
  2113. DRM_MODE_ENCODER_TMDS);
  2114. drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
  2115. intel_connector_attach_encoder(intel_connector, intel_encoder);
  2116. drm_sysfs_connector_add(connector);
  2117. /* Set up the DDC bus. */
  2118. switch (output_reg) {
  2119. case DP_A:
  2120. name = "DPDDC-A";
  2121. break;
  2122. case DP_B:
  2123. case PCH_DP_B:
  2124. dev_priv->hotplug_supported_mask |=
  2125. HDMIB_HOTPLUG_INT_STATUS;
  2126. name = "DPDDC-B";
  2127. break;
  2128. case DP_C:
  2129. case PCH_DP_C:
  2130. dev_priv->hotplug_supported_mask |=
  2131. HDMIC_HOTPLUG_INT_STATUS;
  2132. name = "DPDDC-C";
  2133. break;
  2134. case DP_D:
  2135. case PCH_DP_D:
  2136. dev_priv->hotplug_supported_mask |=
  2137. HDMID_HOTPLUG_INT_STATUS;
  2138. name = "DPDDC-D";
  2139. break;
  2140. }
  2141. /* Cache some DPCD data in the eDP case */
  2142. if (is_edp(intel_dp)) {
  2143. bool ret;
  2144. struct edp_power_seq cur, vbt;
  2145. u32 pp_on, pp_off, pp_div;
  2146. pp_on = I915_READ(PCH_PP_ON_DELAYS);
  2147. pp_off = I915_READ(PCH_PP_OFF_DELAYS);
  2148. pp_div = I915_READ(PCH_PP_DIVISOR);
  2149. if (!pp_on || !pp_off || !pp_div) {
  2150. DRM_INFO("bad panel power sequencing delays, disabling panel\n");
  2151. intel_dp_encoder_destroy(&intel_dp->base.base);
  2152. intel_dp_destroy(&intel_connector->base);
  2153. return;
  2154. }
  2155. /* Pull timing values out of registers */
  2156. cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
  2157. PANEL_POWER_UP_DELAY_SHIFT;
  2158. cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
  2159. PANEL_LIGHT_ON_DELAY_SHIFT;
  2160. cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
  2161. PANEL_LIGHT_OFF_DELAY_SHIFT;
  2162. cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
  2163. PANEL_POWER_DOWN_DELAY_SHIFT;
  2164. cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
  2165. PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
  2166. DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2167. cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
  2168. vbt = dev_priv->edp.pps;
  2169. DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2170. vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
  2171. #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
  2172. intel_dp->panel_power_up_delay = get_delay(t1_t3);
  2173. intel_dp->backlight_on_delay = get_delay(t8);
  2174. intel_dp->backlight_off_delay = get_delay(t9);
  2175. intel_dp->panel_power_down_delay = get_delay(t10);
  2176. intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
  2177. DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
  2178. intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
  2179. intel_dp->panel_power_cycle_delay);
  2180. DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
  2181. intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
  2182. ironlake_edp_panel_vdd_on(intel_dp);
  2183. ret = intel_dp_get_dpcd(intel_dp);
  2184. ironlake_edp_panel_vdd_off(intel_dp, false);
  2185. if (ret) {
  2186. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
  2187. dev_priv->no_aux_handshake =
  2188. intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
  2189. DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
  2190. } else {
  2191. /* if this fails, presume the device is a ghost */
  2192. DRM_INFO("failed to retrieve link info, disabling eDP\n");
  2193. intel_dp_encoder_destroy(&intel_dp->base.base);
  2194. intel_dp_destroy(&intel_connector->base);
  2195. return;
  2196. }
  2197. }
  2198. intel_dp_i2c_init(intel_dp, intel_connector, name);
  2199. intel_encoder->hot_plug = intel_dp_hot_plug;
  2200. if (is_edp(intel_dp)) {
  2201. dev_priv->int_edp_connector = connector;
  2202. intel_panel_setup_backlight(dev);
  2203. }
  2204. intel_dp_add_properties(intel_dp, connector);
  2205. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  2206. * 0xd. Failure to do so will result in spurious interrupts being
  2207. * generated on the port when a cable is not attached.
  2208. */
  2209. if (IS_G4X(dev) && !IS_GM45(dev)) {
  2210. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  2211. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  2212. }
  2213. }