cx23885-cards.c 44 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include <linux/firmware.h>
  27. #include <misc/altera.h>
  28. #include "cx23885.h"
  29. #include "tuner-xc2028.h"
  30. #include "netup-eeprom.h"
  31. #include "netup-init.h"
  32. #include "altera-ci.h"
  33. #include "xc4000.h"
  34. #include "xc5000.h"
  35. #include "cx23888-ir.h"
  36. static unsigned int netup_card_rev = 1;
  37. module_param(netup_card_rev, int, 0644);
  38. MODULE_PARM_DESC(netup_card_rev,
  39. "NetUP Dual DVB-T/C CI card revision");
  40. static unsigned int enable_885_ir;
  41. module_param(enable_885_ir, int, 0644);
  42. MODULE_PARM_DESC(enable_885_ir,
  43. "Enable integrated IR controller for supported\n"
  44. "\t\t CX2388[57] boards that are wired for it:\n"
  45. "\t\t\tHVR-1250 (reported safe)\n"
  46. "\t\t\tTeVii S470 (reported unsafe)\n"
  47. "\t\t This can cause an interrupt storm with some cards.\n"
  48. "\t\t Default: 0 [Disabled]");
  49. /* ------------------------------------------------------------------ */
  50. /* board config info */
  51. struct cx23885_board cx23885_boards[] = {
  52. [CX23885_BOARD_UNKNOWN] = {
  53. .name = "UNKNOWN/GENERIC",
  54. /* Ensure safe default for unknown boards */
  55. .clk_freq = 0,
  56. .input = {{
  57. .type = CX23885_VMUX_COMPOSITE1,
  58. .vmux = 0,
  59. }, {
  60. .type = CX23885_VMUX_COMPOSITE2,
  61. .vmux = 1,
  62. }, {
  63. .type = CX23885_VMUX_COMPOSITE3,
  64. .vmux = 2,
  65. }, {
  66. .type = CX23885_VMUX_COMPOSITE4,
  67. .vmux = 3,
  68. } },
  69. },
  70. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  71. .name = "Hauppauge WinTV-HVR1800lp",
  72. .portc = CX23885_MPEG_DVB,
  73. .input = {{
  74. .type = CX23885_VMUX_TELEVISION,
  75. .vmux = 0,
  76. .gpio0 = 0xff00,
  77. }, {
  78. .type = CX23885_VMUX_DEBUG,
  79. .vmux = 0,
  80. .gpio0 = 0xff01,
  81. }, {
  82. .type = CX23885_VMUX_COMPOSITE1,
  83. .vmux = 1,
  84. .gpio0 = 0xff02,
  85. }, {
  86. .type = CX23885_VMUX_SVIDEO,
  87. .vmux = 2,
  88. .gpio0 = 0xff02,
  89. } },
  90. },
  91. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  92. .name = "Hauppauge WinTV-HVR1800",
  93. .porta = CX23885_ANALOG_VIDEO,
  94. .portb = CX23885_MPEG_ENCODER,
  95. .portc = CX23885_MPEG_DVB,
  96. .tuner_type = TUNER_PHILIPS_TDA8290,
  97. .tuner_addr = 0x42, /* 0x84 >> 1 */
  98. .tuner_bus = 1,
  99. .input = {{
  100. .type = CX23885_VMUX_TELEVISION,
  101. .vmux = CX25840_VIN7_CH3 |
  102. CX25840_VIN5_CH2 |
  103. CX25840_VIN2_CH1,
  104. .amux = CX25840_AUDIO8,
  105. .gpio0 = 0,
  106. }, {
  107. .type = CX23885_VMUX_COMPOSITE1,
  108. .vmux = CX25840_VIN7_CH3 |
  109. CX25840_VIN4_CH2 |
  110. CX25840_VIN6_CH1,
  111. .amux = CX25840_AUDIO7,
  112. .gpio0 = 0,
  113. }, {
  114. .type = CX23885_VMUX_SVIDEO,
  115. .vmux = CX25840_VIN7_CH3 |
  116. CX25840_VIN4_CH2 |
  117. CX25840_VIN8_CH1 |
  118. CX25840_SVIDEO_ON,
  119. .amux = CX25840_AUDIO7,
  120. .gpio0 = 0,
  121. } },
  122. },
  123. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  124. .name = "Hauppauge WinTV-HVR1250",
  125. .portc = CX23885_MPEG_DVB,
  126. .input = {{
  127. .type = CX23885_VMUX_TELEVISION,
  128. .vmux = 0,
  129. .gpio0 = 0xff00,
  130. }, {
  131. .type = CX23885_VMUX_DEBUG,
  132. .vmux = 0,
  133. .gpio0 = 0xff01,
  134. }, {
  135. .type = CX23885_VMUX_COMPOSITE1,
  136. .vmux = 1,
  137. .gpio0 = 0xff02,
  138. }, {
  139. .type = CX23885_VMUX_SVIDEO,
  140. .vmux = 2,
  141. .gpio0 = 0xff02,
  142. } },
  143. },
  144. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  145. .name = "DViCO FusionHDTV5 Express",
  146. .portb = CX23885_MPEG_DVB,
  147. },
  148. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  149. .name = "Hauppauge WinTV-HVR1500Q",
  150. .portc = CX23885_MPEG_DVB,
  151. },
  152. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  153. .name = "Hauppauge WinTV-HVR1500",
  154. .porta = CX23885_ANALOG_VIDEO,
  155. .portc = CX23885_MPEG_DVB,
  156. .tuner_type = TUNER_XC2028,
  157. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  158. .input = {{
  159. .type = CX23885_VMUX_TELEVISION,
  160. .vmux = CX25840_VIN7_CH3 |
  161. CX25840_VIN5_CH2 |
  162. CX25840_VIN2_CH1,
  163. .gpio0 = 0,
  164. }, {
  165. .type = CX23885_VMUX_COMPOSITE1,
  166. .vmux = CX25840_VIN7_CH3 |
  167. CX25840_VIN4_CH2 |
  168. CX25840_VIN6_CH1,
  169. .gpio0 = 0,
  170. }, {
  171. .type = CX23885_VMUX_SVIDEO,
  172. .vmux = CX25840_VIN7_CH3 |
  173. CX25840_VIN4_CH2 |
  174. CX25840_VIN8_CH1 |
  175. CX25840_SVIDEO_ON,
  176. .gpio0 = 0,
  177. } },
  178. },
  179. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  180. .name = "Hauppauge WinTV-HVR1200",
  181. .portc = CX23885_MPEG_DVB,
  182. },
  183. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  184. .name = "Hauppauge WinTV-HVR1700",
  185. .portc = CX23885_MPEG_DVB,
  186. },
  187. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  188. .name = "Hauppauge WinTV-HVR1400",
  189. .portc = CX23885_MPEG_DVB,
  190. },
  191. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  192. .name = "DViCO FusionHDTV7 Dual Express",
  193. .portb = CX23885_MPEG_DVB,
  194. .portc = CX23885_MPEG_DVB,
  195. },
  196. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  197. .name = "DViCO FusionHDTV DVB-T Dual Express",
  198. .portb = CX23885_MPEG_DVB,
  199. .portc = CX23885_MPEG_DVB,
  200. },
  201. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  202. .name = "Leadtek Winfast PxDVR3200 H",
  203. .portc = CX23885_MPEG_DVB,
  204. },
  205. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
  206. .name = "Leadtek Winfast PxDVR3200 H XC4000",
  207. .porta = CX23885_ANALOG_VIDEO,
  208. .portc = CX23885_MPEG_DVB,
  209. .tuner_type = TUNER_XC4000,
  210. .tuner_addr = 0x61,
  211. .radio_type = TUNER_XC4000,
  212. .radio_addr = 0x61,
  213. .input = {{
  214. .type = CX23885_VMUX_TELEVISION,
  215. .vmux = CX25840_VIN2_CH1 |
  216. CX25840_VIN5_CH2 |
  217. CX25840_NONE0_CH3,
  218. }, {
  219. .type = CX23885_VMUX_COMPOSITE1,
  220. .vmux = CX25840_COMPOSITE1,
  221. }, {
  222. .type = CX23885_VMUX_SVIDEO,
  223. .vmux = CX25840_SVIDEO_LUMA3 |
  224. CX25840_SVIDEO_CHROMA4,
  225. }, {
  226. .type = CX23885_VMUX_COMPONENT,
  227. .vmux = CX25840_VIN7_CH1 |
  228. CX25840_VIN6_CH2 |
  229. CX25840_VIN8_CH3 |
  230. CX25840_COMPONENT_ON,
  231. } },
  232. },
  233. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  234. .name = "Compro VideoMate E650F",
  235. .portc = CX23885_MPEG_DVB,
  236. },
  237. [CX23885_BOARD_TBS_6920] = {
  238. .name = "TurboSight TBS 6920",
  239. .portb = CX23885_MPEG_DVB,
  240. },
  241. [CX23885_BOARD_TEVII_S470] = {
  242. .name = "TeVii S470",
  243. .portb = CX23885_MPEG_DVB,
  244. },
  245. [CX23885_BOARD_DVBWORLD_2005] = {
  246. .name = "DVBWorld DVB-S2 2005",
  247. .portb = CX23885_MPEG_DVB,
  248. },
  249. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  250. .ci_type = 1,
  251. .name = "NetUP Dual DVB-S2 CI",
  252. .portb = CX23885_MPEG_DVB,
  253. .portc = CX23885_MPEG_DVB,
  254. },
  255. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  256. .name = "Hauppauge WinTV-HVR1270",
  257. .portc = CX23885_MPEG_DVB,
  258. },
  259. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  260. .name = "Hauppauge WinTV-HVR1275",
  261. .portc = CX23885_MPEG_DVB,
  262. },
  263. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  264. .name = "Hauppauge WinTV-HVR1255",
  265. .portc = CX23885_MPEG_DVB,
  266. },
  267. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  268. .name = "Hauppauge WinTV-HVR1210",
  269. .portc = CX23885_MPEG_DVB,
  270. },
  271. [CX23885_BOARD_MYGICA_X8506] = {
  272. .name = "Mygica X8506 DMB-TH",
  273. .tuner_type = TUNER_XC5000,
  274. .tuner_addr = 0x61,
  275. .tuner_bus = 1,
  276. .porta = CX23885_ANALOG_VIDEO,
  277. .portb = CX23885_MPEG_DVB,
  278. .input = {
  279. {
  280. .type = CX23885_VMUX_TELEVISION,
  281. .vmux = CX25840_COMPOSITE2,
  282. },
  283. {
  284. .type = CX23885_VMUX_COMPOSITE1,
  285. .vmux = CX25840_COMPOSITE8,
  286. },
  287. {
  288. .type = CX23885_VMUX_SVIDEO,
  289. .vmux = CX25840_SVIDEO_LUMA3 |
  290. CX25840_SVIDEO_CHROMA4,
  291. },
  292. {
  293. .type = CX23885_VMUX_COMPONENT,
  294. .vmux = CX25840_COMPONENT_ON |
  295. CX25840_VIN1_CH1 |
  296. CX25840_VIN6_CH2 |
  297. CX25840_VIN7_CH3,
  298. },
  299. },
  300. },
  301. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  302. .name = "Magic-Pro ProHDTV Extreme 2",
  303. .tuner_type = TUNER_XC5000,
  304. .tuner_addr = 0x61,
  305. .tuner_bus = 1,
  306. .porta = CX23885_ANALOG_VIDEO,
  307. .portb = CX23885_MPEG_DVB,
  308. .input = {
  309. {
  310. .type = CX23885_VMUX_TELEVISION,
  311. .vmux = CX25840_COMPOSITE2,
  312. },
  313. {
  314. .type = CX23885_VMUX_COMPOSITE1,
  315. .vmux = CX25840_COMPOSITE8,
  316. },
  317. {
  318. .type = CX23885_VMUX_SVIDEO,
  319. .vmux = CX25840_SVIDEO_LUMA3 |
  320. CX25840_SVIDEO_CHROMA4,
  321. },
  322. {
  323. .type = CX23885_VMUX_COMPONENT,
  324. .vmux = CX25840_COMPONENT_ON |
  325. CX25840_VIN1_CH1 |
  326. CX25840_VIN6_CH2 |
  327. CX25840_VIN7_CH3,
  328. },
  329. },
  330. },
  331. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  332. .name = "Hauppauge WinTV-HVR1850",
  333. .porta = CX23885_ANALOG_VIDEO,
  334. .portb = CX23885_MPEG_ENCODER,
  335. .portc = CX23885_MPEG_DVB,
  336. .tuner_type = TUNER_ABSENT,
  337. .tuner_addr = 0x42, /* 0x84 >> 1 */
  338. .force_bff = 1,
  339. .input = {{
  340. .type = CX23885_VMUX_TELEVISION,
  341. .vmux = CX25840_VIN7_CH3 |
  342. CX25840_VIN5_CH2 |
  343. CX25840_VIN2_CH1 |
  344. CX25840_DIF_ON,
  345. .amux = CX25840_AUDIO8,
  346. }, {
  347. .type = CX23885_VMUX_COMPOSITE1,
  348. .vmux = CX25840_VIN7_CH3 |
  349. CX25840_VIN4_CH2 |
  350. CX25840_VIN6_CH1,
  351. .amux = CX25840_AUDIO7,
  352. }, {
  353. .type = CX23885_VMUX_SVIDEO,
  354. .vmux = CX25840_VIN7_CH3 |
  355. CX25840_VIN4_CH2 |
  356. CX25840_VIN8_CH1 |
  357. CX25840_SVIDEO_ON,
  358. .amux = CX25840_AUDIO7,
  359. } },
  360. },
  361. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  362. .name = "Compro VideoMate E800",
  363. .portc = CX23885_MPEG_DVB,
  364. },
  365. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  366. .name = "Hauppauge WinTV-HVR1290",
  367. .portc = CX23885_MPEG_DVB,
  368. },
  369. [CX23885_BOARD_MYGICA_X8558PRO] = {
  370. .name = "Mygica X8558 PRO DMB-TH",
  371. .portb = CX23885_MPEG_DVB,
  372. .portc = CX23885_MPEG_DVB,
  373. },
  374. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  375. .name = "LEADTEK WinFast PxTV1200",
  376. .porta = CX23885_ANALOG_VIDEO,
  377. .tuner_type = TUNER_XC2028,
  378. .tuner_addr = 0x61,
  379. .tuner_bus = 1,
  380. .input = {{
  381. .type = CX23885_VMUX_TELEVISION,
  382. .vmux = CX25840_VIN2_CH1 |
  383. CX25840_VIN5_CH2 |
  384. CX25840_NONE0_CH3,
  385. }, {
  386. .type = CX23885_VMUX_COMPOSITE1,
  387. .vmux = CX25840_COMPOSITE1,
  388. }, {
  389. .type = CX23885_VMUX_SVIDEO,
  390. .vmux = CX25840_SVIDEO_LUMA3 |
  391. CX25840_SVIDEO_CHROMA4,
  392. }, {
  393. .type = CX23885_VMUX_COMPONENT,
  394. .vmux = CX25840_VIN7_CH1 |
  395. CX25840_VIN6_CH2 |
  396. CX25840_VIN8_CH3 |
  397. CX25840_COMPONENT_ON,
  398. } },
  399. },
  400. [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
  401. .name = "GoTView X5 3D Hybrid",
  402. .tuner_type = TUNER_XC5000,
  403. .tuner_addr = 0x64,
  404. .tuner_bus = 1,
  405. .porta = CX23885_ANALOG_VIDEO,
  406. .portb = CX23885_MPEG_DVB,
  407. .input = {{
  408. .type = CX23885_VMUX_TELEVISION,
  409. .vmux = CX25840_VIN2_CH1 |
  410. CX25840_VIN5_CH2,
  411. .gpio0 = 0x02,
  412. }, {
  413. .type = CX23885_VMUX_COMPOSITE1,
  414. .vmux = CX23885_VMUX_COMPOSITE1,
  415. }, {
  416. .type = CX23885_VMUX_SVIDEO,
  417. .vmux = CX25840_SVIDEO_LUMA3 |
  418. CX25840_SVIDEO_CHROMA4,
  419. } },
  420. },
  421. [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
  422. .ci_type = 2,
  423. .name = "NetUP Dual DVB-T/C-CI RF",
  424. .porta = CX23885_ANALOG_VIDEO,
  425. .portb = CX23885_MPEG_DVB,
  426. .portc = CX23885_MPEG_DVB,
  427. .num_fds_portb = 2,
  428. .num_fds_portc = 2,
  429. .tuner_type = TUNER_XC5000,
  430. .tuner_addr = 0x64,
  431. .input = { {
  432. .type = CX23885_VMUX_TELEVISION,
  433. .vmux = CX25840_COMPOSITE1,
  434. } },
  435. },
  436. [CX23885_BOARD_MPX885] = {
  437. .name = "MPX-885",
  438. .porta = CX23885_ANALOG_VIDEO,
  439. .input = {{
  440. .type = CX23885_VMUX_COMPOSITE1,
  441. .vmux = CX25840_COMPOSITE1,
  442. .amux = CX25840_AUDIO6,
  443. .gpio0 = 0,
  444. }, {
  445. .type = CX23885_VMUX_COMPOSITE2,
  446. .vmux = CX25840_COMPOSITE2,
  447. .amux = CX25840_AUDIO6,
  448. .gpio0 = 0,
  449. }, {
  450. .type = CX23885_VMUX_COMPOSITE3,
  451. .vmux = CX25840_COMPOSITE3,
  452. .amux = CX25840_AUDIO7,
  453. .gpio0 = 0,
  454. }, {
  455. .type = CX23885_VMUX_COMPOSITE4,
  456. .vmux = CX25840_COMPOSITE4,
  457. .amux = CX25840_AUDIO7,
  458. .gpio0 = 0,
  459. } },
  460. },
  461. [CX23885_BOARD_MYGICA_X8507] = {
  462. .name = "Mygica X8507",
  463. .tuner_type = TUNER_XC5000,
  464. .tuner_addr = 0x61,
  465. .tuner_bus = 1,
  466. .porta = CX23885_ANALOG_VIDEO,
  467. .input = {
  468. {
  469. .type = CX23885_VMUX_TELEVISION,
  470. .vmux = CX25840_COMPOSITE2,
  471. .amux = CX25840_AUDIO8,
  472. },
  473. {
  474. .type = CX23885_VMUX_COMPOSITE1,
  475. .vmux = CX25840_COMPOSITE8,
  476. },
  477. {
  478. .type = CX23885_VMUX_SVIDEO,
  479. .vmux = CX25840_SVIDEO_LUMA3 |
  480. CX25840_SVIDEO_CHROMA4,
  481. },
  482. {
  483. .type = CX23885_VMUX_COMPONENT,
  484. .vmux = CX25840_COMPONENT_ON |
  485. CX25840_VIN1_CH1 |
  486. CX25840_VIN6_CH2 |
  487. CX25840_VIN7_CH3,
  488. },
  489. },
  490. }
  491. };
  492. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  493. /* ------------------------------------------------------------------ */
  494. /* PCI subsystem IDs */
  495. struct cx23885_subid cx23885_subids[] = {
  496. {
  497. .subvendor = 0x0070,
  498. .subdevice = 0x3400,
  499. .card = CX23885_BOARD_UNKNOWN,
  500. }, {
  501. .subvendor = 0x0070,
  502. .subdevice = 0x7600,
  503. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  504. }, {
  505. .subvendor = 0x0070,
  506. .subdevice = 0x7800,
  507. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  508. }, {
  509. .subvendor = 0x0070,
  510. .subdevice = 0x7801,
  511. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  512. }, {
  513. .subvendor = 0x0070,
  514. .subdevice = 0x7809,
  515. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  516. }, {
  517. .subvendor = 0x0070,
  518. .subdevice = 0x7911,
  519. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  520. }, {
  521. .subvendor = 0x18ac,
  522. .subdevice = 0xd500,
  523. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  524. }, {
  525. .subvendor = 0x0070,
  526. .subdevice = 0x7790,
  527. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  528. }, {
  529. .subvendor = 0x0070,
  530. .subdevice = 0x7797,
  531. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  532. }, {
  533. .subvendor = 0x0070,
  534. .subdevice = 0x7710,
  535. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  536. }, {
  537. .subvendor = 0x0070,
  538. .subdevice = 0x7717,
  539. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  540. }, {
  541. .subvendor = 0x0070,
  542. .subdevice = 0x71d1,
  543. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  544. }, {
  545. .subvendor = 0x0070,
  546. .subdevice = 0x71d3,
  547. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  548. }, {
  549. .subvendor = 0x0070,
  550. .subdevice = 0x8101,
  551. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  552. }, {
  553. .subvendor = 0x0070,
  554. .subdevice = 0x8010,
  555. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  556. }, {
  557. .subvendor = 0x18ac,
  558. .subdevice = 0xd618,
  559. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  560. }, {
  561. .subvendor = 0x18ac,
  562. .subdevice = 0xdb78,
  563. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  564. }, {
  565. .subvendor = 0x107d,
  566. .subdevice = 0x6681,
  567. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  568. }, {
  569. .subvendor = 0x107d,
  570. .subdevice = 0x6f39,
  571. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
  572. }, {
  573. .subvendor = 0x185b,
  574. .subdevice = 0xe800,
  575. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  576. }, {
  577. .subvendor = 0x6920,
  578. .subdevice = 0x8888,
  579. .card = CX23885_BOARD_TBS_6920,
  580. }, {
  581. .subvendor = 0xd470,
  582. .subdevice = 0x9022,
  583. .card = CX23885_BOARD_TEVII_S470,
  584. }, {
  585. .subvendor = 0x0001,
  586. .subdevice = 0x2005,
  587. .card = CX23885_BOARD_DVBWORLD_2005,
  588. }, {
  589. .subvendor = 0x1b55,
  590. .subdevice = 0x2a2c,
  591. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  592. }, {
  593. .subvendor = 0x0070,
  594. .subdevice = 0x2211,
  595. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  596. }, {
  597. .subvendor = 0x0070,
  598. .subdevice = 0x2215,
  599. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  600. }, {
  601. .subvendor = 0x0070,
  602. .subdevice = 0x221d,
  603. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  604. }, {
  605. .subvendor = 0x0070,
  606. .subdevice = 0x2251,
  607. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  608. }, {
  609. .subvendor = 0x0070,
  610. .subdevice = 0x2259,
  611. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  612. }, {
  613. .subvendor = 0x0070,
  614. .subdevice = 0x2291,
  615. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  616. }, {
  617. .subvendor = 0x0070,
  618. .subdevice = 0x2295,
  619. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  620. }, {
  621. .subvendor = 0x0070,
  622. .subdevice = 0x2299,
  623. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  624. }, {
  625. .subvendor = 0x0070,
  626. .subdevice = 0x229d,
  627. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  628. }, {
  629. .subvendor = 0x0070,
  630. .subdevice = 0x22f0,
  631. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  632. }, {
  633. .subvendor = 0x0070,
  634. .subdevice = 0x22f1,
  635. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  636. }, {
  637. .subvendor = 0x0070,
  638. .subdevice = 0x22f2,
  639. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  640. }, {
  641. .subvendor = 0x0070,
  642. .subdevice = 0x22f3,
  643. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  644. }, {
  645. .subvendor = 0x0070,
  646. .subdevice = 0x22f4,
  647. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  648. }, {
  649. .subvendor = 0x0070,
  650. .subdevice = 0x22f5,
  651. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  652. }, {
  653. .subvendor = 0x14f1,
  654. .subdevice = 0x8651,
  655. .card = CX23885_BOARD_MYGICA_X8506,
  656. }, {
  657. .subvendor = 0x14f1,
  658. .subdevice = 0x8657,
  659. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  660. }, {
  661. .subvendor = 0x0070,
  662. .subdevice = 0x8541,
  663. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  664. }, {
  665. .subvendor = 0x1858,
  666. .subdevice = 0xe800,
  667. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  668. }, {
  669. .subvendor = 0x0070,
  670. .subdevice = 0x8551,
  671. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  672. }, {
  673. .subvendor = 0x14f1,
  674. .subdevice = 0x8578,
  675. .card = CX23885_BOARD_MYGICA_X8558PRO,
  676. }, {
  677. .subvendor = 0x107d,
  678. .subdevice = 0x6f22,
  679. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  680. }, {
  681. .subvendor = 0x5654,
  682. .subdevice = 0x2390,
  683. .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
  684. }, {
  685. .subvendor = 0x1b55,
  686. .subdevice = 0xe2e4,
  687. .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
  688. }, {
  689. .subvendor = 0x14f1,
  690. .subdevice = 0x8502,
  691. .card = CX23885_BOARD_MYGICA_X8507,
  692. },
  693. };
  694. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  695. void cx23885_card_list(struct cx23885_dev *dev)
  696. {
  697. int i;
  698. if (0 == dev->pci->subsystem_vendor &&
  699. 0 == dev->pci->subsystem_device) {
  700. printk(KERN_INFO
  701. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  702. "%s: be autodetected. Pass card=<n> insmod option\n"
  703. "%s: to workaround that. Redirect complaints to the\n"
  704. "%s: vendor of the TV card. Best regards,\n"
  705. "%s: -- tux\n",
  706. dev->name, dev->name, dev->name, dev->name, dev->name);
  707. } else {
  708. printk(KERN_INFO
  709. "%s: Your board isn't known (yet) to the driver.\n"
  710. "%s: Try to pick one of the existing card configs via\n"
  711. "%s: card=<n> insmod option. Updating to the latest\n"
  712. "%s: version might help as well.\n",
  713. dev->name, dev->name, dev->name, dev->name);
  714. }
  715. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  716. dev->name);
  717. for (i = 0; i < cx23885_bcount; i++)
  718. printk(KERN_INFO "%s: card=%d -> %s\n",
  719. dev->name, i, cx23885_boards[i].name);
  720. }
  721. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  722. {
  723. struct tveeprom tv;
  724. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  725. eeprom_data);
  726. /* Make sure we support the board model */
  727. switch (tv.model) {
  728. case 22001:
  729. /* WinTV-HVR1270 (PCIe, Retail, half height)
  730. * ATSC/QAM and basic analog, IR Blast */
  731. case 22009:
  732. /* WinTV-HVR1210 (PCIe, Retail, half height)
  733. * DVB-T and basic analog, IR Blast */
  734. case 22011:
  735. /* WinTV-HVR1270 (PCIe, Retail, half height)
  736. * ATSC/QAM and basic analog, IR Recv */
  737. case 22019:
  738. /* WinTV-HVR1210 (PCIe, Retail, half height)
  739. * DVB-T and basic analog, IR Recv */
  740. case 22021:
  741. /* WinTV-HVR1275 (PCIe, Retail, half height)
  742. * ATSC/QAM and basic analog, IR Recv */
  743. case 22029:
  744. /* WinTV-HVR1210 (PCIe, Retail, half height)
  745. * DVB-T and basic analog, IR Recv */
  746. case 22101:
  747. /* WinTV-HVR1270 (PCIe, Retail, full height)
  748. * ATSC/QAM and basic analog, IR Blast */
  749. case 22109:
  750. /* WinTV-HVR1210 (PCIe, Retail, full height)
  751. * DVB-T and basic analog, IR Blast */
  752. case 22111:
  753. /* WinTV-HVR1270 (PCIe, Retail, full height)
  754. * ATSC/QAM and basic analog, IR Recv */
  755. case 22119:
  756. /* WinTV-HVR1210 (PCIe, Retail, full height)
  757. * DVB-T and basic analog, IR Recv */
  758. case 22121:
  759. /* WinTV-HVR1275 (PCIe, Retail, full height)
  760. * ATSC/QAM and basic analog, IR Recv */
  761. case 22129:
  762. /* WinTV-HVR1210 (PCIe, Retail, full height)
  763. * DVB-T and basic analog, IR Recv */
  764. case 71009:
  765. /* WinTV-HVR1200 (PCIe, Retail, full height)
  766. * DVB-T and basic analog */
  767. case 71359:
  768. /* WinTV-HVR1200 (PCIe, OEM, half height)
  769. * DVB-T and basic analog */
  770. case 71439:
  771. /* WinTV-HVR1200 (PCIe, OEM, half height)
  772. * DVB-T and basic analog */
  773. case 71449:
  774. /* WinTV-HVR1200 (PCIe, OEM, full height)
  775. * DVB-T and basic analog */
  776. case 71939:
  777. /* WinTV-HVR1200 (PCIe, OEM, half height)
  778. * DVB-T and basic analog */
  779. case 71949:
  780. /* WinTV-HVR1200 (PCIe, OEM, full height)
  781. * DVB-T and basic analog */
  782. case 71959:
  783. /* WinTV-HVR1200 (PCIe, OEM, full height)
  784. * DVB-T and basic analog */
  785. case 71979:
  786. /* WinTV-HVR1200 (PCIe, OEM, half height)
  787. * DVB-T and basic analog */
  788. case 71999:
  789. /* WinTV-HVR1200 (PCIe, OEM, full height)
  790. * DVB-T and basic analog */
  791. case 76601:
  792. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  793. channel ATSC and MPEG2 HW Encoder */
  794. case 77001:
  795. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  796. and Basic analog */
  797. case 77011:
  798. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  799. and Basic analog */
  800. case 77041:
  801. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  802. and Basic analog */
  803. case 77051:
  804. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  805. and Basic analog */
  806. case 78011:
  807. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  808. Dual channel ATSC and MPEG2 HW Encoder */
  809. case 78501:
  810. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  811. Dual channel ATSC and MPEG2 HW Encoder */
  812. case 78521:
  813. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  814. Dual channel ATSC and MPEG2 HW Encoder */
  815. case 78531:
  816. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  817. Dual channel ATSC and MPEG2 HW Encoder */
  818. case 78631:
  819. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  820. Dual channel ATSC and MPEG2 HW Encoder */
  821. case 79001:
  822. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  823. ATSC and Basic analog */
  824. case 79101:
  825. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  826. ATSC and Basic analog */
  827. case 79501:
  828. /* WinTV-HVR1250 (PCIe, No IR, half height,
  829. ATSC [at least] and Basic analog) */
  830. case 79561:
  831. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  832. ATSC and Basic analog */
  833. case 79571:
  834. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  835. ATSC and Basic analog */
  836. case 79671:
  837. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  838. ATSC and Basic analog */
  839. case 80019:
  840. /* WinTV-HVR1400 (Express Card, Retail, IR,
  841. * DVB-T and Basic analog */
  842. case 81509:
  843. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  844. * DVB-T and MPEG2 HW Encoder */
  845. case 81519:
  846. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  847. * DVB-T and MPEG2 HW Encoder */
  848. break;
  849. case 85021:
  850. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  851. Dual channel ATSC and MPEG2 HW Encoder */
  852. break;
  853. case 85721:
  854. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  855. Dual channel ATSC and Basic analog */
  856. break;
  857. default:
  858. printk(KERN_WARNING "%s: warning: "
  859. "unknown hauppauge model #%d\n",
  860. dev->name, tv.model);
  861. break;
  862. }
  863. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  864. dev->name, tv.model);
  865. }
  866. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  867. {
  868. struct cx23885_tsport *port = priv;
  869. struct cx23885_dev *dev = port->dev;
  870. u32 bitmask = 0;
  871. if (command == XC2028_RESET_CLK)
  872. return 0;
  873. if (command != 0) {
  874. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  875. __func__, command);
  876. return -EINVAL;
  877. }
  878. switch (dev->board) {
  879. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  880. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  881. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  882. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  883. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  884. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  885. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  886. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  887. /* Tuner Reset Command */
  888. bitmask = 0x04;
  889. break;
  890. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  891. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  892. /* Two identical tuners on two different i2c buses,
  893. * we need to reset the correct gpio. */
  894. if (port->nr == 1)
  895. bitmask = 0x01;
  896. else if (port->nr == 2)
  897. bitmask = 0x04;
  898. break;
  899. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  900. /* Tuner Reset Command */
  901. bitmask = 0x02;
  902. break;
  903. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  904. altera_ci_tuner_reset(dev, port->nr);
  905. break;
  906. }
  907. if (bitmask) {
  908. /* Drive the tuner into reset and back out */
  909. cx_clear(GP0_IO, bitmask);
  910. mdelay(200);
  911. cx_set(GP0_IO, bitmask);
  912. }
  913. return 0;
  914. }
  915. void cx23885_gpio_setup(struct cx23885_dev *dev)
  916. {
  917. switch (dev->board) {
  918. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  919. /* GPIO-0 cx24227 demodulator reset */
  920. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  921. break;
  922. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  923. /* GPIO-0 cx24227 demodulator */
  924. /* GPIO-2 xc3028 tuner */
  925. /* Put the parts into reset */
  926. cx_set(GP0_IO, 0x00050000);
  927. cx_clear(GP0_IO, 0x00000005);
  928. msleep(5);
  929. /* Bring the parts out of reset */
  930. cx_set(GP0_IO, 0x00050005);
  931. break;
  932. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  933. /* GPIO-0 cx24227 demodulator reset */
  934. /* GPIO-2 xc5000 tuner reset */
  935. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  936. break;
  937. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  938. /* GPIO-0 656_CLK */
  939. /* GPIO-1 656_D0 */
  940. /* GPIO-2 8295A Reset */
  941. /* GPIO-3-10 cx23417 data0-7 */
  942. /* GPIO-11-14 cx23417 addr0-3 */
  943. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  944. /* GPIO-19 IR_RX */
  945. /* CX23417 GPIO's */
  946. /* EIO15 Zilog Reset */
  947. /* EIO14 S5H1409/CX24227 Reset */
  948. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  949. /* Put the demod into reset and protect the eeprom */
  950. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  951. mdelay(100);
  952. /* Bring the demod and blaster out of reset */
  953. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  954. mdelay(100);
  955. /* Force the TDA8295A into reset and back */
  956. cx23885_gpio_enable(dev, GPIO_2, 1);
  957. cx23885_gpio_set(dev, GPIO_2);
  958. mdelay(20);
  959. cx23885_gpio_clear(dev, GPIO_2);
  960. mdelay(20);
  961. cx23885_gpio_set(dev, GPIO_2);
  962. mdelay(20);
  963. break;
  964. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  965. /* GPIO-0 tda10048 demodulator reset */
  966. /* GPIO-2 tda18271 tuner reset */
  967. /* Put the parts into reset and back */
  968. cx_set(GP0_IO, 0x00050000);
  969. mdelay(20);
  970. cx_clear(GP0_IO, 0x00000005);
  971. mdelay(20);
  972. cx_set(GP0_IO, 0x00050005);
  973. break;
  974. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  975. /* GPIO-0 TDA10048 demodulator reset */
  976. /* GPIO-2 TDA8295A Reset */
  977. /* GPIO-3-10 cx23417 data0-7 */
  978. /* GPIO-11-14 cx23417 addr0-3 */
  979. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  980. /* The following GPIO's are on the interna AVCore (cx25840) */
  981. /* GPIO-19 IR_RX */
  982. /* GPIO-20 IR_TX 416/DVBT Select */
  983. /* GPIO-21 IIS DAT */
  984. /* GPIO-22 IIS WCLK */
  985. /* GPIO-23 IIS BCLK */
  986. /* Put the parts into reset and back */
  987. cx_set(GP0_IO, 0x00050000);
  988. mdelay(20);
  989. cx_clear(GP0_IO, 0x00000005);
  990. mdelay(20);
  991. cx_set(GP0_IO, 0x00050005);
  992. break;
  993. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  994. /* GPIO-0 Dibcom7000p demodulator reset */
  995. /* GPIO-2 xc3028L tuner reset */
  996. /* GPIO-13 LED */
  997. /* Put the parts into reset and back */
  998. cx_set(GP0_IO, 0x00050000);
  999. mdelay(20);
  1000. cx_clear(GP0_IO, 0x00000005);
  1001. mdelay(20);
  1002. cx_set(GP0_IO, 0x00050005);
  1003. break;
  1004. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1005. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  1006. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  1007. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  1008. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  1009. /* Put the parts into reset and back */
  1010. cx_set(GP0_IO, 0x000f0000);
  1011. mdelay(20);
  1012. cx_clear(GP0_IO, 0x0000000f);
  1013. mdelay(20);
  1014. cx_set(GP0_IO, 0x000f000f);
  1015. break;
  1016. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1017. /* GPIO-0 portb xc3028 reset */
  1018. /* GPIO-1 portb zl10353 reset */
  1019. /* GPIO-2 portc xc3028 reset */
  1020. /* GPIO-3 portc zl10353 reset */
  1021. /* Put the parts into reset and back */
  1022. cx_set(GP0_IO, 0x000f0000);
  1023. mdelay(20);
  1024. cx_clear(GP0_IO, 0x0000000f);
  1025. mdelay(20);
  1026. cx_set(GP0_IO, 0x000f000f);
  1027. break;
  1028. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1029. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1030. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1031. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1032. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1033. /* GPIO-2 xc3028 tuner reset */
  1034. /* The following GPIO's are on the internal AVCore (cx25840) */
  1035. /* GPIO-? zl10353 demod reset */
  1036. /* Put the parts into reset and back */
  1037. cx_set(GP0_IO, 0x00040000);
  1038. mdelay(20);
  1039. cx_clear(GP0_IO, 0x00000004);
  1040. mdelay(20);
  1041. cx_set(GP0_IO, 0x00040004);
  1042. break;
  1043. case CX23885_BOARD_TBS_6920:
  1044. cx_write(MC417_CTL, 0x00000036);
  1045. cx_write(MC417_OEN, 0x00001000);
  1046. cx_set(MC417_RWD, 0x00000002);
  1047. mdelay(200);
  1048. cx_clear(MC417_RWD, 0x00000800);
  1049. mdelay(200);
  1050. cx_set(MC417_RWD, 0x00000800);
  1051. mdelay(200);
  1052. break;
  1053. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1054. /* GPIO-0 INTA from CiMax1
  1055. GPIO-1 INTB from CiMax2
  1056. GPIO-2 reset chips
  1057. GPIO-3 to GPIO-10 data/addr for CA
  1058. GPIO-11 ~CS0 to CiMax1
  1059. GPIO-12 ~CS1 to CiMax2
  1060. GPIO-13 ADL0 load LSB addr
  1061. GPIO-14 ADL1 load MSB addr
  1062. GPIO-15 ~RDY from CiMax
  1063. GPIO-17 ~RD to CiMax
  1064. GPIO-18 ~WR to CiMax
  1065. */
  1066. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  1067. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  1068. cx_clear(GP0_IO, 0x00030004);
  1069. mdelay(100);/* reset delay */
  1070. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  1071. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  1072. /* GPIO-15 IN as ~ACK, rest as OUT */
  1073. cx_write(MC417_OEN, 0x00001000);
  1074. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  1075. cx_write(MC417_RWD, 0x0000c300);
  1076. /* enable irq */
  1077. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1078. break;
  1079. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1080. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1081. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1082. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1083. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  1084. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  1085. /* GPIO-9 Demod reset */
  1086. /* Put the parts into reset and back */
  1087. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  1088. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  1089. cx23885_gpio_clear(dev, GPIO_9);
  1090. mdelay(20);
  1091. cx23885_gpio_set(dev, GPIO_9);
  1092. break;
  1093. case CX23885_BOARD_MYGICA_X8506:
  1094. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1095. case CX23885_BOARD_MYGICA_X8507:
  1096. /* GPIO-0 (0)Analog / (1)Digital TV */
  1097. /* GPIO-1 reset XC5000 */
  1098. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  1099. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  1100. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  1101. mdelay(100);
  1102. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  1103. mdelay(100);
  1104. break;
  1105. case CX23885_BOARD_MYGICA_X8558PRO:
  1106. /* GPIO-0 reset first ATBM8830 */
  1107. /* GPIO-1 reset second ATBM8830 */
  1108. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  1109. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  1110. mdelay(100);
  1111. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  1112. mdelay(100);
  1113. break;
  1114. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1115. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1116. /* GPIO-0 656_CLK */
  1117. /* GPIO-1 656_D0 */
  1118. /* GPIO-2 Wake# */
  1119. /* GPIO-3-10 cx23417 data0-7 */
  1120. /* GPIO-11-14 cx23417 addr0-3 */
  1121. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1122. /* GPIO-19 IR_RX */
  1123. /* GPIO-20 C_IR_TX */
  1124. /* GPIO-21 I2S DAT */
  1125. /* GPIO-22 I2S WCLK */
  1126. /* GPIO-23 I2S BCLK */
  1127. /* ALT GPIO: EXP GPIO LATCH */
  1128. /* CX23417 GPIO's */
  1129. /* GPIO-14 S5H1411/CX24228 Reset */
  1130. /* GPIO-13 EEPROM write protect */
  1131. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  1132. /* Put the demod into reset and protect the eeprom */
  1133. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  1134. mdelay(100);
  1135. /* Bring the demod out of reset */
  1136. mc417_gpio_set(dev, GPIO_14);
  1137. mdelay(100);
  1138. /* CX24228 GPIO */
  1139. /* Connected to IF / Mux */
  1140. break;
  1141. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1142. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1143. break;
  1144. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1145. /* GPIO-0 ~INT in
  1146. GPIO-1 TMS out
  1147. GPIO-2 ~reset chips out
  1148. GPIO-3 to GPIO-10 data/addr for CA in/out
  1149. GPIO-11 ~CS out
  1150. GPIO-12 ADDR out
  1151. GPIO-13 ~WR out
  1152. GPIO-14 ~RD out
  1153. GPIO-15 ~RDY in
  1154. GPIO-16 TCK out
  1155. GPIO-17 TDO in
  1156. GPIO-18 TDI out
  1157. */
  1158. cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
  1159. /* GPIO-0 as INT, reset & TMS low */
  1160. cx_clear(GP0_IO, 0x00010006);
  1161. mdelay(100);/* reset delay */
  1162. cx_set(GP0_IO, 0x00000004); /* reset high */
  1163. cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
  1164. /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
  1165. cx_write(MC417_OEN, 0x00005000);
  1166. /* ~RD, ~WR high; ADDR low; ~CS high */
  1167. cx_write(MC417_RWD, 0x00000d00);
  1168. /* enable irq */
  1169. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1170. break;
  1171. }
  1172. }
  1173. int cx23885_ir_init(struct cx23885_dev *dev)
  1174. {
  1175. static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
  1176. {
  1177. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1178. .pin = CX23885_PIN_IR_RX_GPIO19,
  1179. .function = CX23885_PAD_IR_RX,
  1180. .value = 0,
  1181. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1182. }, {
  1183. .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
  1184. .pin = CX23885_PIN_IR_TX_GPIO20,
  1185. .function = CX23885_PAD_IR_TX,
  1186. .value = 0,
  1187. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1188. }
  1189. };
  1190. const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
  1191. static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
  1192. {
  1193. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1194. .pin = CX23885_PIN_IR_RX_GPIO19,
  1195. .function = CX23885_PAD_IR_RX,
  1196. .value = 0,
  1197. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1198. }
  1199. };
  1200. const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
  1201. struct v4l2_subdev_ir_parameters params;
  1202. int ret = 0;
  1203. switch (dev->board) {
  1204. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1205. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1206. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1207. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1208. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1209. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1210. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1211. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1212. /* FIXME: Implement me */
  1213. break;
  1214. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1215. ret = cx23888_ir_probe(dev);
  1216. if (ret)
  1217. break;
  1218. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1219. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1220. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1221. break;
  1222. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1223. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1224. ret = cx23888_ir_probe(dev);
  1225. if (ret)
  1226. break;
  1227. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1228. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1229. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1230. /*
  1231. * For these boards we need to invert the Tx output via the
  1232. * IR controller to have the LED off while idle
  1233. */
  1234. v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
  1235. params.enable = false;
  1236. params.shutdown = false;
  1237. params.invert_level = true;
  1238. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1239. params.shutdown = true;
  1240. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1241. break;
  1242. case CX23885_BOARD_TEVII_S470:
  1243. if (!enable_885_ir)
  1244. break;
  1245. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1246. if (dev->sd_ir == NULL) {
  1247. ret = -ENODEV;
  1248. break;
  1249. }
  1250. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1251. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1252. break;
  1253. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1254. if (!enable_885_ir)
  1255. break;
  1256. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1257. if (dev->sd_ir == NULL) {
  1258. ret = -ENODEV;
  1259. break;
  1260. }
  1261. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1262. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1263. break;
  1264. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1265. request_module("ir-kbd-i2c");
  1266. break;
  1267. }
  1268. return ret;
  1269. }
  1270. void cx23885_ir_fini(struct cx23885_dev *dev)
  1271. {
  1272. switch (dev->board) {
  1273. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1274. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1275. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1276. cx23885_irq_remove(dev, PCI_MSK_IR);
  1277. cx23888_ir_remove(dev);
  1278. dev->sd_ir = NULL;
  1279. break;
  1280. case CX23885_BOARD_TEVII_S470:
  1281. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1282. cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
  1283. /* sd_ir is a duplicate pointer to the AV Core, just clear it */
  1284. dev->sd_ir = NULL;
  1285. break;
  1286. }
  1287. }
  1288. int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
  1289. {
  1290. int data;
  1291. int tdo = 0;
  1292. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  1293. /*TMS*/
  1294. data = ((cx_read(GP0_IO)) & (~0x00000002));
  1295. data |= (tms ? 0x00020002 : 0x00020000);
  1296. cx_write(GP0_IO, data);
  1297. /*TDI*/
  1298. data = ((cx_read(MC417_RWD)) & (~0x0000a000));
  1299. data |= (tdi ? 0x00008000 : 0);
  1300. cx_write(MC417_RWD, data);
  1301. if (read_tdo)
  1302. tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
  1303. cx_write(MC417_RWD, data | 0x00002000);
  1304. udelay(1);
  1305. /*TCK*/
  1306. cx_write(MC417_RWD, data);
  1307. return tdo;
  1308. }
  1309. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  1310. {
  1311. switch (dev->board) {
  1312. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1313. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1314. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1315. if (dev->sd_ir)
  1316. cx23885_irq_add_enable(dev, PCI_MSK_IR);
  1317. break;
  1318. case CX23885_BOARD_TEVII_S470:
  1319. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1320. if (dev->sd_ir)
  1321. cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
  1322. break;
  1323. }
  1324. }
  1325. void cx23885_card_setup(struct cx23885_dev *dev)
  1326. {
  1327. struct cx23885_tsport *ts1 = &dev->ts1;
  1328. struct cx23885_tsport *ts2 = &dev->ts2;
  1329. static u8 eeprom[256];
  1330. if (dev->i2c_bus[0].i2c_rc == 0) {
  1331. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1332. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  1333. eeprom, sizeof(eeprom));
  1334. }
  1335. switch (dev->board) {
  1336. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1337. if (dev->i2c_bus[0].i2c_rc == 0) {
  1338. if (eeprom[0x80] != 0x84)
  1339. hauppauge_eeprom(dev, eeprom+0xc0);
  1340. else
  1341. hauppauge_eeprom(dev, eeprom+0x80);
  1342. }
  1343. break;
  1344. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1345. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1346. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1347. if (dev->i2c_bus[0].i2c_rc == 0)
  1348. hauppauge_eeprom(dev, eeprom+0x80);
  1349. break;
  1350. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1351. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1352. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1353. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1354. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1355. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1356. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1357. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1358. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1359. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1360. if (dev->i2c_bus[0].i2c_rc == 0)
  1361. hauppauge_eeprom(dev, eeprom+0xc0);
  1362. break;
  1363. }
  1364. switch (dev->board) {
  1365. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1366. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1367. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1368. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1369. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1370. /* break omitted intentionally */
  1371. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  1372. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1373. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1374. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1375. break;
  1376. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1377. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1378. /* Defaults for VID B - Analog encoder */
  1379. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  1380. ts1->gen_ctrl_val = 0x10e;
  1381. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1382. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1383. /* APB_TSVALERR_POL (active low)*/
  1384. ts1->vld_misc_val = 0x2000;
  1385. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  1386. cx_write(0x130184, 0xc);
  1387. /* Defaults for VID C */
  1388. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1389. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1390. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1391. break;
  1392. case CX23885_BOARD_TBS_6920:
  1393. ts1->gen_ctrl_val = 0x4; /* Parallel */
  1394. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1395. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1396. break;
  1397. case CX23885_BOARD_TEVII_S470:
  1398. case CX23885_BOARD_DVBWORLD_2005:
  1399. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1400. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1401. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1402. break;
  1403. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1404. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1405. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1406. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1407. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1408. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1409. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1410. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1411. break;
  1412. case CX23885_BOARD_MYGICA_X8506:
  1413. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1414. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1415. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1416. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1417. break;
  1418. case CX23885_BOARD_MYGICA_X8558PRO:
  1419. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1420. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1421. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1422. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1423. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1424. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1425. break;
  1426. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1427. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1428. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1429. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1430. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1431. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1432. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1433. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1434. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1435. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1436. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1437. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1438. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1439. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1440. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1441. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1442. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1443. default:
  1444. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1445. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1446. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1447. }
  1448. /* Certain boards support analog, or require the avcore to be
  1449. * loaded, ensure this happens.
  1450. */
  1451. switch (dev->board) {
  1452. case CX23885_BOARD_TEVII_S470:
  1453. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1454. /* Currently only enabled for the integrated IR controller */
  1455. if (!enable_885_ir)
  1456. break;
  1457. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1458. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1459. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1460. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1461. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1462. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1463. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1464. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1465. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1466. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1467. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1468. case CX23885_BOARD_MYGICA_X8506:
  1469. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1470. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1471. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1472. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1473. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1474. case CX23885_BOARD_MPX885:
  1475. case CX23885_BOARD_MYGICA_X8507:
  1476. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1477. &dev->i2c_bus[2].i2c_adap,
  1478. "cx25840", 0x88 >> 1, NULL);
  1479. if (dev->sd_cx25840) {
  1480. dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
  1481. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1482. }
  1483. break;
  1484. }
  1485. /* AUX-PLL 27MHz CLK */
  1486. switch (dev->board) {
  1487. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1488. netup_initialize(dev);
  1489. break;
  1490. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1491. int ret;
  1492. const struct firmware *fw;
  1493. const char *filename = "dvb-netup-altera-01.fw";
  1494. char *action = "configure";
  1495. static struct netup_card_info cinfo;
  1496. struct altera_config netup_config = {
  1497. .dev = dev,
  1498. .action = action,
  1499. .jtag_io = netup_jtag_io,
  1500. };
  1501. netup_initialize(dev);
  1502. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1503. if (netup_card_rev)
  1504. cinfo.rev = netup_card_rev;
  1505. switch (cinfo.rev) {
  1506. case 0x4:
  1507. filename = "dvb-netup-altera-04.fw";
  1508. break;
  1509. default:
  1510. filename = "dvb-netup-altera-01.fw";
  1511. break;
  1512. }
  1513. printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
  1514. cinfo.rev, filename);
  1515. ret = request_firmware(&fw, filename, &dev->pci->dev);
  1516. if (ret != 0)
  1517. printk(KERN_ERR "did not find the firmware file. (%s) "
  1518. "Please see linux/Documentation/dvb/ for more details "
  1519. "on firmware-problems.", filename);
  1520. else
  1521. altera_init(&netup_config, fw);
  1522. release_firmware(fw);
  1523. break;
  1524. }
  1525. }
  1526. }
  1527. /* ------------------------------------------------------------------ */