cx23885-dvb.c 28 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "tda10048.h"
  39. #include "tuner-xc2028.h"
  40. #include "tuner-simple.h"
  41. #include "dib7000p.h"
  42. #include "dibx000_common.h"
  43. #include "zl10353.h"
  44. #include "stv0900.h"
  45. #include "stv0900_reg.h"
  46. #include "stv6110.h"
  47. #include "lnbh24.h"
  48. #include "cx24116.h"
  49. #include "cimax2.h"
  50. #include "lgs8gxx.h"
  51. #include "netup-eeprom.h"
  52. #include "netup-init.h"
  53. #include "lgdt3305.h"
  54. static unsigned int debug;
  55. #define dprintk(level, fmt, arg...)\
  56. do { if (debug >= level)\
  57. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  58. } while (0)
  59. /* ------------------------------------------------------------------ */
  60. static unsigned int alt_tuner;
  61. module_param(alt_tuner, int, 0644);
  62. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  63. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  64. /* ------------------------------------------------------------------ */
  65. static int dvb_buf_setup(struct videobuf_queue *q,
  66. unsigned int *count, unsigned int *size)
  67. {
  68. struct cx23885_tsport *port = q->priv_data;
  69. port->ts_packet_size = 188 * 4;
  70. port->ts_packet_count = 32;
  71. *size = port->ts_packet_size * port->ts_packet_count;
  72. *count = 32;
  73. return 0;
  74. }
  75. static int dvb_buf_prepare(struct videobuf_queue *q,
  76. struct videobuf_buffer *vb, enum v4l2_field field)
  77. {
  78. struct cx23885_tsport *port = q->priv_data;
  79. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  80. }
  81. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  82. {
  83. struct cx23885_tsport *port = q->priv_data;
  84. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  85. }
  86. static void dvb_buf_release(struct videobuf_queue *q,
  87. struct videobuf_buffer *vb)
  88. {
  89. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  90. }
  91. static struct videobuf_queue_ops dvb_qops = {
  92. .buf_setup = dvb_buf_setup,
  93. .buf_prepare = dvb_buf_prepare,
  94. .buf_queue = dvb_buf_queue,
  95. .buf_release = dvb_buf_release,
  96. };
  97. static struct s5h1409_config hauppauge_generic_config = {
  98. .demod_address = 0x32 >> 1,
  99. .output_mode = S5H1409_SERIAL_OUTPUT,
  100. .gpio = S5H1409_GPIO_ON,
  101. .qam_if = 44000,
  102. .inversion = S5H1409_INVERSION_OFF,
  103. .status_mode = S5H1409_DEMODLOCKING,
  104. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  105. };
  106. static struct tda10048_config hauppauge_hvr1200_config = {
  107. .demod_address = 0x10 >> 1,
  108. .output_mode = TDA10048_SERIAL_OUTPUT,
  109. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  110. .inversion = TDA10048_INVERSION_ON,
  111. .dtv6_if_freq_khz = TDA10048_IF_3300,
  112. .dtv7_if_freq_khz = TDA10048_IF_3800,
  113. .dtv8_if_freq_khz = TDA10048_IF_4300,
  114. .clk_freq_khz = TDA10048_CLK_16000,
  115. };
  116. static struct tda10048_config hauppauge_hvr1210_config = {
  117. .demod_address = 0x10 >> 1,
  118. .output_mode = TDA10048_SERIAL_OUTPUT,
  119. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  120. .inversion = TDA10048_INVERSION_ON,
  121. .dtv6_if_freq_khz = TDA10048_IF_3300,
  122. .dtv7_if_freq_khz = TDA10048_IF_3500,
  123. .dtv8_if_freq_khz = TDA10048_IF_4000,
  124. .clk_freq_khz = TDA10048_CLK_16000,
  125. };
  126. static struct s5h1409_config hauppauge_ezqam_config = {
  127. .demod_address = 0x32 >> 1,
  128. .output_mode = S5H1409_SERIAL_OUTPUT,
  129. .gpio = S5H1409_GPIO_OFF,
  130. .qam_if = 4000,
  131. .inversion = S5H1409_INVERSION_ON,
  132. .status_mode = S5H1409_DEMODLOCKING,
  133. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  134. };
  135. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  136. .demod_address = 0x32 >> 1,
  137. .output_mode = S5H1409_SERIAL_OUTPUT,
  138. .gpio = S5H1409_GPIO_OFF,
  139. .qam_if = 44000,
  140. .inversion = S5H1409_INVERSION_OFF,
  141. .status_mode = S5H1409_DEMODLOCKING,
  142. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  143. };
  144. static struct s5h1409_config hauppauge_hvr1500_config = {
  145. .demod_address = 0x32 >> 1,
  146. .output_mode = S5H1409_SERIAL_OUTPUT,
  147. .gpio = S5H1409_GPIO_OFF,
  148. .inversion = S5H1409_INVERSION_OFF,
  149. .status_mode = S5H1409_DEMODLOCKING,
  150. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  151. };
  152. static struct mt2131_config hauppauge_generic_tunerconfig = {
  153. 0x61
  154. };
  155. static struct lgdt330x_config fusionhdtv_5_express = {
  156. .demod_address = 0x0e,
  157. .demod_chip = LGDT3303,
  158. .serial_mpeg = 0x40,
  159. };
  160. static struct s5h1409_config hauppauge_hvr1500q_config = {
  161. .demod_address = 0x32 >> 1,
  162. .output_mode = S5H1409_SERIAL_OUTPUT,
  163. .gpio = S5H1409_GPIO_ON,
  164. .qam_if = 44000,
  165. .inversion = S5H1409_INVERSION_OFF,
  166. .status_mode = S5H1409_DEMODLOCKING,
  167. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  168. };
  169. static struct s5h1409_config dvico_s5h1409_config = {
  170. .demod_address = 0x32 >> 1,
  171. .output_mode = S5H1409_SERIAL_OUTPUT,
  172. .gpio = S5H1409_GPIO_ON,
  173. .qam_if = 44000,
  174. .inversion = S5H1409_INVERSION_OFF,
  175. .status_mode = S5H1409_DEMODLOCKING,
  176. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  177. };
  178. static struct s5h1411_config dvico_s5h1411_config = {
  179. .output_mode = S5H1411_SERIAL_OUTPUT,
  180. .gpio = S5H1411_GPIO_ON,
  181. .qam_if = S5H1411_IF_44000,
  182. .vsb_if = S5H1411_IF_44000,
  183. .inversion = S5H1411_INVERSION_OFF,
  184. .status_mode = S5H1411_DEMODLOCKING,
  185. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  186. };
  187. static struct s5h1411_config hcw_s5h1411_config = {
  188. .output_mode = S5H1411_SERIAL_OUTPUT,
  189. .gpio = S5H1411_GPIO_OFF,
  190. .vsb_if = S5H1411_IF_44000,
  191. .qam_if = S5H1411_IF_4000,
  192. .inversion = S5H1411_INVERSION_ON,
  193. .status_mode = S5H1411_DEMODLOCKING,
  194. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  197. .i2c_address = 0x61,
  198. .if_khz = 5380,
  199. };
  200. static struct xc5000_config dvico_xc5000_tunerconfig = {
  201. .i2c_address = 0x64,
  202. .if_khz = 5380,
  203. };
  204. static struct tda829x_config tda829x_no_probe = {
  205. .probe_tuner = TDA829X_DONT_PROBE,
  206. };
  207. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  208. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  209. .if_lvl = 6, .rfagc_top = 0x37 },
  210. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  211. .if_lvl = 6, .rfagc_top = 0x37 },
  212. };
  213. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  214. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  215. .if_lvl = 1, .rfagc_top = 0x37, },
  216. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  217. .if_lvl = 1, .rfagc_top = 0x37, },
  218. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  219. .if_lvl = 1, .rfagc_top = 0x37, },
  220. };
  221. static struct tda18271_config hauppauge_tda18271_config = {
  222. .std_map = &hauppauge_tda18271_std_map,
  223. .gate = TDA18271_GATE_ANALOG,
  224. .output_opt = TDA18271_OUTPUT_LT_OFF,
  225. };
  226. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  227. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  228. .gate = TDA18271_GATE_ANALOG,
  229. .output_opt = TDA18271_OUTPUT_LT_OFF,
  230. };
  231. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  232. .gate = TDA18271_GATE_DIGITAL,
  233. .output_opt = TDA18271_OUTPUT_LT_OFF,
  234. };
  235. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  236. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  237. .if_lvl = 1, .rfagc_top = 0x58 },
  238. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  239. .if_lvl = 1, .rfagc_top = 0x58 },
  240. };
  241. static struct tda18271_config hauppauge_hvr127x_config = {
  242. .std_map = &hauppauge_hvr127x_std_map,
  243. .output_opt = TDA18271_OUTPUT_LT_OFF,
  244. };
  245. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  246. .i2c_addr = 0x0e,
  247. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  248. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  249. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  250. .deny_i2c_rptr = 1,
  251. .spectral_inversion = 1,
  252. .qam_if_khz = 4000,
  253. .vsb_if_khz = 3250,
  254. };
  255. static struct dibx000_agc_config xc3028_agc_config = {
  256. BAND_VHF | BAND_UHF, /* band_caps */
  257. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  258. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  259. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  260. * P_agc_nb_est=2, P_agc_write=0
  261. */
  262. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  263. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  264. 712, /* inv_gain */
  265. 21, /* time_stabiliz */
  266. 0, /* alpha_level */
  267. 118, /* thlock */
  268. 0, /* wbd_inv */
  269. 2867, /* wbd_ref */
  270. 0, /* wbd_sel */
  271. 2, /* wbd_alpha */
  272. 0, /* agc1_max */
  273. 0, /* agc1_min */
  274. 39718, /* agc2_max */
  275. 9930, /* agc2_min */
  276. 0, /* agc1_pt1 */
  277. 0, /* agc1_pt2 */
  278. 0, /* agc1_pt3 */
  279. 0, /* agc1_slope1 */
  280. 0, /* agc1_slope2 */
  281. 0, /* agc2_pt1 */
  282. 128, /* agc2_pt2 */
  283. 29, /* agc2_slope1 */
  284. 29, /* agc2_slope2 */
  285. 17, /* alpha_mant */
  286. 27, /* alpha_exp */
  287. 23, /* beta_mant */
  288. 51, /* beta_exp */
  289. 1, /* perform_agc_softsplit */
  290. };
  291. /* PLL Configuration for COFDM BW_MHz = 8.000000
  292. * With external clock = 30.000000 */
  293. static struct dibx000_bandwidth_config xc3028_bw_config = {
  294. 60000, /* internal */
  295. 30000, /* sampling */
  296. 1, /* pll_cfg: prediv */
  297. 8, /* pll_cfg: ratio */
  298. 3, /* pll_cfg: range */
  299. 1, /* pll_cfg: reset */
  300. 0, /* pll_cfg: bypass */
  301. 0, /* misc: refdiv */
  302. 0, /* misc: bypclk_div */
  303. 1, /* misc: IO_CLK_en_core */
  304. 1, /* misc: ADClkSrc */
  305. 0, /* misc: modulo */
  306. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  307. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  308. 20452225, /* timf */
  309. 30000000 /* xtal_hz */
  310. };
  311. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  312. .output_mpeg2_in_188_bytes = 1,
  313. .hostbus_diversity = 1,
  314. .tuner_is_baseband = 0,
  315. .update_lna = NULL,
  316. .agc_config_count = 1,
  317. .agc = &xc3028_agc_config,
  318. .bw = &xc3028_bw_config,
  319. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  320. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  321. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  322. .pwm_freq_div = 0,
  323. .agc_control = NULL,
  324. .spur_protect = 0,
  325. .output_mode = OUTMODE_MPEG2_SERIAL,
  326. };
  327. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  328. .demod_address = 0x0f,
  329. .if2 = 45600,
  330. .no_tuner = 1,
  331. .disable_i2c_gate_ctrl = 1,
  332. };
  333. static struct stv0900_reg stv0900_ts_regs[] = {
  334. { R0900_TSGENERAL, 0x00 },
  335. { R0900_P1_TSSPEED, 0x40 },
  336. { R0900_P2_TSSPEED, 0x40 },
  337. { R0900_P1_TSCFGM, 0xc0 },
  338. { R0900_P2_TSCFGM, 0xc0 },
  339. { R0900_P1_TSCFGH, 0xe0 },
  340. { R0900_P2_TSCFGH, 0xe0 },
  341. { R0900_P1_TSCFGL, 0x20 },
  342. { R0900_P2_TSCFGL, 0x20 },
  343. { 0xffff, 0xff }, /* terminate */
  344. };
  345. static struct stv0900_config netup_stv0900_config = {
  346. .demod_address = 0x68,
  347. .xtal = 8000000,
  348. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  349. .diseqc_mode = 2,/* 2/3 PWM */
  350. .ts_config_regs = stv0900_ts_regs,
  351. .tun1_maddress = 0,/* 0x60 */
  352. .tun2_maddress = 3,/* 0x63 */
  353. .tun1_adc = 1,/* 1 Vpp */
  354. .tun2_adc = 1,/* 1 Vpp */
  355. };
  356. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  357. .i2c_address = 0x60,
  358. .mclk = 16000000,
  359. .clk_div = 1,
  360. };
  361. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  362. .i2c_address = 0x63,
  363. .mclk = 16000000,
  364. .clk_div = 1,
  365. };
  366. static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  367. {
  368. struct cx23885_tsport *port = fe->dvb->priv;
  369. struct cx23885_dev *dev = port->dev;
  370. if (voltage == SEC_VOLTAGE_18)
  371. cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
  372. else if (voltage == SEC_VOLTAGE_13)
  373. cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
  374. else
  375. cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
  376. return 0;
  377. }
  378. static struct cx24116_config tbs_cx24116_config = {
  379. .demod_address = 0x05,
  380. };
  381. static struct cx24116_config tevii_cx24116_config = {
  382. .demod_address = 0x55,
  383. };
  384. static struct cx24116_config dvbworld_cx24116_config = {
  385. .demod_address = 0x05,
  386. };
  387. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  388. .prod = LGS8GXX_PROD_LGS8GL5,
  389. .demod_address = 0x19,
  390. .serial_ts = 0,
  391. .ts_clk_pol = 1,
  392. .ts_clk_gated = 1,
  393. .if_clk_freq = 30400, /* 30.4 MHz */
  394. .if_freq = 5380, /* 5.38 MHz */
  395. .if_neg_center = 1,
  396. .ext_adc = 0,
  397. .adc_signed = 0,
  398. .if_neg_edge = 0,
  399. };
  400. static struct xc5000_config mygica_x8506_xc5000_config = {
  401. .i2c_address = 0x61,
  402. .if_khz = 5380,
  403. };
  404. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
  405. struct dvb_frontend_parameters *param)
  406. {
  407. struct cx23885_tsport *port = fe->dvb->priv;
  408. struct cx23885_dev *dev = port->dev;
  409. switch (dev->board) {
  410. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  411. switch (param->u.vsb.modulation) {
  412. case VSB_8:
  413. cx23885_gpio_clear(dev, GPIO_5);
  414. break;
  415. case QAM_64:
  416. case QAM_256:
  417. default:
  418. cx23885_gpio_set(dev, GPIO_5);
  419. break;
  420. }
  421. break;
  422. }
  423. return (port->set_frontend_save) ?
  424. port->set_frontend_save(fe, param) : -ENODEV;
  425. }
  426. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  427. .prod = LGS8GXX_PROD_LGS8G75,
  428. .demod_address = 0x19,
  429. .serial_ts = 0,
  430. .ts_clk_pol = 1,
  431. .ts_clk_gated = 1,
  432. .if_clk_freq = 30400, /* 30.4 MHz */
  433. .if_freq = 6500, /* 6.50 MHz */
  434. .if_neg_center = 1,
  435. .ext_adc = 0,
  436. .adc_signed = 1,
  437. .adc_vpp = 2, /* 1.6 Vpp */
  438. .if_neg_edge = 1,
  439. };
  440. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  441. .i2c_address = 0x61,
  442. .if_khz = 6500,
  443. };
  444. static int dvb_register(struct cx23885_tsport *port)
  445. {
  446. struct cx23885_dev *dev = port->dev;
  447. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  448. struct videobuf_dvb_frontend *fe0;
  449. int ret;
  450. /* Get the first frontend */
  451. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  452. if (!fe0)
  453. return -EINVAL;
  454. /* init struct videobuf_dvb */
  455. fe0->dvb.name = dev->name;
  456. /* init frontend */
  457. switch (dev->board) {
  458. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  459. i2c_bus = &dev->i2c_bus[0];
  460. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  461. &hauppauge_generic_config,
  462. &i2c_bus->i2c_adap);
  463. if (fe0->dvb.frontend != NULL) {
  464. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  465. &i2c_bus->i2c_adap,
  466. &hauppauge_generic_tunerconfig, 0);
  467. }
  468. break;
  469. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  470. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  471. i2c_bus = &dev->i2c_bus[0];
  472. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  473. &hauppauge_lgdt3305_config,
  474. &i2c_bus->i2c_adap);
  475. if (fe0->dvb.frontend != NULL) {
  476. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  477. 0x60, &dev->i2c_bus[1].i2c_adap,
  478. &hauppauge_hvr127x_config);
  479. }
  480. /* FIXME: temporary hack */
  481. /* define bridge override to set_frontend */
  482. port->set_frontend_save = fe0->dvb.frontend->ops.set_frontend;
  483. fe0->dvb.frontend->ops.set_frontend = cx23885_dvb_set_frontend;
  484. break;
  485. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  486. i2c_bus = &dev->i2c_bus[0];
  487. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  488. &hcw_s5h1411_config,
  489. &i2c_bus->i2c_adap);
  490. if (fe0->dvb.frontend != NULL) {
  491. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  492. 0x60, &dev->i2c_bus[1].i2c_adap,
  493. &hauppauge_tda18271_config);
  494. }
  495. break;
  496. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  497. i2c_bus = &dev->i2c_bus[0];
  498. switch (alt_tuner) {
  499. case 1:
  500. fe0->dvb.frontend =
  501. dvb_attach(s5h1409_attach,
  502. &hauppauge_ezqam_config,
  503. &i2c_bus->i2c_adap);
  504. if (fe0->dvb.frontend != NULL) {
  505. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  506. &dev->i2c_bus[1].i2c_adap, 0x42,
  507. &tda829x_no_probe);
  508. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  509. 0x60, &dev->i2c_bus[1].i2c_adap,
  510. &hauppauge_tda18271_config);
  511. }
  512. break;
  513. case 0:
  514. default:
  515. fe0->dvb.frontend =
  516. dvb_attach(s5h1409_attach,
  517. &hauppauge_generic_config,
  518. &i2c_bus->i2c_adap);
  519. if (fe0->dvb.frontend != NULL)
  520. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  521. &i2c_bus->i2c_adap,
  522. &hauppauge_generic_tunerconfig, 0);
  523. break;
  524. }
  525. break;
  526. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  527. i2c_bus = &dev->i2c_bus[0];
  528. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  529. &hauppauge_hvr1800lp_config,
  530. &i2c_bus->i2c_adap);
  531. if (fe0->dvb.frontend != NULL) {
  532. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  533. &i2c_bus->i2c_adap,
  534. &hauppauge_generic_tunerconfig, 0);
  535. }
  536. break;
  537. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  538. i2c_bus = &dev->i2c_bus[0];
  539. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  540. &fusionhdtv_5_express,
  541. &i2c_bus->i2c_adap);
  542. if (fe0->dvb.frontend != NULL) {
  543. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  544. &i2c_bus->i2c_adap, 0x61,
  545. TUNER_LG_TDVS_H06XF);
  546. }
  547. break;
  548. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  549. i2c_bus = &dev->i2c_bus[1];
  550. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  551. &hauppauge_hvr1500q_config,
  552. &dev->i2c_bus[0].i2c_adap);
  553. if (fe0->dvb.frontend != NULL)
  554. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  555. &i2c_bus->i2c_adap,
  556. &hauppauge_hvr1500q_tunerconfig);
  557. break;
  558. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  559. i2c_bus = &dev->i2c_bus[1];
  560. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  561. &hauppauge_hvr1500_config,
  562. &dev->i2c_bus[0].i2c_adap);
  563. if (fe0->dvb.frontend != NULL) {
  564. struct dvb_frontend *fe;
  565. struct xc2028_config cfg = {
  566. .i2c_adap = &i2c_bus->i2c_adap,
  567. .i2c_addr = 0x61,
  568. };
  569. static struct xc2028_ctrl ctl = {
  570. .fname = XC2028_DEFAULT_FIRMWARE,
  571. .max_len = 64,
  572. .demod = XC3028_FE_OREN538,
  573. };
  574. fe = dvb_attach(xc2028_attach,
  575. fe0->dvb.frontend, &cfg);
  576. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  577. fe->ops.tuner_ops.set_config(fe, &ctl);
  578. }
  579. break;
  580. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  581. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  582. i2c_bus = &dev->i2c_bus[0];
  583. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  584. &hauppauge_hvr1200_config,
  585. &i2c_bus->i2c_adap);
  586. if (fe0->dvb.frontend != NULL) {
  587. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  588. &dev->i2c_bus[1].i2c_adap, 0x42,
  589. &tda829x_no_probe);
  590. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  591. 0x60, &dev->i2c_bus[1].i2c_adap,
  592. &hauppauge_hvr1200_tuner_config);
  593. }
  594. break;
  595. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  596. i2c_bus = &dev->i2c_bus[0];
  597. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  598. &hauppauge_hvr1210_config,
  599. &i2c_bus->i2c_adap);
  600. if (fe0->dvb.frontend != NULL) {
  601. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  602. 0x60, &dev->i2c_bus[1].i2c_adap,
  603. &hauppauge_hvr1210_tuner_config);
  604. }
  605. break;
  606. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  607. i2c_bus = &dev->i2c_bus[0];
  608. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  609. &i2c_bus->i2c_adap,
  610. 0x12, &hauppauge_hvr1400_dib7000_config);
  611. if (fe0->dvb.frontend != NULL) {
  612. struct dvb_frontend *fe;
  613. struct xc2028_config cfg = {
  614. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  615. .i2c_addr = 0x64,
  616. };
  617. static struct xc2028_ctrl ctl = {
  618. .fname = XC3028L_DEFAULT_FIRMWARE,
  619. .max_len = 64,
  620. .demod = 5000,
  621. /* This is true for all demods with
  622. v36 firmware? */
  623. .type = XC2028_D2633,
  624. };
  625. fe = dvb_attach(xc2028_attach,
  626. fe0->dvb.frontend, &cfg);
  627. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  628. fe->ops.tuner_ops.set_config(fe, &ctl);
  629. }
  630. break;
  631. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  632. i2c_bus = &dev->i2c_bus[port->nr - 1];
  633. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  634. &dvico_s5h1409_config,
  635. &i2c_bus->i2c_adap);
  636. if (fe0->dvb.frontend == NULL)
  637. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  638. &dvico_s5h1411_config,
  639. &i2c_bus->i2c_adap);
  640. if (fe0->dvb.frontend != NULL)
  641. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  642. &i2c_bus->i2c_adap,
  643. &dvico_xc5000_tunerconfig);
  644. break;
  645. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  646. i2c_bus = &dev->i2c_bus[port->nr - 1];
  647. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  648. &dvico_fusionhdtv_xc3028,
  649. &i2c_bus->i2c_adap);
  650. if (fe0->dvb.frontend != NULL) {
  651. struct dvb_frontend *fe;
  652. struct xc2028_config cfg = {
  653. .i2c_adap = &i2c_bus->i2c_adap,
  654. .i2c_addr = 0x61,
  655. };
  656. static struct xc2028_ctrl ctl = {
  657. .fname = XC2028_DEFAULT_FIRMWARE,
  658. .max_len = 64,
  659. .demod = XC3028_FE_ZARLINK456,
  660. };
  661. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  662. &cfg);
  663. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  664. fe->ops.tuner_ops.set_config(fe, &ctl);
  665. }
  666. break;
  667. }
  668. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  669. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  670. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  671. i2c_bus = &dev->i2c_bus[0];
  672. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  673. &dvico_fusionhdtv_xc3028,
  674. &i2c_bus->i2c_adap);
  675. if (fe0->dvb.frontend != NULL) {
  676. struct dvb_frontend *fe;
  677. struct xc2028_config cfg = {
  678. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  679. .i2c_addr = 0x61,
  680. };
  681. static struct xc2028_ctrl ctl = {
  682. .fname = XC2028_DEFAULT_FIRMWARE,
  683. .max_len = 64,
  684. .demod = XC3028_FE_ZARLINK456,
  685. };
  686. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  687. &cfg);
  688. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  689. fe->ops.tuner_ops.set_config(fe, &ctl);
  690. }
  691. break;
  692. case CX23885_BOARD_TBS_6920:
  693. i2c_bus = &dev->i2c_bus[0];
  694. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  695. &tbs_cx24116_config,
  696. &i2c_bus->i2c_adap);
  697. if (fe0->dvb.frontend != NULL)
  698. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  699. break;
  700. case CX23885_BOARD_TEVII_S470:
  701. i2c_bus = &dev->i2c_bus[1];
  702. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  703. &tevii_cx24116_config,
  704. &i2c_bus->i2c_adap);
  705. if (fe0->dvb.frontend != NULL)
  706. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  707. break;
  708. case CX23885_BOARD_DVBWORLD_2005:
  709. i2c_bus = &dev->i2c_bus[1];
  710. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  711. &dvbworld_cx24116_config,
  712. &i2c_bus->i2c_adap);
  713. break;
  714. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  715. i2c_bus = &dev->i2c_bus[0];
  716. switch (port->nr) {
  717. /* port B */
  718. case 1:
  719. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  720. &netup_stv0900_config,
  721. &i2c_bus->i2c_adap, 0);
  722. if (fe0->dvb.frontend != NULL) {
  723. if (dvb_attach(stv6110_attach,
  724. fe0->dvb.frontend,
  725. &netup_stv6110_tunerconfig_a,
  726. &i2c_bus->i2c_adap)) {
  727. if (!dvb_attach(lnbh24_attach,
  728. fe0->dvb.frontend,
  729. &i2c_bus->i2c_adap,
  730. LNBH24_PCL,
  731. LNBH24_TTX, 0x09))
  732. printk(KERN_ERR
  733. "No LNBH24 found!\n");
  734. }
  735. }
  736. break;
  737. /* port C */
  738. case 2:
  739. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  740. &netup_stv0900_config,
  741. &i2c_bus->i2c_adap, 1);
  742. if (fe0->dvb.frontend != NULL) {
  743. if (dvb_attach(stv6110_attach,
  744. fe0->dvb.frontend,
  745. &netup_stv6110_tunerconfig_b,
  746. &i2c_bus->i2c_adap)) {
  747. if (!dvb_attach(lnbh24_attach,
  748. fe0->dvb.frontend,
  749. &i2c_bus->i2c_adap,
  750. LNBH24_PCL,
  751. LNBH24_TTX, 0x0a))
  752. printk(KERN_ERR
  753. "No LNBH24 found!\n");
  754. }
  755. }
  756. break;
  757. }
  758. break;
  759. case CX23885_BOARD_MYGICA_X8506:
  760. i2c_bus = &dev->i2c_bus[0];
  761. i2c_bus2 = &dev->i2c_bus[1];
  762. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  763. &mygica_x8506_lgs8gl5_config,
  764. &i2c_bus->i2c_adap);
  765. if (fe0->dvb.frontend != NULL) {
  766. dvb_attach(xc5000_attach,
  767. fe0->dvb.frontend,
  768. &i2c_bus2->i2c_adap,
  769. &mygica_x8506_xc5000_config);
  770. }
  771. break;
  772. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  773. i2c_bus = &dev->i2c_bus[0];
  774. i2c_bus2 = &dev->i2c_bus[1];
  775. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  776. &magicpro_prohdtve2_lgs8g75_config,
  777. &i2c_bus->i2c_adap);
  778. if (fe0->dvb.frontend != NULL) {
  779. dvb_attach(xc5000_attach,
  780. fe0->dvb.frontend,
  781. &i2c_bus2->i2c_adap,
  782. &magicpro_prohdtve2_xc5000_config);
  783. }
  784. break;
  785. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  786. i2c_bus = &dev->i2c_bus[0];
  787. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  788. &hcw_s5h1411_config,
  789. &i2c_bus->i2c_adap);
  790. if (fe0->dvb.frontend != NULL)
  791. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  792. 0x60, &dev->i2c_bus[0].i2c_adap,
  793. &hauppauge_tda18271_config);
  794. break;
  795. default:
  796. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  797. " isn't supported yet\n",
  798. dev->name);
  799. break;
  800. }
  801. if (NULL == fe0->dvb.frontend) {
  802. printk(KERN_ERR "%s: frontend initialization failed\n",
  803. dev->name);
  804. return -1;
  805. }
  806. /* define general-purpose callback pointer */
  807. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  808. /* Put the analog decoder in standby to keep it quiet */
  809. call_all(dev, tuner, s_standby);
  810. if (fe0->dvb.frontend->ops.analog_ops.standby)
  811. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  812. /* register everything */
  813. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  814. &dev->pci->dev, adapter_nr, 0);
  815. /* init CI & MAC */
  816. switch (dev->board) {
  817. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  818. static struct netup_card_info cinfo;
  819. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  820. memcpy(port->frontends.adapter.proposed_mac,
  821. cinfo.port[port->nr - 1].mac, 6);
  822. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
  823. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  824. port->nr,
  825. port->frontends.adapter.proposed_mac[0],
  826. port->frontends.adapter.proposed_mac[1],
  827. port->frontends.adapter.proposed_mac[2],
  828. port->frontends.adapter.proposed_mac[3],
  829. port->frontends.adapter.proposed_mac[4],
  830. port->frontends.adapter.proposed_mac[5]);
  831. netup_ci_init(port);
  832. break;
  833. }
  834. }
  835. return ret;
  836. }
  837. int cx23885_dvb_register(struct cx23885_tsport *port)
  838. {
  839. struct videobuf_dvb_frontend *fe0;
  840. struct cx23885_dev *dev = port->dev;
  841. int err, i;
  842. /* Here we need to allocate the correct number of frontends,
  843. * as reflected in the cards struct. The reality is that currrently
  844. * no cx23885 boards support this - yet. But, if we don't modify this
  845. * code then the second frontend would never be allocated (later)
  846. * and fail with error before the attach in dvb_register().
  847. * Without these changes we risk an OOPS later. The changes here
  848. * are for safety, and should provide a good foundation for the
  849. * future addition of any multi-frontend cx23885 based boards.
  850. */
  851. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  852. port->num_frontends);
  853. for (i = 1; i <= port->num_frontends; i++) {
  854. if (videobuf_dvb_alloc_frontend(
  855. &port->frontends, i) == NULL) {
  856. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  857. return -ENOMEM;
  858. }
  859. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  860. if (!fe0)
  861. err = -EINVAL;
  862. dprintk(1, "%s\n", __func__);
  863. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  864. dev->board,
  865. dev->name,
  866. dev->pci_bus,
  867. dev->pci_slot);
  868. err = -ENODEV;
  869. /* dvb stuff */
  870. /* We have to init the queue for each frontend on a port. */
  871. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  872. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  873. &dev->pci->dev, &port->slock,
  874. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  875. sizeof(struct cx23885_buffer), port);
  876. }
  877. err = dvb_register(port);
  878. if (err != 0)
  879. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  880. __func__, err);
  881. return err;
  882. }
  883. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  884. {
  885. struct videobuf_dvb_frontend *fe0;
  886. /* FIXME: in an error condition where the we have
  887. * an expected number of frontends (attach problem)
  888. * then this might not clean up correctly, if 1
  889. * is invalid.
  890. * This comment only applies to future boards IF they
  891. * implement MFE support.
  892. */
  893. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  894. if (fe0->dvb.frontend)
  895. videobuf_dvb_unregister_bus(&port->frontends);
  896. switch (port->dev->board) {
  897. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  898. netup_ci_exit(port);
  899. break;
  900. }
  901. return 0;
  902. }