atomic.h 17 KB

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  1. /*
  2. * Atomic operations that C can't guarantee us. Useful for
  3. * resource counting etc..
  4. *
  5. * But use these as seldom as possible since they are much more slower
  6. * than regular operations.
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. *
  12. * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
  13. */
  14. #ifndef _ASM_ATOMIC_H
  15. #define _ASM_ATOMIC_H
  16. #include <linux/irqflags.h>
  17. #include <asm/cpu-features.h>
  18. #include <asm/war.h>
  19. typedef struct { volatile int counter; } atomic_t;
  20. #define ATOMIC_INIT(i) { (i) }
  21. /*
  22. * atomic_read - read atomic variable
  23. * @v: pointer of type atomic_t
  24. *
  25. * Atomically reads the value of @v.
  26. */
  27. #define atomic_read(v) ((v)->counter)
  28. /*
  29. * atomic_set - set atomic variable
  30. * @v: pointer of type atomic_t
  31. * @i: required value
  32. *
  33. * Atomically sets the value of @v to @i.
  34. */
  35. #define atomic_set(v,i) ((v)->counter = (i))
  36. /*
  37. * atomic_add - add integer to atomic variable
  38. * @i: integer value to add
  39. * @v: pointer of type atomic_t
  40. *
  41. * Atomically adds @i to @v.
  42. */
  43. static __inline__ void atomic_add(int i, atomic_t * v)
  44. {
  45. if (cpu_has_llsc && R10000_LLSC_WAR) {
  46. unsigned long temp;
  47. __asm__ __volatile__(
  48. " .set mips3 \n"
  49. "1: ll %0, %1 # atomic_add \n"
  50. " addu %0, %2 \n"
  51. " sc %0, %1 \n"
  52. " beqzl %0, 1b \n"
  53. " .set mips0 \n"
  54. : "=&r" (temp), "=m" (v->counter)
  55. : "Ir" (i), "m" (v->counter));
  56. } else if (cpu_has_llsc) {
  57. unsigned long temp;
  58. __asm__ __volatile__(
  59. " .set mips3 \n"
  60. "1: ll %0, %1 # atomic_add \n"
  61. " addu %0, %2 \n"
  62. " sc %0, %1 \n"
  63. " beqz %0, 1b \n"
  64. " .set mips0 \n"
  65. : "=&r" (temp), "=m" (v->counter)
  66. : "Ir" (i), "m" (v->counter));
  67. } else {
  68. unsigned long flags;
  69. local_irq_save(flags);
  70. v->counter += i;
  71. local_irq_restore(flags);
  72. }
  73. }
  74. /*
  75. * atomic_sub - subtract the atomic variable
  76. * @i: integer value to subtract
  77. * @v: pointer of type atomic_t
  78. *
  79. * Atomically subtracts @i from @v.
  80. */
  81. static __inline__ void atomic_sub(int i, atomic_t * v)
  82. {
  83. if (cpu_has_llsc && R10000_LLSC_WAR) {
  84. unsigned long temp;
  85. __asm__ __volatile__(
  86. " .set mips3 \n"
  87. "1: ll %0, %1 # atomic_sub \n"
  88. " subu %0, %2 \n"
  89. " sc %0, %1 \n"
  90. " beqzl %0, 1b \n"
  91. " .set mips0 \n"
  92. : "=&r" (temp), "=m" (v->counter)
  93. : "Ir" (i), "m" (v->counter));
  94. } else if (cpu_has_llsc) {
  95. unsigned long temp;
  96. __asm__ __volatile__(
  97. " .set mips3 \n"
  98. "1: ll %0, %1 # atomic_sub \n"
  99. " subu %0, %2 \n"
  100. " sc %0, %1 \n"
  101. " beqz %0, 1b \n"
  102. " .set mips0 \n"
  103. : "=&r" (temp), "=m" (v->counter)
  104. : "Ir" (i), "m" (v->counter));
  105. } else {
  106. unsigned long flags;
  107. local_irq_save(flags);
  108. v->counter -= i;
  109. local_irq_restore(flags);
  110. }
  111. }
  112. /*
  113. * Same as above, but return the result value
  114. */
  115. static __inline__ int atomic_add_return(int i, atomic_t * v)
  116. {
  117. unsigned long result;
  118. if (cpu_has_llsc && R10000_LLSC_WAR) {
  119. unsigned long temp;
  120. __asm__ __volatile__(
  121. " .set mips3 \n"
  122. "1: ll %1, %2 # atomic_add_return \n"
  123. " addu %0, %1, %3 \n"
  124. " sc %0, %2 \n"
  125. " beqzl %0, 1b \n"
  126. " addu %0, %1, %3 \n"
  127. " sync \n"
  128. " .set mips0 \n"
  129. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  130. : "Ir" (i), "m" (v->counter)
  131. : "memory");
  132. } else if (cpu_has_llsc) {
  133. unsigned long temp;
  134. __asm__ __volatile__(
  135. " .set mips3 \n"
  136. "1: ll %1, %2 # atomic_add_return \n"
  137. " addu %0, %1, %3 \n"
  138. " sc %0, %2 \n"
  139. " beqz %0, 1b \n"
  140. " addu %0, %1, %3 \n"
  141. " sync \n"
  142. " .set mips0 \n"
  143. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  144. : "Ir" (i), "m" (v->counter)
  145. : "memory");
  146. } else {
  147. unsigned long flags;
  148. local_irq_save(flags);
  149. result = v->counter;
  150. result += i;
  151. v->counter = result;
  152. local_irq_restore(flags);
  153. }
  154. return result;
  155. }
  156. static __inline__ int atomic_sub_return(int i, atomic_t * v)
  157. {
  158. unsigned long result;
  159. if (cpu_has_llsc && R10000_LLSC_WAR) {
  160. unsigned long temp;
  161. __asm__ __volatile__(
  162. " .set mips3 \n"
  163. "1: ll %1, %2 # atomic_sub_return \n"
  164. " subu %0, %1, %3 \n"
  165. " sc %0, %2 \n"
  166. " beqzl %0, 1b \n"
  167. " subu %0, %1, %3 \n"
  168. " sync \n"
  169. " .set mips0 \n"
  170. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  171. : "Ir" (i), "m" (v->counter)
  172. : "memory");
  173. } else if (cpu_has_llsc) {
  174. unsigned long temp;
  175. __asm__ __volatile__(
  176. " .set mips3 \n"
  177. "1: ll %1, %2 # atomic_sub_return \n"
  178. " subu %0, %1, %3 \n"
  179. " sc %0, %2 \n"
  180. " beqz %0, 1b \n"
  181. " subu %0, %1, %3 \n"
  182. " sync \n"
  183. " .set mips0 \n"
  184. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  185. : "Ir" (i), "m" (v->counter)
  186. : "memory");
  187. } else {
  188. unsigned long flags;
  189. local_irq_save(flags);
  190. result = v->counter;
  191. result -= i;
  192. v->counter = result;
  193. local_irq_restore(flags);
  194. }
  195. return result;
  196. }
  197. /*
  198. * atomic_sub_if_positive - conditionally subtract integer from atomic variable
  199. * @i: integer value to subtract
  200. * @v: pointer of type atomic_t
  201. *
  202. * Atomically test @v and subtract @i if @v is greater or equal than @i.
  203. * The function returns the old value of @v minus @i.
  204. */
  205. static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
  206. {
  207. unsigned long result;
  208. if (cpu_has_llsc && R10000_LLSC_WAR) {
  209. unsigned long temp;
  210. __asm__ __volatile__(
  211. " .set mips3 \n"
  212. "1: ll %1, %2 # atomic_sub_if_positive\n"
  213. " subu %0, %1, %3 \n"
  214. " bltz %0, 1f \n"
  215. " sc %0, %2 \n"
  216. " .set noreorder \n"
  217. " beqzl %0, 1b \n"
  218. " subu %0, %1, %3 \n"
  219. " .set reorder \n"
  220. " sync \n"
  221. "1: \n"
  222. " .set mips0 \n"
  223. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  224. : "Ir" (i), "m" (v->counter)
  225. : "memory");
  226. } else if (cpu_has_llsc) {
  227. unsigned long temp;
  228. __asm__ __volatile__(
  229. " .set mips3 \n"
  230. "1: ll %1, %2 # atomic_sub_if_positive\n"
  231. " subu %0, %1, %3 \n"
  232. " bltz %0, 1f \n"
  233. " sc %0, %2 \n"
  234. " .set noreorder \n"
  235. " beqz %0, 1b \n"
  236. " subu %0, %1, %3 \n"
  237. " .set reorder \n"
  238. " sync \n"
  239. "1: \n"
  240. " .set mips0 \n"
  241. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  242. : "Ir" (i), "m" (v->counter)
  243. : "memory");
  244. } else {
  245. unsigned long flags;
  246. local_irq_save(flags);
  247. result = v->counter;
  248. result -= i;
  249. if (result >= 0)
  250. v->counter = result;
  251. local_irq_restore(flags);
  252. }
  253. return result;
  254. }
  255. #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
  256. #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
  257. /**
  258. * atomic_add_unless - add unless the number is a given value
  259. * @v: pointer of type atomic_t
  260. * @a: the amount to add to v...
  261. * @u: ...unless v is equal to u.
  262. *
  263. * Atomically adds @a to @v, so long as it was not @u.
  264. * Returns non-zero if @v was not @u, and zero otherwise.
  265. */
  266. #define atomic_add_unless(v, a, u) \
  267. ({ \
  268. int c, old; \
  269. c = atomic_read(v); \
  270. while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
  271. c = old; \
  272. c != (u); \
  273. })
  274. #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
  275. #define atomic_dec_return(v) atomic_sub_return(1,(v))
  276. #define atomic_inc_return(v) atomic_add_return(1,(v))
  277. /*
  278. * atomic_sub_and_test - subtract value from variable and test result
  279. * @i: integer value to subtract
  280. * @v: pointer of type atomic_t
  281. *
  282. * Atomically subtracts @i from @v and returns
  283. * true if the result is zero, or false for all
  284. * other cases.
  285. */
  286. #define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
  287. /*
  288. * atomic_inc_and_test - increment and test
  289. * @v: pointer of type atomic_t
  290. *
  291. * Atomically increments @v by 1
  292. * and returns true if the result is zero, or false for all
  293. * other cases.
  294. */
  295. #define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
  296. /*
  297. * atomic_dec_and_test - decrement by 1 and test
  298. * @v: pointer of type atomic_t
  299. *
  300. * Atomically decrements @v by 1 and
  301. * returns true if the result is 0, or false for all other
  302. * cases.
  303. */
  304. #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
  305. /*
  306. * atomic_dec_if_positive - decrement by 1 if old value positive
  307. * @v: pointer of type atomic_t
  308. */
  309. #define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
  310. /*
  311. * atomic_inc - increment atomic variable
  312. * @v: pointer of type atomic_t
  313. *
  314. * Atomically increments @v by 1.
  315. */
  316. #define atomic_inc(v) atomic_add(1,(v))
  317. /*
  318. * atomic_dec - decrement and test
  319. * @v: pointer of type atomic_t
  320. *
  321. * Atomically decrements @v by 1.
  322. */
  323. #define atomic_dec(v) atomic_sub(1,(v))
  324. /*
  325. * atomic_add_negative - add and test if negative
  326. * @v: pointer of type atomic_t
  327. * @i: integer value to add
  328. *
  329. * Atomically adds @i to @v and returns true
  330. * if the result is negative, or false when
  331. * result is greater than or equal to zero.
  332. */
  333. #define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0)
  334. #ifdef CONFIG_64BIT
  335. typedef struct { volatile __s64 counter; } atomic64_t;
  336. #define ATOMIC64_INIT(i) { (i) }
  337. /*
  338. * atomic64_read - read atomic variable
  339. * @v: pointer of type atomic64_t
  340. *
  341. */
  342. #define atomic64_read(v) ((v)->counter)
  343. /*
  344. * atomic64_set - set atomic variable
  345. * @v: pointer of type atomic64_t
  346. * @i: required value
  347. */
  348. #define atomic64_set(v,i) ((v)->counter = (i))
  349. /*
  350. * atomic64_add - add integer to atomic variable
  351. * @i: integer value to add
  352. * @v: pointer of type atomic64_t
  353. *
  354. * Atomically adds @i to @v.
  355. */
  356. static __inline__ void atomic64_add(long i, atomic64_t * v)
  357. {
  358. if (cpu_has_llsc && R10000_LLSC_WAR) {
  359. unsigned long temp;
  360. __asm__ __volatile__(
  361. " .set mips3 \n"
  362. "1: lld %0, %1 # atomic64_add \n"
  363. " addu %0, %2 \n"
  364. " scd %0, %1 \n"
  365. " beqzl %0, 1b \n"
  366. " .set mips0 \n"
  367. : "=&r" (temp), "=m" (v->counter)
  368. : "Ir" (i), "m" (v->counter));
  369. } else if (cpu_has_llsc) {
  370. unsigned long temp;
  371. __asm__ __volatile__(
  372. " .set mips3 \n"
  373. "1: lld %0, %1 # atomic64_add \n"
  374. " addu %0, %2 \n"
  375. " scd %0, %1 \n"
  376. " beqz %0, 1b \n"
  377. " .set mips0 \n"
  378. : "=&r" (temp), "=m" (v->counter)
  379. : "Ir" (i), "m" (v->counter));
  380. } else {
  381. unsigned long flags;
  382. local_irq_save(flags);
  383. v->counter += i;
  384. local_irq_restore(flags);
  385. }
  386. }
  387. /*
  388. * atomic64_sub - subtract the atomic variable
  389. * @i: integer value to subtract
  390. * @v: pointer of type atomic64_t
  391. *
  392. * Atomically subtracts @i from @v.
  393. */
  394. static __inline__ void atomic64_sub(long i, atomic64_t * v)
  395. {
  396. if (cpu_has_llsc && R10000_LLSC_WAR) {
  397. unsigned long temp;
  398. __asm__ __volatile__(
  399. " .set mips3 \n"
  400. "1: lld %0, %1 # atomic64_sub \n"
  401. " subu %0, %2 \n"
  402. " scd %0, %1 \n"
  403. " beqzl %0, 1b \n"
  404. " .set mips0 \n"
  405. : "=&r" (temp), "=m" (v->counter)
  406. : "Ir" (i), "m" (v->counter));
  407. } else if (cpu_has_llsc) {
  408. unsigned long temp;
  409. __asm__ __volatile__(
  410. " .set mips3 \n"
  411. "1: lld %0, %1 # atomic64_sub \n"
  412. " subu %0, %2 \n"
  413. " scd %0, %1 \n"
  414. " beqz %0, 1b \n"
  415. " .set mips0 \n"
  416. : "=&r" (temp), "=m" (v->counter)
  417. : "Ir" (i), "m" (v->counter));
  418. } else {
  419. unsigned long flags;
  420. local_irq_save(flags);
  421. v->counter -= i;
  422. local_irq_restore(flags);
  423. }
  424. }
  425. /*
  426. * Same as above, but return the result value
  427. */
  428. static __inline__ long atomic64_add_return(long i, atomic64_t * v)
  429. {
  430. unsigned long result;
  431. if (cpu_has_llsc && R10000_LLSC_WAR) {
  432. unsigned long temp;
  433. __asm__ __volatile__(
  434. " .set mips3 \n"
  435. "1: lld %1, %2 # atomic64_add_return \n"
  436. " addu %0, %1, %3 \n"
  437. " scd %0, %2 \n"
  438. " beqzl %0, 1b \n"
  439. " addu %0, %1, %3 \n"
  440. " sync \n"
  441. " .set mips0 \n"
  442. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  443. : "Ir" (i), "m" (v->counter)
  444. : "memory");
  445. } else if (cpu_has_llsc) {
  446. unsigned long temp;
  447. __asm__ __volatile__(
  448. " .set mips3 \n"
  449. "1: lld %1, %2 # atomic64_add_return \n"
  450. " addu %0, %1, %3 \n"
  451. " scd %0, %2 \n"
  452. " beqz %0, 1b \n"
  453. " addu %0, %1, %3 \n"
  454. " sync \n"
  455. " .set mips0 \n"
  456. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  457. : "Ir" (i), "m" (v->counter)
  458. : "memory");
  459. } else {
  460. unsigned long flags;
  461. local_irq_save(flags);
  462. result = v->counter;
  463. result += i;
  464. v->counter = result;
  465. local_irq_restore(flags);
  466. }
  467. return result;
  468. }
  469. static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
  470. {
  471. unsigned long result;
  472. if (cpu_has_llsc && R10000_LLSC_WAR) {
  473. unsigned long temp;
  474. __asm__ __volatile__(
  475. " .set mips3 \n"
  476. "1: lld %1, %2 # atomic64_sub_return \n"
  477. " subu %0, %1, %3 \n"
  478. " scd %0, %2 \n"
  479. " beqzl %0, 1b \n"
  480. " subu %0, %1, %3 \n"
  481. " sync \n"
  482. " .set mips0 \n"
  483. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  484. : "Ir" (i), "m" (v->counter)
  485. : "memory");
  486. } else if (cpu_has_llsc) {
  487. unsigned long temp;
  488. __asm__ __volatile__(
  489. " .set mips3 \n"
  490. "1: lld %1, %2 # atomic64_sub_return \n"
  491. " subu %0, %1, %3 \n"
  492. " scd %0, %2 \n"
  493. " beqz %0, 1b \n"
  494. " subu %0, %1, %3 \n"
  495. " sync \n"
  496. " .set mips0 \n"
  497. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  498. : "Ir" (i), "m" (v->counter)
  499. : "memory");
  500. } else {
  501. unsigned long flags;
  502. local_irq_save(flags);
  503. result = v->counter;
  504. result -= i;
  505. v->counter = result;
  506. local_irq_restore(flags);
  507. }
  508. return result;
  509. }
  510. /*
  511. * atomic64_sub_if_positive - conditionally subtract integer from atomic variable
  512. * @i: integer value to subtract
  513. * @v: pointer of type atomic64_t
  514. *
  515. * Atomically test @v and subtract @i if @v is greater or equal than @i.
  516. * The function returns the old value of @v minus @i.
  517. */
  518. static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
  519. {
  520. unsigned long result;
  521. if (cpu_has_llsc && R10000_LLSC_WAR) {
  522. unsigned long temp;
  523. __asm__ __volatile__(
  524. " .set mips3 \n"
  525. "1: lld %1, %2 # atomic64_sub_if_positive\n"
  526. " dsubu %0, %1, %3 \n"
  527. " bltz %0, 1f \n"
  528. " scd %0, %2 \n"
  529. " .set noreorder \n"
  530. " beqzl %0, 1b \n"
  531. " dsubu %0, %1, %3 \n"
  532. " .set reorder \n"
  533. " sync \n"
  534. "1: \n"
  535. " .set mips0 \n"
  536. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  537. : "Ir" (i), "m" (v->counter)
  538. : "memory");
  539. } else if (cpu_has_llsc) {
  540. unsigned long temp;
  541. __asm__ __volatile__(
  542. " .set mips3 \n"
  543. "1: lld %1, %2 # atomic64_sub_if_positive\n"
  544. " dsubu %0, %1, %3 \n"
  545. " bltz %0, 1f \n"
  546. " scd %0, %2 \n"
  547. " .set noreorder \n"
  548. " beqz %0, 1b \n"
  549. " dsubu %0, %1, %3 \n"
  550. " .set reorder \n"
  551. " sync \n"
  552. "1: \n"
  553. " .set mips0 \n"
  554. : "=&r" (result), "=&r" (temp), "=m" (v->counter)
  555. : "Ir" (i), "m" (v->counter)
  556. : "memory");
  557. } else {
  558. unsigned long flags;
  559. local_irq_save(flags);
  560. result = v->counter;
  561. result -= i;
  562. if (result >= 0)
  563. v->counter = result;
  564. local_irq_restore(flags);
  565. }
  566. return result;
  567. }
  568. #define atomic64_dec_return(v) atomic64_sub_return(1,(v))
  569. #define atomic64_inc_return(v) atomic64_add_return(1,(v))
  570. /*
  571. * atomic64_sub_and_test - subtract value from variable and test result
  572. * @i: integer value to subtract
  573. * @v: pointer of type atomic64_t
  574. *
  575. * Atomically subtracts @i from @v and returns
  576. * true if the result is zero, or false for all
  577. * other cases.
  578. */
  579. #define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
  580. /*
  581. * atomic64_inc_and_test - increment and test
  582. * @v: pointer of type atomic64_t
  583. *
  584. * Atomically increments @v by 1
  585. * and returns true if the result is zero, or false for all
  586. * other cases.
  587. */
  588. #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
  589. /*
  590. * atomic64_dec_and_test - decrement by 1 and test
  591. * @v: pointer of type atomic64_t
  592. *
  593. * Atomically decrements @v by 1 and
  594. * returns true if the result is 0, or false for all other
  595. * cases.
  596. */
  597. #define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
  598. /*
  599. * atomic64_dec_if_positive - decrement by 1 if old value positive
  600. * @v: pointer of type atomic64_t
  601. */
  602. #define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
  603. /*
  604. * atomic64_inc - increment atomic variable
  605. * @v: pointer of type atomic64_t
  606. *
  607. * Atomically increments @v by 1.
  608. */
  609. #define atomic64_inc(v) atomic64_add(1,(v))
  610. /*
  611. * atomic64_dec - decrement and test
  612. * @v: pointer of type atomic64_t
  613. *
  614. * Atomically decrements @v by 1.
  615. */
  616. #define atomic64_dec(v) atomic64_sub(1,(v))
  617. /*
  618. * atomic64_add_negative - add and test if negative
  619. * @v: pointer of type atomic64_t
  620. * @i: integer value to add
  621. *
  622. * Atomically adds @i to @v and returns true
  623. * if the result is negative, or false when
  624. * result is greater than or equal to zero.
  625. */
  626. #define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0)
  627. #endif /* CONFIG_64BIT */
  628. /*
  629. * atomic*_return operations are serializing but not the non-*_return
  630. * versions.
  631. */
  632. #define smp_mb__before_atomic_dec() smp_mb()
  633. #define smp_mb__after_atomic_dec() smp_mb()
  634. #define smp_mb__before_atomic_inc() smp_mb()
  635. #define smp_mb__after_atomic_inc() smp_mb()
  636. #include <asm-generic/atomic.h>
  637. #endif /* _ASM_ATOMIC_H */