soc-cache.c 37 KB

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  1. /*
  2. * soc-cache.c -- ASoC register cache helpers
  3. *
  4. * Copyright 2009 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/i2c.h>
  14. #include <linux/spi/spi.h>
  15. #include <sound/soc.h>
  16. #include <linux/lzo.h>
  17. #include <linux/bitmap.h>
  18. #include <linux/rbtree.h>
  19. #include <trace/events/asoc.h>
  20. static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
  21. unsigned int reg)
  22. {
  23. int ret;
  24. unsigned int val;
  25. if (reg >= codec->driver->reg_cache_size ||
  26. snd_soc_codec_volatile_register(codec, reg) ||
  27. codec->cache_bypass) {
  28. if (codec->cache_only)
  29. return -1;
  30. BUG_ON(!codec->hw_read);
  31. return codec->hw_read(codec, reg);
  32. }
  33. ret = snd_soc_cache_read(codec, reg, &val);
  34. if (ret < 0)
  35. return -1;
  36. return val;
  37. }
  38. static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
  39. unsigned int value)
  40. {
  41. u8 data[2];
  42. int ret;
  43. data[0] = (reg << 4) | ((value >> 8) & 0x000f);
  44. data[1] = value & 0x00ff;
  45. if (!snd_soc_codec_volatile_register(codec, reg) &&
  46. reg < codec->driver->reg_cache_size &&
  47. !codec->cache_bypass) {
  48. ret = snd_soc_cache_write(codec, reg, value);
  49. if (ret < 0)
  50. return -1;
  51. }
  52. if (codec->cache_only) {
  53. codec->cache_sync = 1;
  54. return 0;
  55. }
  56. ret = codec->hw_write(codec->control_data, data, 2);
  57. if (ret == 2)
  58. return 0;
  59. if (ret < 0)
  60. return ret;
  61. else
  62. return -EIO;
  63. }
  64. #if defined(CONFIG_SPI_MASTER)
  65. static int snd_soc_4_12_spi_write(void *control_data, const char *data,
  66. int len)
  67. {
  68. struct spi_device *spi = control_data;
  69. struct spi_transfer t;
  70. struct spi_message m;
  71. u8 msg[2];
  72. if (len <= 0)
  73. return 0;
  74. msg[0] = data[1];
  75. msg[1] = data[0];
  76. spi_message_init(&m);
  77. memset(&t, 0, sizeof t);
  78. t.tx_buf = &msg[0];
  79. t.len = len;
  80. spi_message_add_tail(&t, &m);
  81. spi_sync(spi, &m);
  82. return len;
  83. }
  84. #else
  85. #define snd_soc_4_12_spi_write NULL
  86. #endif
  87. static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
  88. unsigned int reg)
  89. {
  90. int ret;
  91. unsigned int val;
  92. if (reg >= codec->driver->reg_cache_size ||
  93. snd_soc_codec_volatile_register(codec, reg) ||
  94. codec->cache_bypass) {
  95. if (codec->cache_only)
  96. return -1;
  97. BUG_ON(!codec->hw_read);
  98. return codec->hw_read(codec, reg);
  99. }
  100. ret = snd_soc_cache_read(codec, reg, &val);
  101. if (ret < 0)
  102. return -1;
  103. return val;
  104. }
  105. static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
  106. unsigned int value)
  107. {
  108. u8 data[2];
  109. int ret;
  110. data[0] = (reg << 1) | ((value >> 8) & 0x0001);
  111. data[1] = value & 0x00ff;
  112. if (!snd_soc_codec_volatile_register(codec, reg) &&
  113. reg < codec->driver->reg_cache_size &&
  114. !codec->cache_bypass) {
  115. ret = snd_soc_cache_write(codec, reg, value);
  116. if (ret < 0)
  117. return -1;
  118. }
  119. if (codec->cache_only) {
  120. codec->cache_sync = 1;
  121. return 0;
  122. }
  123. ret = codec->hw_write(codec->control_data, data, 2);
  124. if (ret == 2)
  125. return 0;
  126. if (ret < 0)
  127. return ret;
  128. else
  129. return -EIO;
  130. }
  131. #if defined(CONFIG_SPI_MASTER)
  132. static int snd_soc_7_9_spi_write(void *control_data, const char *data,
  133. int len)
  134. {
  135. struct spi_device *spi = control_data;
  136. struct spi_transfer t;
  137. struct spi_message m;
  138. u8 msg[2];
  139. if (len <= 0)
  140. return 0;
  141. msg[0] = data[0];
  142. msg[1] = data[1];
  143. spi_message_init(&m);
  144. memset(&t, 0, sizeof t);
  145. t.tx_buf = &msg[0];
  146. t.len = len;
  147. spi_message_add_tail(&t, &m);
  148. spi_sync(spi, &m);
  149. return len;
  150. }
  151. #else
  152. #define snd_soc_7_9_spi_write NULL
  153. #endif
  154. static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
  155. unsigned int value)
  156. {
  157. u8 data[2];
  158. int ret;
  159. reg &= 0xff;
  160. data[0] = reg;
  161. data[1] = value & 0xff;
  162. if (!snd_soc_codec_volatile_register(codec, reg) &&
  163. reg < codec->driver->reg_cache_size &&
  164. !codec->cache_bypass) {
  165. ret = snd_soc_cache_write(codec, reg, value);
  166. if (ret < 0)
  167. return -1;
  168. }
  169. if (codec->cache_only) {
  170. codec->cache_sync = 1;
  171. return 0;
  172. }
  173. if (codec->hw_write(codec->control_data, data, 2) == 2)
  174. return 0;
  175. else
  176. return -EIO;
  177. }
  178. static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
  179. unsigned int reg)
  180. {
  181. int ret;
  182. unsigned int val;
  183. reg &= 0xff;
  184. if (reg >= codec->driver->reg_cache_size ||
  185. snd_soc_codec_volatile_register(codec, reg) ||
  186. codec->cache_bypass) {
  187. if (codec->cache_only)
  188. return -1;
  189. BUG_ON(!codec->hw_read);
  190. return codec->hw_read(codec, reg);
  191. }
  192. ret = snd_soc_cache_read(codec, reg, &val);
  193. if (ret < 0)
  194. return -1;
  195. return val;
  196. }
  197. #if defined(CONFIG_SPI_MASTER)
  198. static int snd_soc_8_8_spi_write(void *control_data, const char *data,
  199. int len)
  200. {
  201. struct spi_device *spi = control_data;
  202. struct spi_transfer t;
  203. struct spi_message m;
  204. u8 msg[2];
  205. if (len <= 0)
  206. return 0;
  207. msg[0] = data[0];
  208. msg[1] = data[1];
  209. spi_message_init(&m);
  210. memset(&t, 0, sizeof t);
  211. t.tx_buf = &msg[0];
  212. t.len = len;
  213. spi_message_add_tail(&t, &m);
  214. spi_sync(spi, &m);
  215. return len;
  216. }
  217. #else
  218. #define snd_soc_8_8_spi_write NULL
  219. #endif
  220. static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
  221. unsigned int value)
  222. {
  223. u8 data[3];
  224. int ret;
  225. data[0] = reg;
  226. data[1] = (value >> 8) & 0xff;
  227. data[2] = value & 0xff;
  228. if (!snd_soc_codec_volatile_register(codec, reg) &&
  229. reg < codec->driver->reg_cache_size &&
  230. !codec->cache_bypass) {
  231. ret = snd_soc_cache_write(codec, reg, value);
  232. if (ret < 0)
  233. return -1;
  234. }
  235. if (codec->cache_only) {
  236. codec->cache_sync = 1;
  237. return 0;
  238. }
  239. if (codec->hw_write(codec->control_data, data, 3) == 3)
  240. return 0;
  241. else
  242. return -EIO;
  243. }
  244. static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
  245. unsigned int reg)
  246. {
  247. int ret;
  248. unsigned int val;
  249. if (reg >= codec->driver->reg_cache_size ||
  250. snd_soc_codec_volatile_register(codec, reg) ||
  251. codec->cache_bypass) {
  252. if (codec->cache_only)
  253. return -1;
  254. BUG_ON(!codec->hw_read);
  255. return codec->hw_read(codec, reg);
  256. }
  257. ret = snd_soc_cache_read(codec, reg, &val);
  258. if (ret < 0)
  259. return -1;
  260. return val;
  261. }
  262. #if defined(CONFIG_SPI_MASTER)
  263. static int snd_soc_8_16_spi_write(void *control_data, const char *data,
  264. int len)
  265. {
  266. struct spi_device *spi = control_data;
  267. struct spi_transfer t;
  268. struct spi_message m;
  269. u8 msg[3];
  270. if (len <= 0)
  271. return 0;
  272. msg[0] = data[0];
  273. msg[1] = data[1];
  274. msg[2] = data[2];
  275. spi_message_init(&m);
  276. memset(&t, 0, sizeof t);
  277. t.tx_buf = &msg[0];
  278. t.len = len;
  279. spi_message_add_tail(&t, &m);
  280. spi_sync(spi, &m);
  281. return len;
  282. }
  283. #else
  284. #define snd_soc_8_16_spi_write NULL
  285. #endif
  286. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  287. static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
  288. unsigned int r)
  289. {
  290. struct i2c_msg xfer[2];
  291. u8 reg = r;
  292. u8 data;
  293. int ret;
  294. struct i2c_client *client = codec->control_data;
  295. /* Write register */
  296. xfer[0].addr = client->addr;
  297. xfer[0].flags = 0;
  298. xfer[0].len = 1;
  299. xfer[0].buf = &reg;
  300. /* Read data */
  301. xfer[1].addr = client->addr;
  302. xfer[1].flags = I2C_M_RD;
  303. xfer[1].len = 1;
  304. xfer[1].buf = &data;
  305. ret = i2c_transfer(client->adapter, xfer, 2);
  306. if (ret != 2) {
  307. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  308. return 0;
  309. }
  310. return data;
  311. }
  312. #else
  313. #define snd_soc_8_8_read_i2c NULL
  314. #endif
  315. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  316. static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
  317. unsigned int r)
  318. {
  319. struct i2c_msg xfer[2];
  320. u8 reg = r;
  321. u16 data;
  322. int ret;
  323. struct i2c_client *client = codec->control_data;
  324. /* Write register */
  325. xfer[0].addr = client->addr;
  326. xfer[0].flags = 0;
  327. xfer[0].len = 1;
  328. xfer[0].buf = &reg;
  329. /* Read data */
  330. xfer[1].addr = client->addr;
  331. xfer[1].flags = I2C_M_RD;
  332. xfer[1].len = 2;
  333. xfer[1].buf = (u8 *)&data;
  334. ret = i2c_transfer(client->adapter, xfer, 2);
  335. if (ret != 2) {
  336. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  337. return 0;
  338. }
  339. return (data >> 8) | ((data & 0xff) << 8);
  340. }
  341. #else
  342. #define snd_soc_8_16_read_i2c NULL
  343. #endif
  344. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  345. static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
  346. unsigned int r)
  347. {
  348. struct i2c_msg xfer[2];
  349. u16 reg = r;
  350. u8 data;
  351. int ret;
  352. struct i2c_client *client = codec->control_data;
  353. /* Write register */
  354. xfer[0].addr = client->addr;
  355. xfer[0].flags = 0;
  356. xfer[0].len = 2;
  357. xfer[0].buf = (u8 *)&reg;
  358. /* Read data */
  359. xfer[1].addr = client->addr;
  360. xfer[1].flags = I2C_M_RD;
  361. xfer[1].len = 1;
  362. xfer[1].buf = &data;
  363. ret = i2c_transfer(client->adapter, xfer, 2);
  364. if (ret != 2) {
  365. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  366. return 0;
  367. }
  368. return data;
  369. }
  370. #else
  371. #define snd_soc_16_8_read_i2c NULL
  372. #endif
  373. static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
  374. unsigned int reg)
  375. {
  376. int ret;
  377. unsigned int val;
  378. reg &= 0xff;
  379. if (reg >= codec->driver->reg_cache_size ||
  380. snd_soc_codec_volatile_register(codec, reg) ||
  381. codec->cache_bypass) {
  382. if (codec->cache_only)
  383. return -1;
  384. BUG_ON(!codec->hw_read);
  385. return codec->hw_read(codec, reg);
  386. }
  387. ret = snd_soc_cache_read(codec, reg, &val);
  388. if (ret < 0)
  389. return -1;
  390. return val;
  391. }
  392. static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
  393. unsigned int value)
  394. {
  395. u8 data[3];
  396. int ret;
  397. data[0] = (reg >> 8) & 0xff;
  398. data[1] = reg & 0xff;
  399. data[2] = value;
  400. reg &= 0xff;
  401. if (!snd_soc_codec_volatile_register(codec, reg) &&
  402. reg < codec->driver->reg_cache_size &&
  403. !codec->cache_bypass) {
  404. ret = snd_soc_cache_write(codec, reg, value);
  405. if (ret < 0)
  406. return -1;
  407. }
  408. if (codec->cache_only) {
  409. codec->cache_sync = 1;
  410. return 0;
  411. }
  412. ret = codec->hw_write(codec->control_data, data, 3);
  413. if (ret == 3)
  414. return 0;
  415. if (ret < 0)
  416. return ret;
  417. else
  418. return -EIO;
  419. }
  420. #if defined(CONFIG_SPI_MASTER)
  421. static int snd_soc_16_8_spi_write(void *control_data, const char *data,
  422. int len)
  423. {
  424. struct spi_device *spi = control_data;
  425. struct spi_transfer t;
  426. struct spi_message m;
  427. u8 msg[3];
  428. if (len <= 0)
  429. return 0;
  430. msg[0] = data[0];
  431. msg[1] = data[1];
  432. msg[2] = data[2];
  433. spi_message_init(&m);
  434. memset(&t, 0, sizeof t);
  435. t.tx_buf = &msg[0];
  436. t.len = len;
  437. spi_message_add_tail(&t, &m);
  438. spi_sync(spi, &m);
  439. return len;
  440. }
  441. #else
  442. #define snd_soc_16_8_spi_write NULL
  443. #endif
  444. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  445. static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
  446. unsigned int r)
  447. {
  448. struct i2c_msg xfer[2];
  449. u16 reg = cpu_to_be16(r);
  450. u16 data;
  451. int ret;
  452. struct i2c_client *client = codec->control_data;
  453. /* Write register */
  454. xfer[0].addr = client->addr;
  455. xfer[0].flags = 0;
  456. xfer[0].len = 2;
  457. xfer[0].buf = (u8 *)&reg;
  458. /* Read data */
  459. xfer[1].addr = client->addr;
  460. xfer[1].flags = I2C_M_RD;
  461. xfer[1].len = 2;
  462. xfer[1].buf = (u8 *)&data;
  463. ret = i2c_transfer(client->adapter, xfer, 2);
  464. if (ret != 2) {
  465. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  466. return 0;
  467. }
  468. return be16_to_cpu(data);
  469. }
  470. #else
  471. #define snd_soc_16_16_read_i2c NULL
  472. #endif
  473. static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
  474. unsigned int reg)
  475. {
  476. int ret;
  477. unsigned int val;
  478. if (reg >= codec->driver->reg_cache_size ||
  479. snd_soc_codec_volatile_register(codec, reg) ||
  480. codec->cache_bypass) {
  481. if (codec->cache_only)
  482. return -1;
  483. BUG_ON(!codec->hw_read);
  484. return codec->hw_read(codec, reg);
  485. }
  486. ret = snd_soc_cache_read(codec, reg, &val);
  487. if (ret < 0)
  488. return -1;
  489. return val;
  490. }
  491. static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
  492. unsigned int value)
  493. {
  494. u8 data[4];
  495. int ret;
  496. data[0] = (reg >> 8) & 0xff;
  497. data[1] = reg & 0xff;
  498. data[2] = (value >> 8) & 0xff;
  499. data[3] = value & 0xff;
  500. if (!snd_soc_codec_volatile_register(codec, reg) &&
  501. reg < codec->driver->reg_cache_size &&
  502. !codec->cache_bypass) {
  503. ret = snd_soc_cache_write(codec, reg, value);
  504. if (ret < 0)
  505. return -1;
  506. }
  507. if (codec->cache_only) {
  508. codec->cache_sync = 1;
  509. return 0;
  510. }
  511. ret = codec->hw_write(codec->control_data, data, 4);
  512. if (ret == 4)
  513. return 0;
  514. if (ret < 0)
  515. return ret;
  516. else
  517. return -EIO;
  518. }
  519. #if defined(CONFIG_SPI_MASTER)
  520. static int snd_soc_16_16_spi_write(void *control_data, const char *data,
  521. int len)
  522. {
  523. struct spi_device *spi = control_data;
  524. struct spi_transfer t;
  525. struct spi_message m;
  526. u8 msg[4];
  527. if (len <= 0)
  528. return 0;
  529. msg[0] = data[0];
  530. msg[1] = data[1];
  531. msg[2] = data[2];
  532. msg[3] = data[3];
  533. spi_message_init(&m);
  534. memset(&t, 0, sizeof t);
  535. t.tx_buf = &msg[0];
  536. t.len = len;
  537. spi_message_add_tail(&t, &m);
  538. spi_sync(spi, &m);
  539. return len;
  540. }
  541. #else
  542. #define snd_soc_16_16_spi_write NULL
  543. #endif
  544. static struct {
  545. int addr_bits;
  546. int data_bits;
  547. int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
  548. int (*spi_write)(void *, const char *, int);
  549. unsigned int (*read)(struct snd_soc_codec *, unsigned int);
  550. unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
  551. } io_types[] = {
  552. {
  553. .addr_bits = 4, .data_bits = 12,
  554. .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
  555. .spi_write = snd_soc_4_12_spi_write,
  556. },
  557. {
  558. .addr_bits = 7, .data_bits = 9,
  559. .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
  560. .spi_write = snd_soc_7_9_spi_write,
  561. },
  562. {
  563. .addr_bits = 8, .data_bits = 8,
  564. .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
  565. .i2c_read = snd_soc_8_8_read_i2c,
  566. .spi_write = snd_soc_8_8_spi_write,
  567. },
  568. {
  569. .addr_bits = 8, .data_bits = 16,
  570. .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
  571. .i2c_read = snd_soc_8_16_read_i2c,
  572. .spi_write = snd_soc_8_16_spi_write,
  573. },
  574. {
  575. .addr_bits = 16, .data_bits = 8,
  576. .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
  577. .i2c_read = snd_soc_16_8_read_i2c,
  578. .spi_write = snd_soc_16_8_spi_write,
  579. },
  580. {
  581. .addr_bits = 16, .data_bits = 16,
  582. .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
  583. .i2c_read = snd_soc_16_16_read_i2c,
  584. .spi_write = snd_soc_16_16_spi_write,
  585. },
  586. };
  587. /**
  588. * snd_soc_codec_set_cache_io: Set up standard I/O functions.
  589. *
  590. * @codec: CODEC to configure.
  591. * @type: Type of cache.
  592. * @addr_bits: Number of bits of register address data.
  593. * @data_bits: Number of bits of data per register.
  594. * @control: Control bus used.
  595. *
  596. * Register formats are frequently shared between many I2C and SPI
  597. * devices. In order to promote code reuse the ASoC core provides
  598. * some standard implementations of CODEC read and write operations
  599. * which can be set up using this function.
  600. *
  601. * The caller is responsible for allocating and initialising the
  602. * actual cache.
  603. *
  604. * Note that at present this code cannot be used by CODECs with
  605. * volatile registers.
  606. */
  607. int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
  608. int addr_bits, int data_bits,
  609. enum snd_soc_control_type control)
  610. {
  611. int i;
  612. for (i = 0; i < ARRAY_SIZE(io_types); i++)
  613. if (io_types[i].addr_bits == addr_bits &&
  614. io_types[i].data_bits == data_bits)
  615. break;
  616. if (i == ARRAY_SIZE(io_types)) {
  617. printk(KERN_ERR
  618. "No I/O functions for %d bit address %d bit data\n",
  619. addr_bits, data_bits);
  620. return -EINVAL;
  621. }
  622. codec->write = io_types[i].write;
  623. codec->read = io_types[i].read;
  624. switch (control) {
  625. case SND_SOC_CUSTOM:
  626. break;
  627. case SND_SOC_I2C:
  628. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  629. codec->hw_write = (hw_write_t)i2c_master_send;
  630. #endif
  631. if (io_types[i].i2c_read)
  632. codec->hw_read = io_types[i].i2c_read;
  633. codec->control_data = container_of(codec->dev,
  634. struct i2c_client,
  635. dev);
  636. break;
  637. case SND_SOC_SPI:
  638. if (io_types[i].spi_write)
  639. codec->hw_write = io_types[i].spi_write;
  640. codec->control_data = container_of(codec->dev,
  641. struct spi_device,
  642. dev);
  643. break;
  644. }
  645. return 0;
  646. }
  647. EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
  648. static bool snd_soc_set_cache_val(void *base, unsigned int idx,
  649. unsigned int val, unsigned int word_size)
  650. {
  651. switch (word_size) {
  652. case 1: {
  653. u8 *cache = base;
  654. if (cache[idx] == val)
  655. return true;
  656. cache[idx] = val;
  657. break;
  658. }
  659. case 2: {
  660. u16 *cache = base;
  661. if (cache[idx] == val)
  662. return true;
  663. cache[idx] = val;
  664. break;
  665. }
  666. default:
  667. BUG();
  668. }
  669. return false;
  670. }
  671. static unsigned int snd_soc_get_cache_val(const void *base, unsigned int idx,
  672. unsigned int word_size)
  673. {
  674. switch (word_size) {
  675. case 1: {
  676. const u8 *cache = base;
  677. return cache[idx];
  678. }
  679. case 2: {
  680. const u16 *cache = base;
  681. return cache[idx];
  682. }
  683. default:
  684. BUG();
  685. }
  686. /* unreachable */
  687. return -1;
  688. }
  689. struct snd_soc_rbtree_node {
  690. struct rb_node node;
  691. unsigned int reg;
  692. unsigned int value;
  693. unsigned int defval;
  694. } __attribute__ ((packed));
  695. struct snd_soc_rbtree_ctx {
  696. struct rb_root root;
  697. };
  698. static struct snd_soc_rbtree_node *snd_soc_rbtree_lookup(
  699. struct rb_root *root, unsigned int reg)
  700. {
  701. struct rb_node *node;
  702. struct snd_soc_rbtree_node *rbnode;
  703. node = root->rb_node;
  704. while (node) {
  705. rbnode = container_of(node, struct snd_soc_rbtree_node, node);
  706. if (rbnode->reg < reg)
  707. node = node->rb_left;
  708. else if (rbnode->reg > reg)
  709. node = node->rb_right;
  710. else
  711. return rbnode;
  712. }
  713. return NULL;
  714. }
  715. static int snd_soc_rbtree_insert(struct rb_root *root,
  716. struct snd_soc_rbtree_node *rbnode)
  717. {
  718. struct rb_node **new, *parent;
  719. struct snd_soc_rbtree_node *rbnode_tmp;
  720. parent = NULL;
  721. new = &root->rb_node;
  722. while (*new) {
  723. rbnode_tmp = container_of(*new, struct snd_soc_rbtree_node,
  724. node);
  725. parent = *new;
  726. if (rbnode_tmp->reg < rbnode->reg)
  727. new = &((*new)->rb_left);
  728. else if (rbnode_tmp->reg > rbnode->reg)
  729. new = &((*new)->rb_right);
  730. else
  731. return 0;
  732. }
  733. /* insert the node into the rbtree */
  734. rb_link_node(&rbnode->node, parent, new);
  735. rb_insert_color(&rbnode->node, root);
  736. return 1;
  737. }
  738. static int snd_soc_rbtree_cache_sync(struct snd_soc_codec *codec)
  739. {
  740. struct snd_soc_rbtree_ctx *rbtree_ctx;
  741. struct rb_node *node;
  742. struct snd_soc_rbtree_node *rbnode;
  743. unsigned int val;
  744. int ret;
  745. rbtree_ctx = codec->reg_cache;
  746. for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
  747. rbnode = rb_entry(node, struct snd_soc_rbtree_node, node);
  748. if (rbnode->value == rbnode->defval)
  749. continue;
  750. ret = snd_soc_cache_read(codec, rbnode->reg, &val);
  751. if (ret)
  752. return ret;
  753. codec->cache_bypass = 1;
  754. ret = snd_soc_write(codec, rbnode->reg, val);
  755. codec->cache_bypass = 0;
  756. if (ret)
  757. return ret;
  758. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  759. rbnode->reg, val);
  760. }
  761. return 0;
  762. }
  763. static int snd_soc_rbtree_cache_write(struct snd_soc_codec *codec,
  764. unsigned int reg, unsigned int value)
  765. {
  766. struct snd_soc_rbtree_ctx *rbtree_ctx;
  767. struct snd_soc_rbtree_node *rbnode;
  768. rbtree_ctx = codec->reg_cache;
  769. rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
  770. if (rbnode) {
  771. if (rbnode->value == value)
  772. return 0;
  773. rbnode->value = value;
  774. } else {
  775. /* bail out early, no need to create the rbnode yet */
  776. if (!value)
  777. return 0;
  778. /*
  779. * for uninitialized registers whose value is changed
  780. * from the default zero, create an rbnode and insert
  781. * it into the tree.
  782. */
  783. rbnode = kzalloc(sizeof *rbnode, GFP_KERNEL);
  784. if (!rbnode)
  785. return -ENOMEM;
  786. rbnode->reg = reg;
  787. rbnode->value = value;
  788. snd_soc_rbtree_insert(&rbtree_ctx->root, rbnode);
  789. }
  790. return 0;
  791. }
  792. static int snd_soc_rbtree_cache_read(struct snd_soc_codec *codec,
  793. unsigned int reg, unsigned int *value)
  794. {
  795. struct snd_soc_rbtree_ctx *rbtree_ctx;
  796. struct snd_soc_rbtree_node *rbnode;
  797. rbtree_ctx = codec->reg_cache;
  798. rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
  799. if (rbnode) {
  800. *value = rbnode->value;
  801. } else {
  802. /* uninitialized registers default to 0 */
  803. *value = 0;
  804. }
  805. return 0;
  806. }
  807. static int snd_soc_rbtree_cache_exit(struct snd_soc_codec *codec)
  808. {
  809. struct rb_node *next;
  810. struct snd_soc_rbtree_ctx *rbtree_ctx;
  811. struct snd_soc_rbtree_node *rbtree_node;
  812. /* if we've already been called then just return */
  813. rbtree_ctx = codec->reg_cache;
  814. if (!rbtree_ctx)
  815. return 0;
  816. /* free up the rbtree */
  817. next = rb_first(&rbtree_ctx->root);
  818. while (next) {
  819. rbtree_node = rb_entry(next, struct snd_soc_rbtree_node, node);
  820. next = rb_next(&rbtree_node->node);
  821. rb_erase(&rbtree_node->node, &rbtree_ctx->root);
  822. kfree(rbtree_node);
  823. }
  824. /* release the resources */
  825. kfree(codec->reg_cache);
  826. codec->reg_cache = NULL;
  827. return 0;
  828. }
  829. static int snd_soc_rbtree_cache_init(struct snd_soc_codec *codec)
  830. {
  831. struct snd_soc_rbtree_node *rbtree_node;
  832. struct snd_soc_rbtree_ctx *rbtree_ctx;
  833. unsigned int val;
  834. unsigned int word_size;
  835. int i;
  836. int ret;
  837. codec->reg_cache = kmalloc(sizeof *rbtree_ctx, GFP_KERNEL);
  838. if (!codec->reg_cache)
  839. return -ENOMEM;
  840. rbtree_ctx = codec->reg_cache;
  841. rbtree_ctx->root = RB_ROOT;
  842. if (!codec->reg_def_copy)
  843. return 0;
  844. /*
  845. * populate the rbtree with the initialized registers. All other
  846. * registers will be inserted when they are first modified.
  847. */
  848. word_size = codec->driver->reg_word_size;
  849. for (i = 0; i < codec->driver->reg_cache_size; ++i) {
  850. val = snd_soc_get_cache_val(codec->reg_def_copy, i, word_size);
  851. if (!val)
  852. continue;
  853. rbtree_node = kzalloc(sizeof *rbtree_node, GFP_KERNEL);
  854. if (!rbtree_node) {
  855. ret = -ENOMEM;
  856. snd_soc_cache_exit(codec);
  857. break;
  858. }
  859. rbtree_node->reg = i;
  860. rbtree_node->value = val;
  861. rbtree_node->defval = val;
  862. snd_soc_rbtree_insert(&rbtree_ctx->root, rbtree_node);
  863. }
  864. return 0;
  865. }
  866. #ifdef CONFIG_SND_SOC_CACHE_LZO
  867. struct snd_soc_lzo_ctx {
  868. void *wmem;
  869. void *dst;
  870. const void *src;
  871. size_t src_len;
  872. size_t dst_len;
  873. size_t decompressed_size;
  874. unsigned long *sync_bmp;
  875. int sync_bmp_nbits;
  876. };
  877. #define LZO_BLOCK_NUM 8
  878. static int snd_soc_lzo_block_count(void)
  879. {
  880. return LZO_BLOCK_NUM;
  881. }
  882. static int snd_soc_lzo_prepare(struct snd_soc_lzo_ctx *lzo_ctx)
  883. {
  884. lzo_ctx->wmem = kmalloc(LZO1X_MEM_COMPRESS, GFP_KERNEL);
  885. if (!lzo_ctx->wmem)
  886. return -ENOMEM;
  887. return 0;
  888. }
  889. static int snd_soc_lzo_compress(struct snd_soc_lzo_ctx *lzo_ctx)
  890. {
  891. size_t compress_size;
  892. int ret;
  893. ret = lzo1x_1_compress(lzo_ctx->src, lzo_ctx->src_len,
  894. lzo_ctx->dst, &compress_size, lzo_ctx->wmem);
  895. if (ret != LZO_E_OK || compress_size > lzo_ctx->dst_len)
  896. return -EINVAL;
  897. lzo_ctx->dst_len = compress_size;
  898. return 0;
  899. }
  900. static int snd_soc_lzo_decompress(struct snd_soc_lzo_ctx *lzo_ctx)
  901. {
  902. size_t dst_len;
  903. int ret;
  904. dst_len = lzo_ctx->dst_len;
  905. ret = lzo1x_decompress_safe(lzo_ctx->src, lzo_ctx->src_len,
  906. lzo_ctx->dst, &dst_len);
  907. if (ret != LZO_E_OK || dst_len != lzo_ctx->dst_len)
  908. return -EINVAL;
  909. return 0;
  910. }
  911. static int snd_soc_lzo_compress_cache_block(struct snd_soc_codec *codec,
  912. struct snd_soc_lzo_ctx *lzo_ctx)
  913. {
  914. int ret;
  915. lzo_ctx->dst_len = lzo1x_worst_compress(PAGE_SIZE);
  916. lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
  917. if (!lzo_ctx->dst) {
  918. lzo_ctx->dst_len = 0;
  919. return -ENOMEM;
  920. }
  921. ret = snd_soc_lzo_compress(lzo_ctx);
  922. if (ret < 0)
  923. return ret;
  924. return 0;
  925. }
  926. static int snd_soc_lzo_decompress_cache_block(struct snd_soc_codec *codec,
  927. struct snd_soc_lzo_ctx *lzo_ctx)
  928. {
  929. int ret;
  930. lzo_ctx->dst_len = lzo_ctx->decompressed_size;
  931. lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
  932. if (!lzo_ctx->dst) {
  933. lzo_ctx->dst_len = 0;
  934. return -ENOMEM;
  935. }
  936. ret = snd_soc_lzo_decompress(lzo_ctx);
  937. if (ret < 0)
  938. return ret;
  939. return 0;
  940. }
  941. static inline int snd_soc_lzo_get_blkindex(struct snd_soc_codec *codec,
  942. unsigned int reg)
  943. {
  944. const struct snd_soc_codec_driver *codec_drv;
  945. codec_drv = codec->driver;
  946. return (reg * codec_drv->reg_word_size) /
  947. DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count());
  948. }
  949. static inline int snd_soc_lzo_get_blkpos(struct snd_soc_codec *codec,
  950. unsigned int reg)
  951. {
  952. const struct snd_soc_codec_driver *codec_drv;
  953. codec_drv = codec->driver;
  954. return reg % (DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count()) /
  955. codec_drv->reg_word_size);
  956. }
  957. static inline int snd_soc_lzo_get_blksize(struct snd_soc_codec *codec)
  958. {
  959. const struct snd_soc_codec_driver *codec_drv;
  960. codec_drv = codec->driver;
  961. return DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count());
  962. }
  963. static int snd_soc_lzo_cache_sync(struct snd_soc_codec *codec)
  964. {
  965. struct snd_soc_lzo_ctx **lzo_blocks;
  966. unsigned int val;
  967. int i;
  968. int ret;
  969. lzo_blocks = codec->reg_cache;
  970. for_each_set_bit(i, lzo_blocks[0]->sync_bmp, lzo_blocks[0]->sync_bmp_nbits) {
  971. ret = snd_soc_cache_read(codec, i, &val);
  972. if (ret)
  973. return ret;
  974. codec->cache_bypass = 1;
  975. ret = snd_soc_write(codec, i, val);
  976. codec->cache_bypass = 0;
  977. if (ret)
  978. return ret;
  979. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  980. i, val);
  981. }
  982. return 0;
  983. }
  984. static int snd_soc_lzo_cache_write(struct snd_soc_codec *codec,
  985. unsigned int reg, unsigned int value)
  986. {
  987. struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
  988. int ret, blkindex, blkpos;
  989. size_t blksize, tmp_dst_len;
  990. void *tmp_dst;
  991. /* index of the compressed lzo block */
  992. blkindex = snd_soc_lzo_get_blkindex(codec, reg);
  993. /* register index within the decompressed block */
  994. blkpos = snd_soc_lzo_get_blkpos(codec, reg);
  995. /* size of the compressed block */
  996. blksize = snd_soc_lzo_get_blksize(codec);
  997. lzo_blocks = codec->reg_cache;
  998. lzo_block = lzo_blocks[blkindex];
  999. /* save the pointer and length of the compressed block */
  1000. tmp_dst = lzo_block->dst;
  1001. tmp_dst_len = lzo_block->dst_len;
  1002. /* prepare the source to be the compressed block */
  1003. lzo_block->src = lzo_block->dst;
  1004. lzo_block->src_len = lzo_block->dst_len;
  1005. /* decompress the block */
  1006. ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
  1007. if (ret < 0) {
  1008. kfree(lzo_block->dst);
  1009. goto out;
  1010. }
  1011. /* write the new value to the cache */
  1012. if (snd_soc_set_cache_val(lzo_block->dst, blkpos, value,
  1013. codec->driver->reg_word_size)) {
  1014. kfree(lzo_block->dst);
  1015. goto out;
  1016. }
  1017. /* prepare the source to be the decompressed block */
  1018. lzo_block->src = lzo_block->dst;
  1019. lzo_block->src_len = lzo_block->dst_len;
  1020. /* compress the block */
  1021. ret = snd_soc_lzo_compress_cache_block(codec, lzo_block);
  1022. if (ret < 0) {
  1023. kfree(lzo_block->dst);
  1024. kfree(lzo_block->src);
  1025. goto out;
  1026. }
  1027. /* set the bit so we know we have to sync this register */
  1028. set_bit(reg, lzo_block->sync_bmp);
  1029. kfree(tmp_dst);
  1030. kfree(lzo_block->src);
  1031. return 0;
  1032. out:
  1033. lzo_block->dst = tmp_dst;
  1034. lzo_block->dst_len = tmp_dst_len;
  1035. return ret;
  1036. }
  1037. static int snd_soc_lzo_cache_read(struct snd_soc_codec *codec,
  1038. unsigned int reg, unsigned int *value)
  1039. {
  1040. struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
  1041. int ret, blkindex, blkpos;
  1042. size_t blksize, tmp_dst_len;
  1043. void *tmp_dst;
  1044. *value = 0;
  1045. /* index of the compressed lzo block */
  1046. blkindex = snd_soc_lzo_get_blkindex(codec, reg);
  1047. /* register index within the decompressed block */
  1048. blkpos = snd_soc_lzo_get_blkpos(codec, reg);
  1049. /* size of the compressed block */
  1050. blksize = snd_soc_lzo_get_blksize(codec);
  1051. lzo_blocks = codec->reg_cache;
  1052. lzo_block = lzo_blocks[blkindex];
  1053. /* save the pointer and length of the compressed block */
  1054. tmp_dst = lzo_block->dst;
  1055. tmp_dst_len = lzo_block->dst_len;
  1056. /* prepare the source to be the compressed block */
  1057. lzo_block->src = lzo_block->dst;
  1058. lzo_block->src_len = lzo_block->dst_len;
  1059. /* decompress the block */
  1060. ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
  1061. if (ret >= 0)
  1062. /* fetch the value from the cache */
  1063. *value = snd_soc_get_cache_val(lzo_block->dst, blkpos,
  1064. codec->driver->reg_word_size);
  1065. kfree(lzo_block->dst);
  1066. /* restore the pointer and length of the compressed block */
  1067. lzo_block->dst = tmp_dst;
  1068. lzo_block->dst_len = tmp_dst_len;
  1069. return 0;
  1070. }
  1071. static int snd_soc_lzo_cache_exit(struct snd_soc_codec *codec)
  1072. {
  1073. struct snd_soc_lzo_ctx **lzo_blocks;
  1074. int i, blkcount;
  1075. lzo_blocks = codec->reg_cache;
  1076. if (!lzo_blocks)
  1077. return 0;
  1078. blkcount = snd_soc_lzo_block_count();
  1079. /*
  1080. * the pointer to the bitmap used for syncing the cache
  1081. * is shared amongst all lzo_blocks. Ensure it is freed
  1082. * only once.
  1083. */
  1084. if (lzo_blocks[0])
  1085. kfree(lzo_blocks[0]->sync_bmp);
  1086. for (i = 0; i < blkcount; ++i) {
  1087. if (lzo_blocks[i]) {
  1088. kfree(lzo_blocks[i]->wmem);
  1089. kfree(lzo_blocks[i]->dst);
  1090. }
  1091. /* each lzo_block is a pointer returned by kmalloc or NULL */
  1092. kfree(lzo_blocks[i]);
  1093. }
  1094. kfree(lzo_blocks);
  1095. codec->reg_cache = NULL;
  1096. return 0;
  1097. }
  1098. static int snd_soc_lzo_cache_init(struct snd_soc_codec *codec)
  1099. {
  1100. struct snd_soc_lzo_ctx **lzo_blocks;
  1101. size_t bmp_size;
  1102. const struct snd_soc_codec_driver *codec_drv;
  1103. int ret, tofree, i, blksize, blkcount;
  1104. const char *p, *end;
  1105. unsigned long *sync_bmp;
  1106. ret = 0;
  1107. codec_drv = codec->driver;
  1108. /*
  1109. * If we have not been given a default register cache
  1110. * then allocate a dummy zero-ed out region, compress it
  1111. * and remember to free it afterwards.
  1112. */
  1113. tofree = 0;
  1114. if (!codec->reg_def_copy)
  1115. tofree = 1;
  1116. if (!codec->reg_def_copy) {
  1117. codec->reg_def_copy = kzalloc(codec->reg_size, GFP_KERNEL);
  1118. if (!codec->reg_def_copy)
  1119. return -ENOMEM;
  1120. }
  1121. blkcount = snd_soc_lzo_block_count();
  1122. codec->reg_cache = kzalloc(blkcount * sizeof *lzo_blocks,
  1123. GFP_KERNEL);
  1124. if (!codec->reg_cache) {
  1125. ret = -ENOMEM;
  1126. goto err_tofree;
  1127. }
  1128. lzo_blocks = codec->reg_cache;
  1129. /*
  1130. * allocate a bitmap to be used when syncing the cache with
  1131. * the hardware. Each time a register is modified, the corresponding
  1132. * bit is set in the bitmap, so we know that we have to sync
  1133. * that register.
  1134. */
  1135. bmp_size = codec_drv->reg_cache_size;
  1136. sync_bmp = kmalloc(BITS_TO_LONGS(bmp_size) * sizeof(long),
  1137. GFP_KERNEL);
  1138. if (!sync_bmp) {
  1139. ret = -ENOMEM;
  1140. goto err;
  1141. }
  1142. bitmap_zero(sync_bmp, bmp_size);
  1143. /* allocate the lzo blocks and initialize them */
  1144. for (i = 0; i < blkcount; ++i) {
  1145. lzo_blocks[i] = kzalloc(sizeof **lzo_blocks,
  1146. GFP_KERNEL);
  1147. if (!lzo_blocks[i]) {
  1148. kfree(sync_bmp);
  1149. ret = -ENOMEM;
  1150. goto err;
  1151. }
  1152. lzo_blocks[i]->sync_bmp = sync_bmp;
  1153. lzo_blocks[i]->sync_bmp_nbits = bmp_size;
  1154. /* alloc the working space for the compressed block */
  1155. ret = snd_soc_lzo_prepare(lzo_blocks[i]);
  1156. if (ret < 0)
  1157. goto err;
  1158. }
  1159. blksize = snd_soc_lzo_get_blksize(codec);
  1160. p = codec->reg_def_copy;
  1161. end = codec->reg_def_copy + codec->reg_size;
  1162. /* compress the register map and fill the lzo blocks */
  1163. for (i = 0; i < blkcount; ++i, p += blksize) {
  1164. lzo_blocks[i]->src = p;
  1165. if (p + blksize > end)
  1166. lzo_blocks[i]->src_len = end - p;
  1167. else
  1168. lzo_blocks[i]->src_len = blksize;
  1169. ret = snd_soc_lzo_compress_cache_block(codec,
  1170. lzo_blocks[i]);
  1171. if (ret < 0)
  1172. goto err;
  1173. lzo_blocks[i]->decompressed_size =
  1174. lzo_blocks[i]->src_len;
  1175. }
  1176. if (tofree) {
  1177. kfree(codec->reg_def_copy);
  1178. codec->reg_def_copy = NULL;
  1179. }
  1180. return 0;
  1181. err:
  1182. snd_soc_cache_exit(codec);
  1183. err_tofree:
  1184. if (tofree) {
  1185. kfree(codec->reg_def_copy);
  1186. codec->reg_def_copy = NULL;
  1187. }
  1188. return ret;
  1189. }
  1190. #endif
  1191. static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec)
  1192. {
  1193. int i;
  1194. int ret;
  1195. const struct snd_soc_codec_driver *codec_drv;
  1196. unsigned int val;
  1197. codec_drv = codec->driver;
  1198. for (i = 0; i < codec_drv->reg_cache_size; ++i) {
  1199. ret = snd_soc_cache_read(codec, i, &val);
  1200. if (ret)
  1201. return ret;
  1202. if (codec->reg_def_copy)
  1203. if (snd_soc_get_cache_val(codec->reg_def_copy,
  1204. i, codec_drv->reg_word_size) == val)
  1205. continue;
  1206. ret = snd_soc_write(codec, i, val);
  1207. if (ret)
  1208. return ret;
  1209. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  1210. i, val);
  1211. }
  1212. return 0;
  1213. }
  1214. static int snd_soc_flat_cache_write(struct snd_soc_codec *codec,
  1215. unsigned int reg, unsigned int value)
  1216. {
  1217. snd_soc_set_cache_val(codec->reg_cache, reg, value,
  1218. codec->driver->reg_word_size);
  1219. return 0;
  1220. }
  1221. static int snd_soc_flat_cache_read(struct snd_soc_codec *codec,
  1222. unsigned int reg, unsigned int *value)
  1223. {
  1224. *value = snd_soc_get_cache_val(codec->reg_cache, reg,
  1225. codec->driver->reg_word_size);
  1226. return 0;
  1227. }
  1228. static int snd_soc_flat_cache_exit(struct snd_soc_codec *codec)
  1229. {
  1230. if (!codec->reg_cache)
  1231. return 0;
  1232. kfree(codec->reg_cache);
  1233. codec->reg_cache = NULL;
  1234. return 0;
  1235. }
  1236. static int snd_soc_flat_cache_init(struct snd_soc_codec *codec)
  1237. {
  1238. const struct snd_soc_codec_driver *codec_drv;
  1239. codec_drv = codec->driver;
  1240. if (codec->reg_def_copy)
  1241. codec->reg_cache = kmemdup(codec->reg_def_copy,
  1242. codec->reg_size, GFP_KERNEL);
  1243. else
  1244. codec->reg_cache = kzalloc(codec->reg_size, GFP_KERNEL);
  1245. if (!codec->reg_cache)
  1246. return -ENOMEM;
  1247. return 0;
  1248. }
  1249. /* an array of all supported compression types */
  1250. static const struct snd_soc_cache_ops cache_types[] = {
  1251. /* Flat *must* be the first entry for fallback */
  1252. {
  1253. .id = SND_SOC_FLAT_COMPRESSION,
  1254. .name = "flat",
  1255. .init = snd_soc_flat_cache_init,
  1256. .exit = snd_soc_flat_cache_exit,
  1257. .read = snd_soc_flat_cache_read,
  1258. .write = snd_soc_flat_cache_write,
  1259. .sync = snd_soc_flat_cache_sync
  1260. },
  1261. #ifdef CONFIG_SND_SOC_CACHE_LZO
  1262. {
  1263. .id = SND_SOC_LZO_COMPRESSION,
  1264. .name = "LZO",
  1265. .init = snd_soc_lzo_cache_init,
  1266. .exit = snd_soc_lzo_cache_exit,
  1267. .read = snd_soc_lzo_cache_read,
  1268. .write = snd_soc_lzo_cache_write,
  1269. .sync = snd_soc_lzo_cache_sync
  1270. },
  1271. #endif
  1272. {
  1273. .id = SND_SOC_RBTREE_COMPRESSION,
  1274. .name = "rbtree",
  1275. .init = snd_soc_rbtree_cache_init,
  1276. .exit = snd_soc_rbtree_cache_exit,
  1277. .read = snd_soc_rbtree_cache_read,
  1278. .write = snd_soc_rbtree_cache_write,
  1279. .sync = snd_soc_rbtree_cache_sync
  1280. }
  1281. };
  1282. int snd_soc_cache_init(struct snd_soc_codec *codec)
  1283. {
  1284. int i;
  1285. for (i = 0; i < ARRAY_SIZE(cache_types); ++i)
  1286. if (cache_types[i].id == codec->compress_type)
  1287. break;
  1288. /* Fall back to flat compression */
  1289. if (i == ARRAY_SIZE(cache_types)) {
  1290. dev_warn(codec->dev, "Could not match compress type: %d\n",
  1291. codec->compress_type);
  1292. i = 0;
  1293. }
  1294. mutex_init(&codec->cache_rw_mutex);
  1295. codec->cache_ops = &cache_types[i];
  1296. if (codec->cache_ops->init) {
  1297. if (codec->cache_ops->name)
  1298. dev_dbg(codec->dev, "Initializing %s cache for %s codec\n",
  1299. codec->cache_ops->name, codec->name);
  1300. return codec->cache_ops->init(codec);
  1301. }
  1302. return -EINVAL;
  1303. }
  1304. /*
  1305. * NOTE: keep in mind that this function might be called
  1306. * multiple times.
  1307. */
  1308. int snd_soc_cache_exit(struct snd_soc_codec *codec)
  1309. {
  1310. if (codec->cache_ops && codec->cache_ops->exit) {
  1311. if (codec->cache_ops->name)
  1312. dev_dbg(codec->dev, "Destroying %s cache for %s codec\n",
  1313. codec->cache_ops->name, codec->name);
  1314. return codec->cache_ops->exit(codec);
  1315. }
  1316. return -EINVAL;
  1317. }
  1318. /**
  1319. * snd_soc_cache_read: Fetch the value of a given register from the cache.
  1320. *
  1321. * @codec: CODEC to configure.
  1322. * @reg: The register index.
  1323. * @value: The value to be returned.
  1324. */
  1325. int snd_soc_cache_read(struct snd_soc_codec *codec,
  1326. unsigned int reg, unsigned int *value)
  1327. {
  1328. int ret;
  1329. mutex_lock(&codec->cache_rw_mutex);
  1330. if (value && codec->cache_ops && codec->cache_ops->read) {
  1331. ret = codec->cache_ops->read(codec, reg, value);
  1332. mutex_unlock(&codec->cache_rw_mutex);
  1333. return ret;
  1334. }
  1335. mutex_unlock(&codec->cache_rw_mutex);
  1336. return -EINVAL;
  1337. }
  1338. EXPORT_SYMBOL_GPL(snd_soc_cache_read);
  1339. /**
  1340. * snd_soc_cache_write: Set the value of a given register in the cache.
  1341. *
  1342. * @codec: CODEC to configure.
  1343. * @reg: The register index.
  1344. * @value: The new register value.
  1345. */
  1346. int snd_soc_cache_write(struct snd_soc_codec *codec,
  1347. unsigned int reg, unsigned int value)
  1348. {
  1349. int ret;
  1350. mutex_lock(&codec->cache_rw_mutex);
  1351. if (codec->cache_ops && codec->cache_ops->write) {
  1352. ret = codec->cache_ops->write(codec, reg, value);
  1353. mutex_unlock(&codec->cache_rw_mutex);
  1354. return ret;
  1355. }
  1356. mutex_unlock(&codec->cache_rw_mutex);
  1357. return -EINVAL;
  1358. }
  1359. EXPORT_SYMBOL_GPL(snd_soc_cache_write);
  1360. /**
  1361. * snd_soc_cache_sync: Sync the register cache with the hardware.
  1362. *
  1363. * @codec: CODEC to configure.
  1364. *
  1365. * Any registers that should not be synced should be marked as
  1366. * volatile. In general drivers can choose not to use the provided
  1367. * syncing functionality if they so require.
  1368. */
  1369. int snd_soc_cache_sync(struct snd_soc_codec *codec)
  1370. {
  1371. int ret;
  1372. const char *name;
  1373. if (!codec->cache_sync) {
  1374. return 0;
  1375. }
  1376. if (!codec->cache_ops || !codec->cache_ops->sync)
  1377. return -EINVAL;
  1378. if (codec->cache_ops->name)
  1379. name = codec->cache_ops->name;
  1380. else
  1381. name = "unknown";
  1382. if (codec->cache_ops->name)
  1383. dev_dbg(codec->dev, "Syncing %s cache for %s codec\n",
  1384. codec->cache_ops->name, codec->name);
  1385. trace_snd_soc_cache_sync(codec, name, "start");
  1386. ret = codec->cache_ops->sync(codec);
  1387. if (!ret)
  1388. codec->cache_sync = 0;
  1389. trace_snd_soc_cache_sync(codec, name, "end");
  1390. return ret;
  1391. }
  1392. EXPORT_SYMBOL_GPL(snd_soc_cache_sync);
  1393. static int snd_soc_get_reg_access_index(struct snd_soc_codec *codec,
  1394. unsigned int reg)
  1395. {
  1396. const struct snd_soc_codec_driver *codec_drv;
  1397. unsigned int min, max, index;
  1398. codec_drv = codec->driver;
  1399. min = 0;
  1400. max = codec_drv->reg_access_size - 1;
  1401. do {
  1402. index = (min + max) / 2;
  1403. if (codec_drv->reg_access_default[index].reg == reg)
  1404. return index;
  1405. if (codec_drv->reg_access_default[index].reg < reg)
  1406. min = index + 1;
  1407. else
  1408. max = index;
  1409. } while (min <= max);
  1410. return -1;
  1411. }
  1412. int snd_soc_default_volatile_register(struct snd_soc_codec *codec,
  1413. unsigned int reg)
  1414. {
  1415. int index;
  1416. if (reg >= codec->driver->reg_cache_size)
  1417. return 1;
  1418. index = snd_soc_get_reg_access_index(codec, reg);
  1419. if (index < 0)
  1420. return 0;
  1421. return codec->driver->reg_access_default[index].vol;
  1422. }
  1423. EXPORT_SYMBOL_GPL(snd_soc_default_volatile_register);
  1424. int snd_soc_default_readable_register(struct snd_soc_codec *codec,
  1425. unsigned int reg)
  1426. {
  1427. int index;
  1428. if (reg >= codec->driver->reg_cache_size)
  1429. return 1;
  1430. index = snd_soc_get_reg_access_index(codec, reg);
  1431. if (index < 0)
  1432. return 0;
  1433. return codec->driver->reg_access_default[index].read;
  1434. }
  1435. EXPORT_SYMBOL_GPL(snd_soc_default_readable_register);