au1550_ac97.c 51 KB

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  1. /*
  2. * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
  3. * Processor.
  4. *
  5. * Copyright 2004 Embedded Edge, LLC
  6. * dan@embeddededge.com
  7. *
  8. * Mostly copied from the au1000.c driver and some from the
  9. * PowerMac dbdma driver.
  10. * We assume the processor can do memory coherent DMA.
  11. *
  12. * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License as published by the
  16. * Free Software Foundation; either version 2 of the License, or (at your
  17. * option) any later version.
  18. *
  19. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  20. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  21. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  22. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  25. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. *
  30. * You should have received a copy of the GNU General Public License along
  31. * with this program; if not, write to the Free Software Foundation, Inc.,
  32. * 675 Mass Ave, Cambridge, MA 02139, USA.
  33. *
  34. */
  35. #undef DEBUG
  36. #include <linux/module.h>
  37. #include <linux/string.h>
  38. #include <linux/ioport.h>
  39. #include <linux/sched.h>
  40. #include <linux/delay.h>
  41. #include <linux/sound.h>
  42. #include <linux/slab.h>
  43. #include <linux/soundcard.h>
  44. #include <linux/init.h>
  45. #include <linux/interrupt.h>
  46. #include <linux/kernel.h>
  47. #include <linux/poll.h>
  48. #include <linux/bitops.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/ac97_codec.h>
  51. #include <linux/mutex.h>
  52. #include <asm/io.h>
  53. #include <asm/uaccess.h>
  54. #include <asm/hardirq.h>
  55. #include <asm/mach-au1x00/au1xxx_psc.h>
  56. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  57. #include <asm/mach-au1x00/au1xxx.h>
  58. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  59. /* misc stuff */
  60. #define POLL_COUNT 0x50000
  61. #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
  62. /* The number of DBDMA ring descriptors to allocate. No sense making
  63. * this too large....if you can't keep up with a few you aren't likely
  64. * to be able to with lots of them, either.
  65. */
  66. #define NUM_DBDMA_DESCRIPTORS 4
  67. #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
  68. /* Boot options
  69. * 0 = no VRA, 1 = use VRA if codec supports it
  70. */
  71. static DEFINE_MUTEX(au1550_ac97_mutex);
  72. static int vra = 1;
  73. module_param(vra, bool, 0);
  74. MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
  75. static struct au1550_state {
  76. /* soundcore stuff */
  77. int dev_audio;
  78. struct ac97_codec *codec;
  79. unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
  80. unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
  81. int no_vra; /* do not use VRA */
  82. spinlock_t lock;
  83. struct mutex open_mutex;
  84. struct mutex sem;
  85. fmode_t open_mode;
  86. wait_queue_head_t open_wait;
  87. struct dmabuf {
  88. u32 dmanr;
  89. unsigned sample_rate;
  90. unsigned src_factor;
  91. unsigned sample_size;
  92. int num_channels;
  93. int dma_bytes_per_sample;
  94. int user_bytes_per_sample;
  95. int cnt_factor;
  96. void *rawbuf;
  97. unsigned buforder;
  98. unsigned numfrag;
  99. unsigned fragshift;
  100. void *nextIn;
  101. void *nextOut;
  102. int count;
  103. unsigned total_bytes;
  104. unsigned error;
  105. wait_queue_head_t wait;
  106. /* redundant, but makes calculations easier */
  107. unsigned fragsize;
  108. unsigned dma_fragsize;
  109. unsigned dmasize;
  110. unsigned dma_qcount;
  111. /* OSS stuff */
  112. unsigned mapped:1;
  113. unsigned ready:1;
  114. unsigned stopped:1;
  115. unsigned ossfragshift;
  116. int ossmaxfrags;
  117. unsigned subdivision;
  118. } dma_dac, dma_adc;
  119. } au1550_state;
  120. static unsigned
  121. ld2(unsigned int x)
  122. {
  123. unsigned r = 0;
  124. if (x >= 0x10000) {
  125. x >>= 16;
  126. r += 16;
  127. }
  128. if (x >= 0x100) {
  129. x >>= 8;
  130. r += 8;
  131. }
  132. if (x >= 0x10) {
  133. x >>= 4;
  134. r += 4;
  135. }
  136. if (x >= 4) {
  137. x >>= 2;
  138. r += 2;
  139. }
  140. if (x >= 2)
  141. r++;
  142. return r;
  143. }
  144. static void
  145. au1550_delay(int msec)
  146. {
  147. if (in_interrupt())
  148. return;
  149. schedule_timeout_uninterruptible(msecs_to_jiffies(msec));
  150. }
  151. static u16
  152. rdcodec(struct ac97_codec *codec, u8 addr)
  153. {
  154. struct au1550_state *s = codec->private_data;
  155. unsigned long flags;
  156. u32 cmd, val;
  157. u16 data;
  158. int i;
  159. spin_lock_irqsave(&s->lock, flags);
  160. for (i = 0; i < POLL_COUNT; i++) {
  161. val = au_readl(PSC_AC97STAT);
  162. au_sync();
  163. if (!(val & PSC_AC97STAT_CP))
  164. break;
  165. }
  166. if (i == POLL_COUNT)
  167. err("rdcodec: codec cmd pending expired!");
  168. cmd = (u32)PSC_AC97CDC_INDX(addr);
  169. cmd |= PSC_AC97CDC_RD; /* read command */
  170. au_writel(cmd, PSC_AC97CDC);
  171. au_sync();
  172. /* now wait for the data
  173. */
  174. for (i = 0; i < POLL_COUNT; i++) {
  175. val = au_readl(PSC_AC97STAT);
  176. au_sync();
  177. if (!(val & PSC_AC97STAT_CP))
  178. break;
  179. }
  180. if (i == POLL_COUNT) {
  181. err("rdcodec: read poll expired!");
  182. data = 0;
  183. goto out;
  184. }
  185. /* wait for command done?
  186. */
  187. for (i = 0; i < POLL_COUNT; i++) {
  188. val = au_readl(PSC_AC97EVNT);
  189. au_sync();
  190. if (val & PSC_AC97EVNT_CD)
  191. break;
  192. }
  193. if (i == POLL_COUNT) {
  194. err("rdcodec: read cmdwait expired!");
  195. data = 0;
  196. goto out;
  197. }
  198. data = au_readl(PSC_AC97CDC) & 0xffff;
  199. au_sync();
  200. /* Clear command done event.
  201. */
  202. au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
  203. au_sync();
  204. out:
  205. spin_unlock_irqrestore(&s->lock, flags);
  206. return data;
  207. }
  208. static void
  209. wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  210. {
  211. struct au1550_state *s = codec->private_data;
  212. unsigned long flags;
  213. u32 cmd, val;
  214. int i;
  215. spin_lock_irqsave(&s->lock, flags);
  216. for (i = 0; i < POLL_COUNT; i++) {
  217. val = au_readl(PSC_AC97STAT);
  218. au_sync();
  219. if (!(val & PSC_AC97STAT_CP))
  220. break;
  221. }
  222. if (i == POLL_COUNT)
  223. err("wrcodec: codec cmd pending expired!");
  224. cmd = (u32)PSC_AC97CDC_INDX(addr);
  225. cmd |= (u32)data;
  226. au_writel(cmd, PSC_AC97CDC);
  227. au_sync();
  228. for (i = 0; i < POLL_COUNT; i++) {
  229. val = au_readl(PSC_AC97STAT);
  230. au_sync();
  231. if (!(val & PSC_AC97STAT_CP))
  232. break;
  233. }
  234. if (i == POLL_COUNT)
  235. err("wrcodec: codec cmd pending expired!");
  236. for (i = 0; i < POLL_COUNT; i++) {
  237. val = au_readl(PSC_AC97EVNT);
  238. au_sync();
  239. if (val & PSC_AC97EVNT_CD)
  240. break;
  241. }
  242. if (i == POLL_COUNT)
  243. err("wrcodec: read cmdwait expired!");
  244. /* Clear command done event.
  245. */
  246. au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
  247. au_sync();
  248. spin_unlock_irqrestore(&s->lock, flags);
  249. }
  250. static void
  251. waitcodec(struct ac97_codec *codec)
  252. {
  253. u16 temp;
  254. u32 val;
  255. int i;
  256. /* codec_wait is used to wait for a ready state after
  257. * an AC97C_RESET.
  258. */
  259. au1550_delay(10);
  260. /* first poll the CODEC_READY tag bit
  261. */
  262. for (i = 0; i < POLL_COUNT; i++) {
  263. val = au_readl(PSC_AC97STAT);
  264. au_sync();
  265. if (val & PSC_AC97STAT_CR)
  266. break;
  267. }
  268. if (i == POLL_COUNT) {
  269. err("waitcodec: CODEC_READY poll expired!");
  270. return;
  271. }
  272. /* get AC'97 powerdown control/status register
  273. */
  274. temp = rdcodec(codec, AC97_POWER_CONTROL);
  275. /* If anything is powered down, power'em up
  276. */
  277. if (temp & 0x7f00) {
  278. /* Power on
  279. */
  280. wrcodec(codec, AC97_POWER_CONTROL, 0);
  281. au1550_delay(100);
  282. /* Reread
  283. */
  284. temp = rdcodec(codec, AC97_POWER_CONTROL);
  285. }
  286. /* Check if Codec REF,ANL,DAC,ADC ready
  287. */
  288. if ((temp & 0x7f0f) != 0x000f)
  289. err("codec reg 26 status (0x%x) not ready!!", temp);
  290. }
  291. /* stop the ADC before calling */
  292. static void
  293. set_adc_rate(struct au1550_state *s, unsigned rate)
  294. {
  295. struct dmabuf *adc = &s->dma_adc;
  296. struct dmabuf *dac = &s->dma_dac;
  297. unsigned adc_rate, dac_rate;
  298. u16 ac97_extstat;
  299. if (s->no_vra) {
  300. /* calc SRC factor
  301. */
  302. adc->src_factor = ((96000 / rate) + 1) >> 1;
  303. adc->sample_rate = 48000 / adc->src_factor;
  304. return;
  305. }
  306. adc->src_factor = 1;
  307. ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  308. rate = rate > 48000 ? 48000 : rate;
  309. /* enable VRA
  310. */
  311. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  312. ac97_extstat | AC97_EXTSTAT_VRA);
  313. /* now write the sample rate
  314. */
  315. wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
  316. /* read it back for actual supported rate
  317. */
  318. adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
  319. pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
  320. /* some codec's don't allow unequal DAC and ADC rates, in which case
  321. * writing one rate reg actually changes both.
  322. */
  323. dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  324. if (dac->num_channels > 2)
  325. wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
  326. if (dac->num_channels > 4)
  327. wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
  328. adc->sample_rate = adc_rate;
  329. dac->sample_rate = dac_rate;
  330. }
  331. /* stop the DAC before calling */
  332. static void
  333. set_dac_rate(struct au1550_state *s, unsigned rate)
  334. {
  335. struct dmabuf *dac = &s->dma_dac;
  336. struct dmabuf *adc = &s->dma_adc;
  337. unsigned adc_rate, dac_rate;
  338. u16 ac97_extstat;
  339. if (s->no_vra) {
  340. /* calc SRC factor
  341. */
  342. dac->src_factor = ((96000 / rate) + 1) >> 1;
  343. dac->sample_rate = 48000 / dac->src_factor;
  344. return;
  345. }
  346. dac->src_factor = 1;
  347. ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  348. rate = rate > 48000 ? 48000 : rate;
  349. /* enable VRA
  350. */
  351. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  352. ac97_extstat | AC97_EXTSTAT_VRA);
  353. /* now write the sample rate
  354. */
  355. wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
  356. /* I don't support different sample rates for multichannel,
  357. * so make these channels the same.
  358. */
  359. if (dac->num_channels > 2)
  360. wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
  361. if (dac->num_channels > 4)
  362. wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
  363. /* read it back for actual supported rate
  364. */
  365. dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  366. pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
  367. /* some codec's don't allow unequal DAC and ADC rates, in which case
  368. * writing one rate reg actually changes both.
  369. */
  370. adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
  371. dac->sample_rate = dac_rate;
  372. adc->sample_rate = adc_rate;
  373. }
  374. static void
  375. stop_dac(struct au1550_state *s)
  376. {
  377. struct dmabuf *db = &s->dma_dac;
  378. u32 stat;
  379. unsigned long flags;
  380. if (db->stopped)
  381. return;
  382. spin_lock_irqsave(&s->lock, flags);
  383. au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
  384. au_sync();
  385. /* Wait for Transmit Busy to show disabled.
  386. */
  387. do {
  388. stat = au_readl(PSC_AC97STAT);
  389. au_sync();
  390. } while ((stat & PSC_AC97STAT_TB) != 0);
  391. au1xxx_dbdma_reset(db->dmanr);
  392. db->stopped = 1;
  393. spin_unlock_irqrestore(&s->lock, flags);
  394. }
  395. static void
  396. stop_adc(struct au1550_state *s)
  397. {
  398. struct dmabuf *db = &s->dma_adc;
  399. unsigned long flags;
  400. u32 stat;
  401. if (db->stopped)
  402. return;
  403. spin_lock_irqsave(&s->lock, flags);
  404. au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
  405. au_sync();
  406. /* Wait for Receive Busy to show disabled.
  407. */
  408. do {
  409. stat = au_readl(PSC_AC97STAT);
  410. au_sync();
  411. } while ((stat & PSC_AC97STAT_RB) != 0);
  412. au1xxx_dbdma_reset(db->dmanr);
  413. db->stopped = 1;
  414. spin_unlock_irqrestore(&s->lock, flags);
  415. }
  416. static void
  417. set_xmit_slots(int num_channels)
  418. {
  419. u32 ac97_config, stat;
  420. ac97_config = au_readl(PSC_AC97CFG);
  421. au_sync();
  422. ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
  423. au_writel(ac97_config, PSC_AC97CFG);
  424. au_sync();
  425. switch (num_channels) {
  426. case 6: /* stereo with surround and center/LFE,
  427. * slots 3,4,6,7,8,9
  428. */
  429. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
  430. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
  431. case 4: /* stereo with surround, slots 3,4,7,8 */
  432. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
  433. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
  434. case 2: /* stereo, slots 3,4 */
  435. case 1: /* mono */
  436. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
  437. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
  438. }
  439. au_writel(ac97_config, PSC_AC97CFG);
  440. au_sync();
  441. ac97_config |= PSC_AC97CFG_DE_ENABLE;
  442. au_writel(ac97_config, PSC_AC97CFG);
  443. au_sync();
  444. /* Wait for Device ready.
  445. */
  446. do {
  447. stat = au_readl(PSC_AC97STAT);
  448. au_sync();
  449. } while ((stat & PSC_AC97STAT_DR) == 0);
  450. }
  451. static void
  452. set_recv_slots(int num_channels)
  453. {
  454. u32 ac97_config, stat;
  455. ac97_config = au_readl(PSC_AC97CFG);
  456. au_sync();
  457. ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
  458. au_writel(ac97_config, PSC_AC97CFG);
  459. au_sync();
  460. /* Always enable slots 3 and 4 (stereo). Slot 6 is
  461. * optional Mic ADC, which we don't support yet.
  462. */
  463. ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
  464. ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
  465. au_writel(ac97_config, PSC_AC97CFG);
  466. au_sync();
  467. ac97_config |= PSC_AC97CFG_DE_ENABLE;
  468. au_writel(ac97_config, PSC_AC97CFG);
  469. au_sync();
  470. /* Wait for Device ready.
  471. */
  472. do {
  473. stat = au_readl(PSC_AC97STAT);
  474. au_sync();
  475. } while ((stat & PSC_AC97STAT_DR) == 0);
  476. }
  477. /* Hold spinlock for both start_dac() and start_adc() calls */
  478. static void
  479. start_dac(struct au1550_state *s)
  480. {
  481. struct dmabuf *db = &s->dma_dac;
  482. if (!db->stopped)
  483. return;
  484. set_xmit_slots(db->num_channels);
  485. au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
  486. au_sync();
  487. au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
  488. au_sync();
  489. au1xxx_dbdma_start(db->dmanr);
  490. db->stopped = 0;
  491. }
  492. static void
  493. start_adc(struct au1550_state *s)
  494. {
  495. struct dmabuf *db = &s->dma_adc;
  496. int i;
  497. if (!db->stopped)
  498. return;
  499. /* Put two buffers on the ring to get things started.
  500. */
  501. for (i=0; i<2; i++) {
  502. au1xxx_dbdma_put_dest(db->dmanr, virt_to_phys(db->nextIn),
  503. db->dma_fragsize, DDMA_FLAGS_IE);
  504. db->nextIn += db->dma_fragsize;
  505. if (db->nextIn >= db->rawbuf + db->dmasize)
  506. db->nextIn -= db->dmasize;
  507. }
  508. set_recv_slots(db->num_channels);
  509. au1xxx_dbdma_start(db->dmanr);
  510. au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
  511. au_sync();
  512. au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
  513. au_sync();
  514. db->stopped = 0;
  515. }
  516. static int
  517. prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
  518. {
  519. unsigned user_bytes_per_sec;
  520. unsigned bufs;
  521. unsigned rate = db->sample_rate;
  522. if (!db->rawbuf) {
  523. db->ready = db->mapped = 0;
  524. db->buforder = 5; /* 32 * PAGE_SIZE */
  525. db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
  526. if (!db->rawbuf)
  527. return -ENOMEM;
  528. }
  529. db->cnt_factor = 1;
  530. if (db->sample_size == 8)
  531. db->cnt_factor *= 2;
  532. if (db->num_channels == 1)
  533. db->cnt_factor *= 2;
  534. db->cnt_factor *= db->src_factor;
  535. db->count = 0;
  536. db->dma_qcount = 0;
  537. db->nextIn = db->nextOut = db->rawbuf;
  538. db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
  539. db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
  540. 2 : db->num_channels);
  541. user_bytes_per_sec = rate * db->user_bytes_per_sample;
  542. bufs = PAGE_SIZE << db->buforder;
  543. if (db->ossfragshift) {
  544. if ((1000 << db->ossfragshift) < user_bytes_per_sec)
  545. db->fragshift = ld2(user_bytes_per_sec/1000);
  546. else
  547. db->fragshift = db->ossfragshift;
  548. } else {
  549. db->fragshift = ld2(user_bytes_per_sec / 100 /
  550. (db->subdivision ? db->subdivision : 1));
  551. if (db->fragshift < 3)
  552. db->fragshift = 3;
  553. }
  554. db->fragsize = 1 << db->fragshift;
  555. db->dma_fragsize = db->fragsize * db->cnt_factor;
  556. db->numfrag = bufs / db->dma_fragsize;
  557. while (db->numfrag < 4 && db->fragshift > 3) {
  558. db->fragshift--;
  559. db->fragsize = 1 << db->fragshift;
  560. db->dma_fragsize = db->fragsize * db->cnt_factor;
  561. db->numfrag = bufs / db->dma_fragsize;
  562. }
  563. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  564. db->numfrag = db->ossmaxfrags;
  565. db->dmasize = db->dma_fragsize * db->numfrag;
  566. memset(db->rawbuf, 0, bufs);
  567. pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
  568. rate, db->sample_size, db->num_channels);
  569. pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
  570. db->fragsize, db->cnt_factor, db->dma_fragsize);
  571. pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
  572. db->ready = 1;
  573. return 0;
  574. }
  575. static int
  576. prog_dmabuf_adc(struct au1550_state *s)
  577. {
  578. stop_adc(s);
  579. return prog_dmabuf(s, &s->dma_adc);
  580. }
  581. static int
  582. prog_dmabuf_dac(struct au1550_state *s)
  583. {
  584. stop_dac(s);
  585. return prog_dmabuf(s, &s->dma_dac);
  586. }
  587. static void dac_dma_interrupt(int irq, void *dev_id)
  588. {
  589. struct au1550_state *s = (struct au1550_state *) dev_id;
  590. struct dmabuf *db = &s->dma_dac;
  591. u32 ac97c_stat;
  592. spin_lock(&s->lock);
  593. ac97c_stat = au_readl(PSC_AC97STAT);
  594. if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
  595. pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
  596. db->dma_qcount--;
  597. if (db->count >= db->fragsize) {
  598. if (au1xxx_dbdma_put_source(db->dmanr,
  599. virt_to_phys(db->nextOut), db->fragsize,
  600. DDMA_FLAGS_IE) == 0) {
  601. err("qcount < 2 and no ring room!");
  602. }
  603. db->nextOut += db->fragsize;
  604. if (db->nextOut >= db->rawbuf + db->dmasize)
  605. db->nextOut -= db->dmasize;
  606. db->count -= db->fragsize;
  607. db->total_bytes += db->dma_fragsize;
  608. db->dma_qcount++;
  609. }
  610. /* wake up anybody listening */
  611. if (waitqueue_active(&db->wait))
  612. wake_up(&db->wait);
  613. spin_unlock(&s->lock);
  614. }
  615. static void adc_dma_interrupt(int irq, void *dev_id)
  616. {
  617. struct au1550_state *s = (struct au1550_state *)dev_id;
  618. struct dmabuf *dp = &s->dma_adc;
  619. u32 obytes;
  620. char *obuf;
  621. spin_lock(&s->lock);
  622. /* Pull the buffer from the dma queue.
  623. */
  624. au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
  625. if ((dp->count + obytes) > dp->dmasize) {
  626. /* Overrun. Stop ADC and log the error
  627. */
  628. spin_unlock(&s->lock);
  629. stop_adc(s);
  630. dp->error++;
  631. err("adc overrun");
  632. return;
  633. }
  634. /* Put a new empty buffer on the destination DMA.
  635. */
  636. au1xxx_dbdma_put_dest(dp->dmanr, virt_to_phys(dp->nextIn),
  637. dp->dma_fragsize, DDMA_FLAGS_IE);
  638. dp->nextIn += dp->dma_fragsize;
  639. if (dp->nextIn >= dp->rawbuf + dp->dmasize)
  640. dp->nextIn -= dp->dmasize;
  641. dp->count += obytes;
  642. dp->total_bytes += obytes;
  643. /* wake up anybody listening
  644. */
  645. if (waitqueue_active(&dp->wait))
  646. wake_up(&dp->wait);
  647. spin_unlock(&s->lock);
  648. }
  649. static loff_t
  650. au1550_llseek(struct file *file, loff_t offset, int origin)
  651. {
  652. return -ESPIPE;
  653. }
  654. static int
  655. au1550_open_mixdev(struct inode *inode, struct file *file)
  656. {
  657. mutex_lock(&au1550_ac97_mutex);
  658. file->private_data = &au1550_state;
  659. mutex_unlock(&au1550_ac97_mutex);
  660. return 0;
  661. }
  662. static int
  663. au1550_release_mixdev(struct inode *inode, struct file *file)
  664. {
  665. return 0;
  666. }
  667. static int
  668. mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
  669. unsigned long arg)
  670. {
  671. return codec->mixer_ioctl(codec, cmd, arg);
  672. }
  673. static long
  674. au1550_ioctl_mixdev(struct file *file, unsigned int cmd, unsigned long arg)
  675. {
  676. struct au1550_state *s = file->private_data;
  677. struct ac97_codec *codec = s->codec;
  678. int ret;
  679. mutex_lock(&au1550_ac97_mutex);
  680. ret = mixdev_ioctl(codec, cmd, arg);
  681. mutex_unlock(&au1550_ac97_mutex);
  682. return ret;
  683. }
  684. static /*const */ struct file_operations au1550_mixer_fops = {
  685. .owner = THIS_MODULE,
  686. .llseek = au1550_llseek,
  687. .unlocked_ioctl = au1550_ioctl_mixdev,
  688. .open = au1550_open_mixdev,
  689. .release = au1550_release_mixdev,
  690. };
  691. static int
  692. drain_dac(struct au1550_state *s, int nonblock)
  693. {
  694. unsigned long flags;
  695. int count, tmo;
  696. if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
  697. return 0;
  698. for (;;) {
  699. spin_lock_irqsave(&s->lock, flags);
  700. count = s->dma_dac.count;
  701. spin_unlock_irqrestore(&s->lock, flags);
  702. if (count <= s->dma_dac.fragsize)
  703. break;
  704. if (signal_pending(current))
  705. break;
  706. if (nonblock)
  707. return -EBUSY;
  708. tmo = 1000 * count / (s->no_vra ?
  709. 48000 : s->dma_dac.sample_rate);
  710. tmo /= s->dma_dac.dma_bytes_per_sample;
  711. au1550_delay(tmo);
  712. }
  713. if (signal_pending(current))
  714. return -ERESTARTSYS;
  715. return 0;
  716. }
  717. static inline u8 S16_TO_U8(s16 ch)
  718. {
  719. return (u8) (ch >> 8) + 0x80;
  720. }
  721. static inline s16 U8_TO_S16(u8 ch)
  722. {
  723. return (s16) (ch - 0x80) << 8;
  724. }
  725. /*
  726. * Translates user samples to dma buffer suitable for AC'97 DAC data:
  727. * If mono, copy left channel to right channel in dma buffer.
  728. * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
  729. * If interpolating (no VRA), duplicate every audio frame src_factor times.
  730. */
  731. static int
  732. translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
  733. int dmacount)
  734. {
  735. int sample, i;
  736. int interp_bytes_per_sample;
  737. int num_samples;
  738. int mono = (db->num_channels == 1);
  739. char usersample[12];
  740. s16 ch, dmasample[6];
  741. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  742. /* no translation necessary, just copy
  743. */
  744. if (copy_from_user(dmabuf, userbuf, dmacount))
  745. return -EFAULT;
  746. return dmacount;
  747. }
  748. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  749. num_samples = dmacount / interp_bytes_per_sample;
  750. for (sample = 0; sample < num_samples; sample++) {
  751. if (copy_from_user(usersample, userbuf,
  752. db->user_bytes_per_sample)) {
  753. return -EFAULT;
  754. }
  755. for (i = 0; i < db->num_channels; i++) {
  756. if (db->sample_size == 8)
  757. ch = U8_TO_S16(usersample[i]);
  758. else
  759. ch = *((s16 *) (&usersample[i * 2]));
  760. dmasample[i] = ch;
  761. if (mono)
  762. dmasample[i + 1] = ch; /* right channel */
  763. }
  764. /* duplicate every audio frame src_factor times
  765. */
  766. for (i = 0; i < db->src_factor; i++)
  767. memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
  768. userbuf += db->user_bytes_per_sample;
  769. dmabuf += interp_bytes_per_sample;
  770. }
  771. return num_samples * interp_bytes_per_sample;
  772. }
  773. /*
  774. * Translates AC'97 ADC samples to user buffer:
  775. * If mono, send only left channel to user buffer.
  776. * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
  777. * If decimating (no VRA), skip over src_factor audio frames.
  778. */
  779. static int
  780. translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
  781. int dmacount)
  782. {
  783. int sample, i;
  784. int interp_bytes_per_sample;
  785. int num_samples;
  786. int mono = (db->num_channels == 1);
  787. char usersample[12];
  788. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  789. /* no translation necessary, just copy
  790. */
  791. if (copy_to_user(userbuf, dmabuf, dmacount))
  792. return -EFAULT;
  793. return dmacount;
  794. }
  795. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  796. num_samples = dmacount / interp_bytes_per_sample;
  797. for (sample = 0; sample < num_samples; sample++) {
  798. for (i = 0; i < db->num_channels; i++) {
  799. if (db->sample_size == 8)
  800. usersample[i] =
  801. S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
  802. else
  803. *((s16 *) (&usersample[i * 2])) =
  804. *((s16 *) (&dmabuf[i * 2]));
  805. }
  806. if (copy_to_user(userbuf, usersample,
  807. db->user_bytes_per_sample)) {
  808. return -EFAULT;
  809. }
  810. userbuf += db->user_bytes_per_sample;
  811. dmabuf += interp_bytes_per_sample;
  812. }
  813. return num_samples * interp_bytes_per_sample;
  814. }
  815. /*
  816. * Copy audio data to/from user buffer from/to dma buffer, taking care
  817. * that we wrap when reading/writing the dma buffer. Returns actual byte
  818. * count written to or read from the dma buffer.
  819. */
  820. static int
  821. copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
  822. {
  823. char *bufptr = to_user ? db->nextOut : db->nextIn;
  824. char *bufend = db->rawbuf + db->dmasize;
  825. int cnt, ret;
  826. if (bufptr + count > bufend) {
  827. int partial = (int) (bufend - bufptr);
  828. if (to_user) {
  829. if ((cnt = translate_to_user(db, userbuf,
  830. bufptr, partial)) < 0)
  831. return cnt;
  832. ret = cnt;
  833. if ((cnt = translate_to_user(db, userbuf + partial,
  834. db->rawbuf,
  835. count - partial)) < 0)
  836. return cnt;
  837. ret += cnt;
  838. } else {
  839. if ((cnt = translate_from_user(db, bufptr, userbuf,
  840. partial)) < 0)
  841. return cnt;
  842. ret = cnt;
  843. if ((cnt = translate_from_user(db, db->rawbuf,
  844. userbuf + partial,
  845. count - partial)) < 0)
  846. return cnt;
  847. ret += cnt;
  848. }
  849. } else {
  850. if (to_user)
  851. ret = translate_to_user(db, userbuf, bufptr, count);
  852. else
  853. ret = translate_from_user(db, bufptr, userbuf, count);
  854. }
  855. return ret;
  856. }
  857. static ssize_t
  858. au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
  859. {
  860. struct au1550_state *s = file->private_data;
  861. struct dmabuf *db = &s->dma_adc;
  862. DECLARE_WAITQUEUE(wait, current);
  863. ssize_t ret;
  864. unsigned long flags;
  865. int cnt, usercnt, avail;
  866. if (db->mapped)
  867. return -ENXIO;
  868. if (!access_ok(VERIFY_WRITE, buffer, count))
  869. return -EFAULT;
  870. ret = 0;
  871. count *= db->cnt_factor;
  872. mutex_lock(&s->sem);
  873. add_wait_queue(&db->wait, &wait);
  874. while (count > 0) {
  875. /* wait for samples in ADC dma buffer
  876. */
  877. do {
  878. spin_lock_irqsave(&s->lock, flags);
  879. if (db->stopped)
  880. start_adc(s);
  881. avail = db->count;
  882. if (avail <= 0)
  883. __set_current_state(TASK_INTERRUPTIBLE);
  884. spin_unlock_irqrestore(&s->lock, flags);
  885. if (avail <= 0) {
  886. if (file->f_flags & O_NONBLOCK) {
  887. if (!ret)
  888. ret = -EAGAIN;
  889. goto out;
  890. }
  891. mutex_unlock(&s->sem);
  892. schedule();
  893. if (signal_pending(current)) {
  894. if (!ret)
  895. ret = -ERESTARTSYS;
  896. goto out2;
  897. }
  898. mutex_lock(&s->sem);
  899. }
  900. } while (avail <= 0);
  901. /* copy from nextOut to user
  902. */
  903. if ((cnt = copy_dmabuf_user(db, buffer,
  904. count > avail ?
  905. avail : count, 1)) < 0) {
  906. if (!ret)
  907. ret = -EFAULT;
  908. goto out;
  909. }
  910. spin_lock_irqsave(&s->lock, flags);
  911. db->count -= cnt;
  912. db->nextOut += cnt;
  913. if (db->nextOut >= db->rawbuf + db->dmasize)
  914. db->nextOut -= db->dmasize;
  915. spin_unlock_irqrestore(&s->lock, flags);
  916. count -= cnt;
  917. usercnt = cnt / db->cnt_factor;
  918. buffer += usercnt;
  919. ret += usercnt;
  920. } /* while (count > 0) */
  921. out:
  922. mutex_unlock(&s->sem);
  923. out2:
  924. remove_wait_queue(&db->wait, &wait);
  925. set_current_state(TASK_RUNNING);
  926. return ret;
  927. }
  928. static ssize_t
  929. au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
  930. {
  931. struct au1550_state *s = file->private_data;
  932. struct dmabuf *db = &s->dma_dac;
  933. DECLARE_WAITQUEUE(wait, current);
  934. ssize_t ret = 0;
  935. unsigned long flags;
  936. int cnt, usercnt, avail;
  937. pr_debug("write: count=%d\n", count);
  938. if (db->mapped)
  939. return -ENXIO;
  940. if (!access_ok(VERIFY_READ, buffer, count))
  941. return -EFAULT;
  942. count *= db->cnt_factor;
  943. mutex_lock(&s->sem);
  944. add_wait_queue(&db->wait, &wait);
  945. while (count > 0) {
  946. /* wait for space in playback buffer
  947. */
  948. do {
  949. spin_lock_irqsave(&s->lock, flags);
  950. avail = (int) db->dmasize - db->count;
  951. if (avail <= 0)
  952. __set_current_state(TASK_INTERRUPTIBLE);
  953. spin_unlock_irqrestore(&s->lock, flags);
  954. if (avail <= 0) {
  955. if (file->f_flags & O_NONBLOCK) {
  956. if (!ret)
  957. ret = -EAGAIN;
  958. goto out;
  959. }
  960. mutex_unlock(&s->sem);
  961. schedule();
  962. if (signal_pending(current)) {
  963. if (!ret)
  964. ret = -ERESTARTSYS;
  965. goto out2;
  966. }
  967. mutex_lock(&s->sem);
  968. }
  969. } while (avail <= 0);
  970. /* copy from user to nextIn
  971. */
  972. if ((cnt = copy_dmabuf_user(db, (char *) buffer,
  973. count > avail ?
  974. avail : count, 0)) < 0) {
  975. if (!ret)
  976. ret = -EFAULT;
  977. goto out;
  978. }
  979. spin_lock_irqsave(&s->lock, flags);
  980. db->count += cnt;
  981. db->nextIn += cnt;
  982. if (db->nextIn >= db->rawbuf + db->dmasize)
  983. db->nextIn -= db->dmasize;
  984. /* If the data is available, we want to keep two buffers
  985. * on the dma queue. If the queue count reaches zero,
  986. * we know the dma has stopped.
  987. */
  988. while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
  989. if (au1xxx_dbdma_put_source(db->dmanr,
  990. virt_to_phys(db->nextOut), db->fragsize,
  991. DDMA_FLAGS_IE) == 0) {
  992. err("qcount < 2 and no ring room!");
  993. }
  994. db->nextOut += db->fragsize;
  995. if (db->nextOut >= db->rawbuf + db->dmasize)
  996. db->nextOut -= db->dmasize;
  997. db->total_bytes += db->dma_fragsize;
  998. if (db->dma_qcount == 0)
  999. start_dac(s);
  1000. db->dma_qcount++;
  1001. }
  1002. spin_unlock_irqrestore(&s->lock, flags);
  1003. count -= cnt;
  1004. usercnt = cnt / db->cnt_factor;
  1005. buffer += usercnt;
  1006. ret += usercnt;
  1007. } /* while (count > 0) */
  1008. out:
  1009. mutex_unlock(&s->sem);
  1010. out2:
  1011. remove_wait_queue(&db->wait, &wait);
  1012. set_current_state(TASK_RUNNING);
  1013. return ret;
  1014. }
  1015. /* No kernel lock - we have our own spinlock */
  1016. static unsigned int
  1017. au1550_poll(struct file *file, struct poll_table_struct *wait)
  1018. {
  1019. struct au1550_state *s = file->private_data;
  1020. unsigned long flags;
  1021. unsigned int mask = 0;
  1022. if (file->f_mode & FMODE_WRITE) {
  1023. if (!s->dma_dac.ready)
  1024. return 0;
  1025. poll_wait(file, &s->dma_dac.wait, wait);
  1026. }
  1027. if (file->f_mode & FMODE_READ) {
  1028. if (!s->dma_adc.ready)
  1029. return 0;
  1030. poll_wait(file, &s->dma_adc.wait, wait);
  1031. }
  1032. spin_lock_irqsave(&s->lock, flags);
  1033. if (file->f_mode & FMODE_READ) {
  1034. if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
  1035. mask |= POLLIN | POLLRDNORM;
  1036. }
  1037. if (file->f_mode & FMODE_WRITE) {
  1038. if (s->dma_dac.mapped) {
  1039. if (s->dma_dac.count >=
  1040. (signed)s->dma_dac.dma_fragsize)
  1041. mask |= POLLOUT | POLLWRNORM;
  1042. } else {
  1043. if ((signed) s->dma_dac.dmasize >=
  1044. s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
  1045. mask |= POLLOUT | POLLWRNORM;
  1046. }
  1047. }
  1048. spin_unlock_irqrestore(&s->lock, flags);
  1049. return mask;
  1050. }
  1051. static int
  1052. au1550_mmap(struct file *file, struct vm_area_struct *vma)
  1053. {
  1054. struct au1550_state *s = file->private_data;
  1055. struct dmabuf *db;
  1056. unsigned long size;
  1057. int ret = 0;
  1058. mutex_lock(&au1550_ac97_mutex);
  1059. mutex_lock(&s->sem);
  1060. if (vma->vm_flags & VM_WRITE)
  1061. db = &s->dma_dac;
  1062. else if (vma->vm_flags & VM_READ)
  1063. db = &s->dma_adc;
  1064. else {
  1065. ret = -EINVAL;
  1066. goto out;
  1067. }
  1068. if (vma->vm_pgoff != 0) {
  1069. ret = -EINVAL;
  1070. goto out;
  1071. }
  1072. size = vma->vm_end - vma->vm_start;
  1073. if (size > (PAGE_SIZE << db->buforder)) {
  1074. ret = -EINVAL;
  1075. goto out;
  1076. }
  1077. if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
  1078. size, vma->vm_page_prot)) {
  1079. ret = -EAGAIN;
  1080. goto out;
  1081. }
  1082. vma->vm_flags &= ~VM_IO;
  1083. db->mapped = 1;
  1084. out:
  1085. mutex_unlock(&s->sem);
  1086. mutex_unlock(&au1550_ac97_mutex);
  1087. return ret;
  1088. }
  1089. #ifdef DEBUG
  1090. static struct ioctl_str_t {
  1091. unsigned int cmd;
  1092. const char *str;
  1093. } ioctl_str[] = {
  1094. {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
  1095. {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
  1096. {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
  1097. {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
  1098. {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
  1099. {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
  1100. {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
  1101. {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
  1102. {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
  1103. {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
  1104. {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
  1105. {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
  1106. {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
  1107. {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
  1108. {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
  1109. {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
  1110. {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
  1111. {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
  1112. {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
  1113. {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
  1114. {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
  1115. {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
  1116. {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
  1117. {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
  1118. {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
  1119. {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
  1120. {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
  1121. {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
  1122. {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
  1123. {OSS_GETVERSION, "OSS_GETVERSION"},
  1124. {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
  1125. {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
  1126. {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
  1127. {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
  1128. };
  1129. #endif
  1130. static int
  1131. dma_count_done(struct dmabuf *db)
  1132. {
  1133. if (db->stopped)
  1134. return 0;
  1135. return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
  1136. }
  1137. static int
  1138. au1550_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  1139. {
  1140. struct au1550_state *s = file->private_data;
  1141. unsigned long flags;
  1142. audio_buf_info abinfo;
  1143. count_info cinfo;
  1144. int count;
  1145. int val, mapped, ret, diff;
  1146. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1147. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1148. #ifdef DEBUG
  1149. for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
  1150. if (ioctl_str[count].cmd == cmd)
  1151. break;
  1152. }
  1153. if (count < ARRAY_SIZE(ioctl_str))
  1154. pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
  1155. else
  1156. pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
  1157. #endif
  1158. switch (cmd) {
  1159. case OSS_GETVERSION:
  1160. return put_user(SOUND_VERSION, (int *) arg);
  1161. case SNDCTL_DSP_SYNC:
  1162. if (file->f_mode & FMODE_WRITE)
  1163. return drain_dac(s, file->f_flags & O_NONBLOCK);
  1164. return 0;
  1165. case SNDCTL_DSP_SETDUPLEX:
  1166. return 0;
  1167. case SNDCTL_DSP_GETCAPS:
  1168. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
  1169. DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
  1170. case SNDCTL_DSP_RESET:
  1171. if (file->f_mode & FMODE_WRITE) {
  1172. stop_dac(s);
  1173. synchronize_irq();
  1174. s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1175. s->dma_dac.nextIn = s->dma_dac.nextOut =
  1176. s->dma_dac.rawbuf;
  1177. }
  1178. if (file->f_mode & FMODE_READ) {
  1179. stop_adc(s);
  1180. synchronize_irq();
  1181. s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1182. s->dma_adc.nextIn = s->dma_adc.nextOut =
  1183. s->dma_adc.rawbuf;
  1184. }
  1185. return 0;
  1186. case SNDCTL_DSP_SPEED:
  1187. if (get_user(val, (int *) arg))
  1188. return -EFAULT;
  1189. if (val >= 0) {
  1190. if (file->f_mode & FMODE_READ) {
  1191. stop_adc(s);
  1192. set_adc_rate(s, val);
  1193. }
  1194. if (file->f_mode & FMODE_WRITE) {
  1195. stop_dac(s);
  1196. set_dac_rate(s, val);
  1197. }
  1198. if (s->open_mode & FMODE_READ)
  1199. if ((ret = prog_dmabuf_adc(s)))
  1200. return ret;
  1201. if (s->open_mode & FMODE_WRITE)
  1202. if ((ret = prog_dmabuf_dac(s)))
  1203. return ret;
  1204. }
  1205. return put_user((file->f_mode & FMODE_READ) ?
  1206. s->dma_adc.sample_rate :
  1207. s->dma_dac.sample_rate,
  1208. (int *)arg);
  1209. case SNDCTL_DSP_STEREO:
  1210. if (get_user(val, (int *) arg))
  1211. return -EFAULT;
  1212. if (file->f_mode & FMODE_READ) {
  1213. stop_adc(s);
  1214. s->dma_adc.num_channels = val ? 2 : 1;
  1215. if ((ret = prog_dmabuf_adc(s)))
  1216. return ret;
  1217. }
  1218. if (file->f_mode & FMODE_WRITE) {
  1219. stop_dac(s);
  1220. s->dma_dac.num_channels = val ? 2 : 1;
  1221. if (s->codec_ext_caps & AC97_EXT_DACS) {
  1222. /* disable surround and center/lfe in AC'97
  1223. */
  1224. u16 ext_stat = rdcodec(s->codec,
  1225. AC97_EXTENDED_STATUS);
  1226. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1227. ext_stat | (AC97_EXTSTAT_PRI |
  1228. AC97_EXTSTAT_PRJ |
  1229. AC97_EXTSTAT_PRK));
  1230. }
  1231. if ((ret = prog_dmabuf_dac(s)))
  1232. return ret;
  1233. }
  1234. return 0;
  1235. case SNDCTL_DSP_CHANNELS:
  1236. if (get_user(val, (int *) arg))
  1237. return -EFAULT;
  1238. if (val != 0) {
  1239. if (file->f_mode & FMODE_READ) {
  1240. if (val < 0 || val > 2)
  1241. return -EINVAL;
  1242. stop_adc(s);
  1243. s->dma_adc.num_channels = val;
  1244. if ((ret = prog_dmabuf_adc(s)))
  1245. return ret;
  1246. }
  1247. if (file->f_mode & FMODE_WRITE) {
  1248. switch (val) {
  1249. case 1:
  1250. case 2:
  1251. break;
  1252. case 3:
  1253. case 5:
  1254. return -EINVAL;
  1255. case 4:
  1256. if (!(s->codec_ext_caps &
  1257. AC97_EXTID_SDAC))
  1258. return -EINVAL;
  1259. break;
  1260. case 6:
  1261. if ((s->codec_ext_caps &
  1262. AC97_EXT_DACS) != AC97_EXT_DACS)
  1263. return -EINVAL;
  1264. break;
  1265. default:
  1266. return -EINVAL;
  1267. }
  1268. stop_dac(s);
  1269. if (val <= 2 &&
  1270. (s->codec_ext_caps & AC97_EXT_DACS)) {
  1271. /* disable surround and center/lfe
  1272. * channels in AC'97
  1273. */
  1274. u16 ext_stat =
  1275. rdcodec(s->codec,
  1276. AC97_EXTENDED_STATUS);
  1277. wrcodec(s->codec,
  1278. AC97_EXTENDED_STATUS,
  1279. ext_stat | (AC97_EXTSTAT_PRI |
  1280. AC97_EXTSTAT_PRJ |
  1281. AC97_EXTSTAT_PRK));
  1282. } else if (val >= 4) {
  1283. /* enable surround, center/lfe
  1284. * channels in AC'97
  1285. */
  1286. u16 ext_stat =
  1287. rdcodec(s->codec,
  1288. AC97_EXTENDED_STATUS);
  1289. ext_stat &= ~AC97_EXTSTAT_PRJ;
  1290. if (val == 6)
  1291. ext_stat &=
  1292. ~(AC97_EXTSTAT_PRI |
  1293. AC97_EXTSTAT_PRK);
  1294. wrcodec(s->codec,
  1295. AC97_EXTENDED_STATUS,
  1296. ext_stat);
  1297. }
  1298. s->dma_dac.num_channels = val;
  1299. if ((ret = prog_dmabuf_dac(s)))
  1300. return ret;
  1301. }
  1302. }
  1303. return put_user(val, (int *) arg);
  1304. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1305. return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
  1306. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
  1307. if (get_user(val, (int *) arg))
  1308. return -EFAULT;
  1309. if (val != AFMT_QUERY) {
  1310. if (file->f_mode & FMODE_READ) {
  1311. stop_adc(s);
  1312. if (val == AFMT_S16_LE)
  1313. s->dma_adc.sample_size = 16;
  1314. else {
  1315. val = AFMT_U8;
  1316. s->dma_adc.sample_size = 8;
  1317. }
  1318. if ((ret = prog_dmabuf_adc(s)))
  1319. return ret;
  1320. }
  1321. if (file->f_mode & FMODE_WRITE) {
  1322. stop_dac(s);
  1323. if (val == AFMT_S16_LE)
  1324. s->dma_dac.sample_size = 16;
  1325. else {
  1326. val = AFMT_U8;
  1327. s->dma_dac.sample_size = 8;
  1328. }
  1329. if ((ret = prog_dmabuf_dac(s)))
  1330. return ret;
  1331. }
  1332. } else {
  1333. if (file->f_mode & FMODE_READ)
  1334. val = (s->dma_adc.sample_size == 16) ?
  1335. AFMT_S16_LE : AFMT_U8;
  1336. else
  1337. val = (s->dma_dac.sample_size == 16) ?
  1338. AFMT_S16_LE : AFMT_U8;
  1339. }
  1340. return put_user(val, (int *) arg);
  1341. case SNDCTL_DSP_POST:
  1342. return 0;
  1343. case SNDCTL_DSP_GETTRIGGER:
  1344. val = 0;
  1345. spin_lock_irqsave(&s->lock, flags);
  1346. if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
  1347. val |= PCM_ENABLE_INPUT;
  1348. if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
  1349. val |= PCM_ENABLE_OUTPUT;
  1350. spin_unlock_irqrestore(&s->lock, flags);
  1351. return put_user(val, (int *) arg);
  1352. case SNDCTL_DSP_SETTRIGGER:
  1353. if (get_user(val, (int *) arg))
  1354. return -EFAULT;
  1355. if (file->f_mode & FMODE_READ) {
  1356. if (val & PCM_ENABLE_INPUT) {
  1357. spin_lock_irqsave(&s->lock, flags);
  1358. start_adc(s);
  1359. spin_unlock_irqrestore(&s->lock, flags);
  1360. } else
  1361. stop_adc(s);
  1362. }
  1363. if (file->f_mode & FMODE_WRITE) {
  1364. if (val & PCM_ENABLE_OUTPUT) {
  1365. spin_lock_irqsave(&s->lock, flags);
  1366. start_dac(s);
  1367. spin_unlock_irqrestore(&s->lock, flags);
  1368. } else
  1369. stop_dac(s);
  1370. }
  1371. return 0;
  1372. case SNDCTL_DSP_GETOSPACE:
  1373. if (!(file->f_mode & FMODE_WRITE))
  1374. return -EINVAL;
  1375. abinfo.fragsize = s->dma_dac.fragsize;
  1376. spin_lock_irqsave(&s->lock, flags);
  1377. count = s->dma_dac.count;
  1378. count -= dma_count_done(&s->dma_dac);
  1379. spin_unlock_irqrestore(&s->lock, flags);
  1380. if (count < 0)
  1381. count = 0;
  1382. abinfo.bytes = (s->dma_dac.dmasize - count) /
  1383. s->dma_dac.cnt_factor;
  1384. abinfo.fragstotal = s->dma_dac.numfrag;
  1385. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1386. pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
  1387. return copy_to_user((void *) arg, &abinfo,
  1388. sizeof(abinfo)) ? -EFAULT : 0;
  1389. case SNDCTL_DSP_GETISPACE:
  1390. if (!(file->f_mode & FMODE_READ))
  1391. return -EINVAL;
  1392. abinfo.fragsize = s->dma_adc.fragsize;
  1393. spin_lock_irqsave(&s->lock, flags);
  1394. count = s->dma_adc.count;
  1395. count += dma_count_done(&s->dma_adc);
  1396. spin_unlock_irqrestore(&s->lock, flags);
  1397. if (count < 0)
  1398. count = 0;
  1399. abinfo.bytes = count / s->dma_adc.cnt_factor;
  1400. abinfo.fragstotal = s->dma_adc.numfrag;
  1401. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1402. return copy_to_user((void *) arg, &abinfo,
  1403. sizeof(abinfo)) ? -EFAULT : 0;
  1404. case SNDCTL_DSP_NONBLOCK:
  1405. spin_lock(&file->f_lock);
  1406. file->f_flags |= O_NONBLOCK;
  1407. spin_unlock(&file->f_lock);
  1408. return 0;
  1409. case SNDCTL_DSP_GETODELAY:
  1410. if (!(file->f_mode & FMODE_WRITE))
  1411. return -EINVAL;
  1412. spin_lock_irqsave(&s->lock, flags);
  1413. count = s->dma_dac.count;
  1414. count -= dma_count_done(&s->dma_dac);
  1415. spin_unlock_irqrestore(&s->lock, flags);
  1416. if (count < 0)
  1417. count = 0;
  1418. count /= s->dma_dac.cnt_factor;
  1419. return put_user(count, (int *) arg);
  1420. case SNDCTL_DSP_GETIPTR:
  1421. if (!(file->f_mode & FMODE_READ))
  1422. return -EINVAL;
  1423. spin_lock_irqsave(&s->lock, flags);
  1424. cinfo.bytes = s->dma_adc.total_bytes;
  1425. count = s->dma_adc.count;
  1426. if (!s->dma_adc.stopped) {
  1427. diff = dma_count_done(&s->dma_adc);
  1428. count += diff;
  1429. cinfo.bytes += diff;
  1430. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
  1431. virt_to_phys(s->dma_adc.rawbuf);
  1432. } else
  1433. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
  1434. virt_to_phys(s->dma_adc.rawbuf);
  1435. if (s->dma_adc.mapped)
  1436. s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
  1437. spin_unlock_irqrestore(&s->lock, flags);
  1438. if (count < 0)
  1439. count = 0;
  1440. cinfo.blocks = count >> s->dma_adc.fragshift;
  1441. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
  1442. case SNDCTL_DSP_GETOPTR:
  1443. if (!(file->f_mode & FMODE_READ))
  1444. return -EINVAL;
  1445. spin_lock_irqsave(&s->lock, flags);
  1446. cinfo.bytes = s->dma_dac.total_bytes;
  1447. count = s->dma_dac.count;
  1448. if (!s->dma_dac.stopped) {
  1449. diff = dma_count_done(&s->dma_dac);
  1450. count -= diff;
  1451. cinfo.bytes += diff;
  1452. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
  1453. virt_to_phys(s->dma_dac.rawbuf);
  1454. } else
  1455. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
  1456. virt_to_phys(s->dma_dac.rawbuf);
  1457. if (s->dma_dac.mapped)
  1458. s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
  1459. spin_unlock_irqrestore(&s->lock, flags);
  1460. if (count < 0)
  1461. count = 0;
  1462. cinfo.blocks = count >> s->dma_dac.fragshift;
  1463. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
  1464. case SNDCTL_DSP_GETBLKSIZE:
  1465. if (file->f_mode & FMODE_WRITE)
  1466. return put_user(s->dma_dac.fragsize, (int *) arg);
  1467. else
  1468. return put_user(s->dma_adc.fragsize, (int *) arg);
  1469. case SNDCTL_DSP_SETFRAGMENT:
  1470. if (get_user(val, (int *) arg))
  1471. return -EFAULT;
  1472. if (file->f_mode & FMODE_READ) {
  1473. stop_adc(s);
  1474. s->dma_adc.ossfragshift = val & 0xffff;
  1475. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1476. if (s->dma_adc.ossfragshift < 4)
  1477. s->dma_adc.ossfragshift = 4;
  1478. if (s->dma_adc.ossfragshift > 15)
  1479. s->dma_adc.ossfragshift = 15;
  1480. if (s->dma_adc.ossmaxfrags < 4)
  1481. s->dma_adc.ossmaxfrags = 4;
  1482. if ((ret = prog_dmabuf_adc(s)))
  1483. return ret;
  1484. }
  1485. if (file->f_mode & FMODE_WRITE) {
  1486. stop_dac(s);
  1487. s->dma_dac.ossfragshift = val & 0xffff;
  1488. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1489. if (s->dma_dac.ossfragshift < 4)
  1490. s->dma_dac.ossfragshift = 4;
  1491. if (s->dma_dac.ossfragshift > 15)
  1492. s->dma_dac.ossfragshift = 15;
  1493. if (s->dma_dac.ossmaxfrags < 4)
  1494. s->dma_dac.ossmaxfrags = 4;
  1495. if ((ret = prog_dmabuf_dac(s)))
  1496. return ret;
  1497. }
  1498. return 0;
  1499. case SNDCTL_DSP_SUBDIVIDE:
  1500. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1501. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1502. return -EINVAL;
  1503. if (get_user(val, (int *) arg))
  1504. return -EFAULT;
  1505. if (val != 1 && val != 2 && val != 4)
  1506. return -EINVAL;
  1507. if (file->f_mode & FMODE_READ) {
  1508. stop_adc(s);
  1509. s->dma_adc.subdivision = val;
  1510. if ((ret = prog_dmabuf_adc(s)))
  1511. return ret;
  1512. }
  1513. if (file->f_mode & FMODE_WRITE) {
  1514. stop_dac(s);
  1515. s->dma_dac.subdivision = val;
  1516. if ((ret = prog_dmabuf_dac(s)))
  1517. return ret;
  1518. }
  1519. return 0;
  1520. case SOUND_PCM_READ_RATE:
  1521. return put_user((file->f_mode & FMODE_READ) ?
  1522. s->dma_adc.sample_rate :
  1523. s->dma_dac.sample_rate,
  1524. (int *)arg);
  1525. case SOUND_PCM_READ_CHANNELS:
  1526. if (file->f_mode & FMODE_READ)
  1527. return put_user(s->dma_adc.num_channels, (int *)arg);
  1528. else
  1529. return put_user(s->dma_dac.num_channels, (int *)arg);
  1530. case SOUND_PCM_READ_BITS:
  1531. if (file->f_mode & FMODE_READ)
  1532. return put_user(s->dma_adc.sample_size, (int *)arg);
  1533. else
  1534. return put_user(s->dma_dac.sample_size, (int *)arg);
  1535. case SOUND_PCM_WRITE_FILTER:
  1536. case SNDCTL_DSP_SETSYNCRO:
  1537. case SOUND_PCM_READ_FILTER:
  1538. return -EINVAL;
  1539. }
  1540. return mixdev_ioctl(s->codec, cmd, arg);
  1541. }
  1542. static long
  1543. au1550_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  1544. {
  1545. int ret;
  1546. mutex_lock(&au1550_ac97_mutex);
  1547. ret = au1550_ioctl(file, cmd, arg);
  1548. mutex_unlock(&au1550_ac97_mutex);
  1549. return ret;
  1550. }
  1551. static int
  1552. au1550_open(struct inode *inode, struct file *file)
  1553. {
  1554. int minor = MINOR(inode->i_rdev);
  1555. DECLARE_WAITQUEUE(wait, current);
  1556. struct au1550_state *s = &au1550_state;
  1557. int ret;
  1558. #ifdef DEBUG
  1559. if (file->f_flags & O_NONBLOCK)
  1560. pr_debug("open: non-blocking\n");
  1561. else
  1562. pr_debug("open: blocking\n");
  1563. #endif
  1564. file->private_data = s;
  1565. mutex_lock(&au1550_ac97_mutex);
  1566. /* wait for device to become free */
  1567. mutex_lock(&s->open_mutex);
  1568. while (s->open_mode & file->f_mode) {
  1569. ret = -EBUSY;
  1570. if (file->f_flags & O_NONBLOCK)
  1571. goto out;
  1572. add_wait_queue(&s->open_wait, &wait);
  1573. __set_current_state(TASK_INTERRUPTIBLE);
  1574. mutex_unlock(&s->open_mutex);
  1575. schedule();
  1576. remove_wait_queue(&s->open_wait, &wait);
  1577. set_current_state(TASK_RUNNING);
  1578. ret = -ERESTARTSYS;
  1579. if (signal_pending(current))
  1580. goto out2;
  1581. mutex_lock(&s->open_mutex);
  1582. }
  1583. stop_dac(s);
  1584. stop_adc(s);
  1585. if (file->f_mode & FMODE_READ) {
  1586. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
  1587. s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
  1588. s->dma_adc.num_channels = 1;
  1589. s->dma_adc.sample_size = 8;
  1590. set_adc_rate(s, 8000);
  1591. if ((minor & 0xf) == SND_DEV_DSP16)
  1592. s->dma_adc.sample_size = 16;
  1593. }
  1594. if (file->f_mode & FMODE_WRITE) {
  1595. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
  1596. s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
  1597. s->dma_dac.num_channels = 1;
  1598. s->dma_dac.sample_size = 8;
  1599. set_dac_rate(s, 8000);
  1600. if ((minor & 0xf) == SND_DEV_DSP16)
  1601. s->dma_dac.sample_size = 16;
  1602. }
  1603. if (file->f_mode & FMODE_READ) {
  1604. if ((ret = prog_dmabuf_adc(s)))
  1605. goto out;
  1606. }
  1607. if (file->f_mode & FMODE_WRITE) {
  1608. if ((ret = prog_dmabuf_dac(s)))
  1609. goto out;
  1610. }
  1611. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1612. mutex_init(&s->sem);
  1613. ret = 0;
  1614. out:
  1615. mutex_unlock(&s->open_mutex);
  1616. out2:
  1617. mutex_unlock(&au1550_ac97_mutex);
  1618. return ret;
  1619. }
  1620. static int
  1621. au1550_release(struct inode *inode, struct file *file)
  1622. {
  1623. struct au1550_state *s = file->private_data;
  1624. mutex_lock(&au1550_ac97_mutex);
  1625. if (file->f_mode & FMODE_WRITE) {
  1626. mutex_unlock(&au1550_ac97_mutex);
  1627. drain_dac(s, file->f_flags & O_NONBLOCK);
  1628. mutex_lock(&au1550_ac97_mutex);
  1629. }
  1630. mutex_lock(&s->open_mutex);
  1631. if (file->f_mode & FMODE_WRITE) {
  1632. stop_dac(s);
  1633. kfree(s->dma_dac.rawbuf);
  1634. s->dma_dac.rawbuf = NULL;
  1635. }
  1636. if (file->f_mode & FMODE_READ) {
  1637. stop_adc(s);
  1638. kfree(s->dma_adc.rawbuf);
  1639. s->dma_adc.rawbuf = NULL;
  1640. }
  1641. s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
  1642. mutex_unlock(&s->open_mutex);
  1643. wake_up(&s->open_wait);
  1644. mutex_unlock(&au1550_ac97_mutex);
  1645. return 0;
  1646. }
  1647. static /*const */ struct file_operations au1550_audio_fops = {
  1648. .owner = THIS_MODULE,
  1649. .llseek = au1550_llseek,
  1650. .read = au1550_read,
  1651. .write = au1550_write,
  1652. .poll = au1550_poll,
  1653. .unlocked_ioctl = au1550_unlocked_ioctl,
  1654. .mmap = au1550_mmap,
  1655. .open = au1550_open,
  1656. .release = au1550_release,
  1657. };
  1658. MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
  1659. MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
  1660. MODULE_LICENSE("GPL");
  1661. static int __devinit
  1662. au1550_probe(void)
  1663. {
  1664. struct au1550_state *s = &au1550_state;
  1665. int val;
  1666. memset(s, 0, sizeof(struct au1550_state));
  1667. init_waitqueue_head(&s->dma_adc.wait);
  1668. init_waitqueue_head(&s->dma_dac.wait);
  1669. init_waitqueue_head(&s->open_wait);
  1670. mutex_init(&s->open_mutex);
  1671. spin_lock_init(&s->lock);
  1672. s->codec = ac97_alloc_codec();
  1673. if(s->codec == NULL) {
  1674. err("Out of memory");
  1675. return -1;
  1676. }
  1677. s->codec->private_data = s;
  1678. s->codec->id = 0;
  1679. s->codec->codec_read = rdcodec;
  1680. s->codec->codec_write = wrcodec;
  1681. s->codec->codec_wait = waitcodec;
  1682. if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
  1683. 0x30, "Au1550 AC97")) {
  1684. err("AC'97 ports in use");
  1685. }
  1686. /* Allocate the DMA Channels
  1687. */
  1688. if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
  1689. DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
  1690. err("Can't get DAC DMA");
  1691. goto err_dma1;
  1692. }
  1693. au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
  1694. if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
  1695. NUM_DBDMA_DESCRIPTORS) == 0) {
  1696. err("Can't get DAC DMA descriptors");
  1697. goto err_dma1;
  1698. }
  1699. if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
  1700. DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
  1701. err("Can't get ADC DMA");
  1702. goto err_dma2;
  1703. }
  1704. au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
  1705. if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
  1706. NUM_DBDMA_DESCRIPTORS) == 0) {
  1707. err("Can't get ADC DMA descriptors");
  1708. goto err_dma2;
  1709. }
  1710. pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
  1711. /* register devices */
  1712. if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
  1713. goto err_dev1;
  1714. if ((s->codec->dev_mixer =
  1715. register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
  1716. goto err_dev2;
  1717. /* The GPIO for the appropriate PSC was configured by the
  1718. * board specific start up.
  1719. *
  1720. * configure PSC for AC'97
  1721. */
  1722. au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
  1723. au_sync();
  1724. au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
  1725. au_sync();
  1726. /* cold reset the AC'97
  1727. */
  1728. au_writel(PSC_AC97RST_RST, PSC_AC97RST);
  1729. au_sync();
  1730. au1550_delay(10);
  1731. au_writel(0, PSC_AC97RST);
  1732. au_sync();
  1733. /* need to delay around 500msec(bleech) to give
  1734. some CODECs enough time to wakeup */
  1735. au1550_delay(500);
  1736. /* warm reset the AC'97 to start the bitclk
  1737. */
  1738. au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
  1739. au_sync();
  1740. udelay(100);
  1741. au_writel(0, PSC_AC97RST);
  1742. au_sync();
  1743. /* Enable PSC
  1744. */
  1745. au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
  1746. au_sync();
  1747. /* Wait for PSC ready.
  1748. */
  1749. do {
  1750. val = au_readl(PSC_AC97STAT);
  1751. au_sync();
  1752. } while ((val & PSC_AC97STAT_SR) == 0);
  1753. /* Configure AC97 controller.
  1754. * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
  1755. */
  1756. val = PSC_AC97CFG_SET_LEN(16);
  1757. val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
  1758. /* Enable device so we can at least
  1759. * talk over the AC-link.
  1760. */
  1761. au_writel(val, PSC_AC97CFG);
  1762. au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
  1763. au_sync();
  1764. val |= PSC_AC97CFG_DE_ENABLE;
  1765. au_writel(val, PSC_AC97CFG);
  1766. au_sync();
  1767. /* Wait for Device ready.
  1768. */
  1769. do {
  1770. val = au_readl(PSC_AC97STAT);
  1771. au_sync();
  1772. } while ((val & PSC_AC97STAT_DR) == 0);
  1773. /* codec init */
  1774. if (!ac97_probe_codec(s->codec))
  1775. goto err_dev3;
  1776. s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
  1777. s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
  1778. pr_info("AC'97 Base/Extended ID = %04x/%04x",
  1779. s->codec_base_caps, s->codec_ext_caps);
  1780. if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
  1781. /* codec does not support VRA
  1782. */
  1783. s->no_vra = 1;
  1784. } else if (!vra) {
  1785. /* Boot option says disable VRA
  1786. */
  1787. u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  1788. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1789. ac97_extstat & ~AC97_EXTSTAT_VRA);
  1790. s->no_vra = 1;
  1791. }
  1792. if (s->no_vra)
  1793. pr_info("no VRA, interpolating and decimating");
  1794. /* set mic to be the recording source */
  1795. val = SOUND_MASK_MIC;
  1796. mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
  1797. (unsigned long) &val);
  1798. return 0;
  1799. err_dev3:
  1800. unregister_sound_mixer(s->codec->dev_mixer);
  1801. err_dev2:
  1802. unregister_sound_dsp(s->dev_audio);
  1803. err_dev1:
  1804. au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
  1805. err_dma2:
  1806. au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
  1807. err_dma1:
  1808. release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
  1809. ac97_release_codec(s->codec);
  1810. return -1;
  1811. }
  1812. static void __devinit
  1813. au1550_remove(void)
  1814. {
  1815. struct au1550_state *s = &au1550_state;
  1816. if (!s)
  1817. return;
  1818. synchronize_irq();
  1819. au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
  1820. au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
  1821. release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
  1822. unregister_sound_dsp(s->dev_audio);
  1823. unregister_sound_mixer(s->codec->dev_mixer);
  1824. ac97_release_codec(s->codec);
  1825. }
  1826. static int __init
  1827. init_au1550(void)
  1828. {
  1829. return au1550_probe();
  1830. }
  1831. static void __exit
  1832. cleanup_au1550(void)
  1833. {
  1834. au1550_remove();
  1835. }
  1836. module_init(init_au1550);
  1837. module_exit(cleanup_au1550);
  1838. #ifndef MODULE
  1839. static int __init
  1840. au1550_setup(char *options)
  1841. {
  1842. char *this_opt;
  1843. if (!options || !*options)
  1844. return 0;
  1845. while ((this_opt = strsep(&options, ","))) {
  1846. if (!*this_opt)
  1847. continue;
  1848. if (!strncmp(this_opt, "vra", 3)) {
  1849. vra = 1;
  1850. }
  1851. }
  1852. return 1;
  1853. }
  1854. __setup("au1550_audio=", au1550_setup);
  1855. #endif /* MODULE */