s3c2410_wdt.c 14 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/types.h>
  28. #include <linux/timer.h>
  29. #include <linux/miscdevice.h>
  30. #include <linux/watchdog.h>
  31. #include <linux/fs.h>
  32. #include <linux/init.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/clk.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <linux/cpufreq.h>
  39. #include <linux/slab.h>
  40. #include <mach/map.h>
  41. #undef S3C_VA_WATCHDOG
  42. #define S3C_VA_WATCHDOG (0)
  43. #include <plat/regs-watchdog.h>
  44. #define PFX "s3c2410-wdt: "
  45. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  46. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  47. static int nowayout = WATCHDOG_NOWAYOUT;
  48. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  49. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  50. static int soft_noboot;
  51. static int debug;
  52. module_param(tmr_margin, int, 0);
  53. module_param(tmr_atboot, int, 0);
  54. module_param(nowayout, int, 0);
  55. module_param(soft_noboot, int, 0);
  56. module_param(debug, int, 0);
  57. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  58. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  59. MODULE_PARM_DESC(tmr_atboot,
  60. "Watchdog is started at boot time if set to 1, default="
  61. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  62. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  63. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  64. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  65. "0 to reboot (default 0)");
  66. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
  67. static unsigned long open_lock;
  68. static struct device *wdt_dev; /* platform device attached to */
  69. static struct resource *wdt_mem;
  70. static struct resource *wdt_irq;
  71. static struct clk *wdt_clock;
  72. static void __iomem *wdt_base;
  73. static unsigned int wdt_count;
  74. static char expect_close;
  75. static DEFINE_SPINLOCK(wdt_lock);
  76. /* watchdog control routines */
  77. #define DBG(msg...) do { \
  78. if (debug) \
  79. printk(KERN_INFO msg); \
  80. } while (0)
  81. /* functions */
  82. static void s3c2410wdt_keepalive(void)
  83. {
  84. spin_lock(&wdt_lock);
  85. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  86. spin_unlock(&wdt_lock);
  87. }
  88. static void __s3c2410wdt_stop(void)
  89. {
  90. unsigned long wtcon;
  91. wtcon = readl(wdt_base + S3C2410_WTCON);
  92. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  93. writel(wtcon, wdt_base + S3C2410_WTCON);
  94. }
  95. static void s3c2410wdt_stop(void)
  96. {
  97. spin_lock(&wdt_lock);
  98. __s3c2410wdt_stop();
  99. spin_unlock(&wdt_lock);
  100. }
  101. static void s3c2410wdt_start(void)
  102. {
  103. unsigned long wtcon;
  104. spin_lock(&wdt_lock);
  105. __s3c2410wdt_stop();
  106. wtcon = readl(wdt_base + S3C2410_WTCON);
  107. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  108. if (soft_noboot) {
  109. wtcon |= S3C2410_WTCON_INTEN;
  110. wtcon &= ~S3C2410_WTCON_RSTEN;
  111. } else {
  112. wtcon &= ~S3C2410_WTCON_INTEN;
  113. wtcon |= S3C2410_WTCON_RSTEN;
  114. }
  115. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  116. __func__, wdt_count, wtcon);
  117. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  118. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  119. writel(wtcon, wdt_base + S3C2410_WTCON);
  120. spin_unlock(&wdt_lock);
  121. }
  122. static inline int s3c2410wdt_is_running(void)
  123. {
  124. return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
  125. }
  126. static int s3c2410wdt_set_heartbeat(int timeout)
  127. {
  128. unsigned long freq = clk_get_rate(wdt_clock);
  129. unsigned int count;
  130. unsigned int divisor = 1;
  131. unsigned long wtcon;
  132. if (timeout < 1)
  133. return -EINVAL;
  134. freq /= 128;
  135. count = timeout * freq;
  136. DBG("%s: count=%d, timeout=%d, freq=%lu\n",
  137. __func__, count, timeout, freq);
  138. /* if the count is bigger than the watchdog register,
  139. then work out what we need to do (and if) we can
  140. actually make this value
  141. */
  142. if (count >= 0x10000) {
  143. for (divisor = 1; divisor <= 0x100; divisor++) {
  144. if ((count / divisor) < 0x10000)
  145. break;
  146. }
  147. if ((count / divisor) >= 0x10000) {
  148. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  149. return -EINVAL;
  150. }
  151. }
  152. tmr_margin = timeout;
  153. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  154. __func__, timeout, divisor, count, count/divisor);
  155. count /= divisor;
  156. wdt_count = count;
  157. /* update the pre-scaler */
  158. wtcon = readl(wdt_base + S3C2410_WTCON);
  159. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  160. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  161. writel(count, wdt_base + S3C2410_WTDAT);
  162. writel(wtcon, wdt_base + S3C2410_WTCON);
  163. return 0;
  164. }
  165. /*
  166. * /dev/watchdog handling
  167. */
  168. static int s3c2410wdt_open(struct inode *inode, struct file *file)
  169. {
  170. if (test_and_set_bit(0, &open_lock))
  171. return -EBUSY;
  172. if (nowayout)
  173. __module_get(THIS_MODULE);
  174. expect_close = 0;
  175. /* start the timer */
  176. s3c2410wdt_start();
  177. return nonseekable_open(inode, file);
  178. }
  179. static int s3c2410wdt_release(struct inode *inode, struct file *file)
  180. {
  181. /*
  182. * Shut off the timer.
  183. * Lock it in if it's a module and we set nowayout
  184. */
  185. if (expect_close == 42)
  186. s3c2410wdt_stop();
  187. else {
  188. dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
  189. s3c2410wdt_keepalive();
  190. }
  191. expect_close = 0;
  192. clear_bit(0, &open_lock);
  193. return 0;
  194. }
  195. static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
  196. size_t len, loff_t *ppos)
  197. {
  198. /*
  199. * Refresh the timer.
  200. */
  201. if (len) {
  202. if (!nowayout) {
  203. size_t i;
  204. /* In case it was set long ago */
  205. expect_close = 0;
  206. for (i = 0; i != len; i++) {
  207. char c;
  208. if (get_user(c, data + i))
  209. return -EFAULT;
  210. if (c == 'V')
  211. expect_close = 42;
  212. }
  213. }
  214. s3c2410wdt_keepalive();
  215. }
  216. return len;
  217. }
  218. #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
  219. static const struct watchdog_info s3c2410_wdt_ident = {
  220. .options = OPTIONS,
  221. .firmware_version = 0,
  222. .identity = "S3C2410 Watchdog",
  223. };
  224. static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
  225. unsigned long arg)
  226. {
  227. void __user *argp = (void __user *)arg;
  228. int __user *p = argp;
  229. int new_margin;
  230. switch (cmd) {
  231. case WDIOC_GETSUPPORT:
  232. return copy_to_user(argp, &s3c2410_wdt_ident,
  233. sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
  234. case WDIOC_GETSTATUS:
  235. case WDIOC_GETBOOTSTATUS:
  236. return put_user(0, p);
  237. case WDIOC_KEEPALIVE:
  238. s3c2410wdt_keepalive();
  239. return 0;
  240. case WDIOC_SETTIMEOUT:
  241. if (get_user(new_margin, p))
  242. return -EFAULT;
  243. if (s3c2410wdt_set_heartbeat(new_margin))
  244. return -EINVAL;
  245. s3c2410wdt_keepalive();
  246. return put_user(tmr_margin, p);
  247. case WDIOC_GETTIMEOUT:
  248. return put_user(tmr_margin, p);
  249. default:
  250. return -ENOTTY;
  251. }
  252. }
  253. /* kernel interface */
  254. static const struct file_operations s3c2410wdt_fops = {
  255. .owner = THIS_MODULE,
  256. .llseek = no_llseek,
  257. .write = s3c2410wdt_write,
  258. .unlocked_ioctl = s3c2410wdt_ioctl,
  259. .open = s3c2410wdt_open,
  260. .release = s3c2410wdt_release,
  261. };
  262. static struct miscdevice s3c2410wdt_miscdev = {
  263. .minor = WATCHDOG_MINOR,
  264. .name = "watchdog",
  265. .fops = &s3c2410wdt_fops,
  266. };
  267. /* interrupt handler code */
  268. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  269. {
  270. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  271. s3c2410wdt_keepalive();
  272. return IRQ_HANDLED;
  273. }
  274. #ifdef CONFIG_CPU_FREQ
  275. static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
  276. unsigned long val, void *data)
  277. {
  278. int ret;
  279. if (!s3c2410wdt_is_running())
  280. goto done;
  281. if (val == CPUFREQ_PRECHANGE) {
  282. /* To ensure that over the change we don't cause the
  283. * watchdog to trigger, we perform an keep-alive if
  284. * the watchdog is running.
  285. */
  286. s3c2410wdt_keepalive();
  287. } else if (val == CPUFREQ_POSTCHANGE) {
  288. s3c2410wdt_stop();
  289. ret = s3c2410wdt_set_heartbeat(tmr_margin);
  290. if (ret >= 0)
  291. s3c2410wdt_start();
  292. else
  293. goto err;
  294. }
  295. done:
  296. return 0;
  297. err:
  298. dev_err(wdt_dev, "cannot set new value for timeout %d\n", tmr_margin);
  299. return ret;
  300. }
  301. static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
  302. .notifier_call = s3c2410wdt_cpufreq_transition,
  303. };
  304. static inline int s3c2410wdt_cpufreq_register(void)
  305. {
  306. return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
  307. CPUFREQ_TRANSITION_NOTIFIER);
  308. }
  309. static inline void s3c2410wdt_cpufreq_deregister(void)
  310. {
  311. cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
  312. CPUFREQ_TRANSITION_NOTIFIER);
  313. }
  314. #else
  315. static inline int s3c2410wdt_cpufreq_register(void)
  316. {
  317. return 0;
  318. }
  319. static inline void s3c2410wdt_cpufreq_deregister(void)
  320. {
  321. }
  322. #endif
  323. /* device interface */
  324. static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
  325. {
  326. struct device *dev;
  327. unsigned int wtcon;
  328. int started = 0;
  329. int ret;
  330. int size;
  331. DBG("%s: probe=%p\n", __func__, pdev);
  332. dev = &pdev->dev;
  333. wdt_dev = &pdev->dev;
  334. /* get the memory region for the watchdog timer */
  335. wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  336. if (wdt_mem == NULL) {
  337. dev_err(dev, "no memory resource specified\n");
  338. return -ENOENT;
  339. }
  340. size = resource_size(wdt_mem);
  341. if (!request_mem_region(wdt_mem->start, size, pdev->name)) {
  342. dev_err(dev, "failed to get memory region\n");
  343. return -EBUSY;
  344. }
  345. wdt_base = ioremap(wdt_mem->start, size);
  346. if (wdt_base == NULL) {
  347. dev_err(dev, "failed to ioremap() region\n");
  348. ret = -EINVAL;
  349. goto err_req;
  350. }
  351. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  352. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  353. if (wdt_irq == NULL) {
  354. dev_err(dev, "no irq resource specified\n");
  355. ret = -ENOENT;
  356. goto err_map;
  357. }
  358. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  359. if (ret != 0) {
  360. dev_err(dev, "failed to install irq (%d)\n", ret);
  361. goto err_map;
  362. }
  363. wdt_clock = clk_get(&pdev->dev, "watchdog");
  364. if (IS_ERR(wdt_clock)) {
  365. dev_err(dev, "failed to find watchdog clock source\n");
  366. ret = PTR_ERR(wdt_clock);
  367. goto err_irq;
  368. }
  369. clk_enable(wdt_clock);
  370. if (s3c2410wdt_cpufreq_register() < 0) {
  371. printk(KERN_ERR PFX "failed to register cpufreq\n");
  372. goto err_clk;
  373. }
  374. /* see if we can actually set the requested timer margin, and if
  375. * not, try the default value */
  376. if (s3c2410wdt_set_heartbeat(tmr_margin)) {
  377. started = s3c2410wdt_set_heartbeat(
  378. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  379. if (started == 0)
  380. dev_info(dev,
  381. "tmr_margin value out of range, default %d used\n",
  382. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  383. else
  384. dev_info(dev, "default timer value is out of range, "
  385. "cannot start\n");
  386. }
  387. ret = misc_register(&s3c2410wdt_miscdev);
  388. if (ret) {
  389. dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
  390. WATCHDOG_MINOR, ret);
  391. goto err_cpufreq;
  392. }
  393. if (tmr_atboot && started == 0) {
  394. dev_info(dev, "starting watchdog timer\n");
  395. s3c2410wdt_start();
  396. } else if (!tmr_atboot) {
  397. /* if we're not enabling the watchdog, then ensure it is
  398. * disabled if it has been left running from the bootloader
  399. * or other source */
  400. s3c2410wdt_stop();
  401. }
  402. /* print out a statement of readiness */
  403. wtcon = readl(wdt_base + S3C2410_WTCON);
  404. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  405. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  406. (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
  407. (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
  408. return 0;
  409. err_cpufreq:
  410. s3c2410wdt_cpufreq_deregister();
  411. err_clk:
  412. clk_disable(wdt_clock);
  413. clk_put(wdt_clock);
  414. err_irq:
  415. free_irq(wdt_irq->start, pdev);
  416. err_map:
  417. iounmap(wdt_base);
  418. err_req:
  419. release_mem_region(wdt_mem->start, size);
  420. wdt_mem = NULL;
  421. return ret;
  422. }
  423. static int __devexit s3c2410wdt_remove(struct platform_device *dev)
  424. {
  425. misc_deregister(&s3c2410wdt_miscdev);
  426. s3c2410wdt_cpufreq_deregister();
  427. clk_disable(wdt_clock);
  428. clk_put(wdt_clock);
  429. wdt_clock = NULL;
  430. free_irq(wdt_irq->start, dev);
  431. wdt_irq = NULL;
  432. iounmap(wdt_base);
  433. release_mem_region(wdt_mem->start, resource_size(wdt_mem));
  434. wdt_mem = NULL;
  435. return 0;
  436. }
  437. static void s3c2410wdt_shutdown(struct platform_device *dev)
  438. {
  439. s3c2410wdt_stop();
  440. }
  441. #ifdef CONFIG_PM
  442. static unsigned long wtcon_save;
  443. static unsigned long wtdat_save;
  444. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  445. {
  446. /* Save watchdog state, and turn it off. */
  447. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  448. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  449. /* Note that WTCNT doesn't need to be saved. */
  450. s3c2410wdt_stop();
  451. return 0;
  452. }
  453. static int s3c2410wdt_resume(struct platform_device *dev)
  454. {
  455. /* Restore watchdog state. */
  456. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  457. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  458. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  459. printk(KERN_INFO PFX "watchdog %sabled\n",
  460. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  461. return 0;
  462. }
  463. #else
  464. #define s3c2410wdt_suspend NULL
  465. #define s3c2410wdt_resume NULL
  466. #endif /* CONFIG_PM */
  467. static struct platform_driver s3c2410wdt_driver = {
  468. .probe = s3c2410wdt_probe,
  469. .remove = __devexit_p(s3c2410wdt_remove),
  470. .shutdown = s3c2410wdt_shutdown,
  471. .suspend = s3c2410wdt_suspend,
  472. .resume = s3c2410wdt_resume,
  473. .driver = {
  474. .owner = THIS_MODULE,
  475. .name = "s3c2410-wdt",
  476. },
  477. };
  478. static char banner[] __initdata =
  479. KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
  480. static int __init watchdog_init(void)
  481. {
  482. printk(banner);
  483. return platform_driver_register(&s3c2410wdt_driver);
  484. }
  485. static void __exit watchdog_exit(void)
  486. {
  487. platform_driver_unregister(&s3c2410wdt_driver);
  488. }
  489. module_init(watchdog_init);
  490. module_exit(watchdog_exit);
  491. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  492. "Dimitry Andric <dimitry.andric@tomtom.com>");
  493. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  494. MODULE_LICENSE("GPL");
  495. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  496. MODULE_ALIAS("platform:s3c2410-wdt");