langwell_otg.c 60 KB

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  1. /*
  2. * Intel Langwell USB OTG transceiver driver
  3. * Copyright (C) 2008 - 2010, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. /* This driver helps to switch Langwell OTG controller function between host
  20. * and peripheral. It works with EHCI driver and Langwell client controller
  21. * driver together.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/pci.h>
  26. #include <linux/errno.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/kernel.h>
  29. #include <linux/device.h>
  30. #include <linux/moduleparam.h>
  31. #include <linux/usb/ch9.h>
  32. #include <linux/usb/gadget.h>
  33. #include <linux/usb.h>
  34. #include <linux/usb/otg.h>
  35. #include <linux/usb/hcd.h>
  36. #include <linux/notifier.h>
  37. #include <linux/delay.h>
  38. #include <asm/intel_scu_ipc.h>
  39. #include <linux/usb/langwell_otg.h>
  40. #define DRIVER_DESC "Intel Langwell USB OTG transceiver driver"
  41. #define DRIVER_VERSION "July 10, 2010"
  42. MODULE_DESCRIPTION(DRIVER_DESC);
  43. MODULE_AUTHOR("Henry Yuan <hang.yuan@intel.com>, Hao Wu <hao.wu@intel.com>");
  44. MODULE_VERSION(DRIVER_VERSION);
  45. MODULE_LICENSE("GPL");
  46. static const char driver_name[] = "langwell_otg";
  47. static int langwell_otg_probe(struct pci_dev *pdev,
  48. const struct pci_device_id *id);
  49. static void langwell_otg_remove(struct pci_dev *pdev);
  50. static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message);
  51. static int langwell_otg_resume(struct pci_dev *pdev);
  52. static int langwell_otg_set_host(struct otg_transceiver *otg,
  53. struct usb_bus *host);
  54. static int langwell_otg_set_peripheral(struct otg_transceiver *otg,
  55. struct usb_gadget *gadget);
  56. static int langwell_otg_start_srp(struct otg_transceiver *otg);
  57. static const struct pci_device_id pci_ids[] = {{
  58. .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
  59. .class_mask = ~0,
  60. .vendor = 0x8086,
  61. .device = 0x0811,
  62. .subvendor = PCI_ANY_ID,
  63. .subdevice = PCI_ANY_ID,
  64. }, { /* end: all zeroes */ }
  65. };
  66. static struct pci_driver otg_pci_driver = {
  67. .name = (char *) driver_name,
  68. .id_table = pci_ids,
  69. .probe = langwell_otg_probe,
  70. .remove = langwell_otg_remove,
  71. .suspend = langwell_otg_suspend,
  72. .resume = langwell_otg_resume,
  73. };
  74. static const char *state_string(enum usb_otg_state state)
  75. {
  76. switch (state) {
  77. case OTG_STATE_A_IDLE:
  78. return "a_idle";
  79. case OTG_STATE_A_WAIT_VRISE:
  80. return "a_wait_vrise";
  81. case OTG_STATE_A_WAIT_BCON:
  82. return "a_wait_bcon";
  83. case OTG_STATE_A_HOST:
  84. return "a_host";
  85. case OTG_STATE_A_SUSPEND:
  86. return "a_suspend";
  87. case OTG_STATE_A_PERIPHERAL:
  88. return "a_peripheral";
  89. case OTG_STATE_A_WAIT_VFALL:
  90. return "a_wait_vfall";
  91. case OTG_STATE_A_VBUS_ERR:
  92. return "a_vbus_err";
  93. case OTG_STATE_B_IDLE:
  94. return "b_idle";
  95. case OTG_STATE_B_SRP_INIT:
  96. return "b_srp_init";
  97. case OTG_STATE_B_PERIPHERAL:
  98. return "b_peripheral";
  99. case OTG_STATE_B_WAIT_ACON:
  100. return "b_wait_acon";
  101. case OTG_STATE_B_HOST:
  102. return "b_host";
  103. default:
  104. return "UNDEFINED";
  105. }
  106. }
  107. /* HSM timers */
  108. static inline struct langwell_otg_timer *otg_timer_initializer
  109. (void (*function)(unsigned long), unsigned long expires, unsigned long data)
  110. {
  111. struct langwell_otg_timer *timer;
  112. timer = kmalloc(sizeof(struct langwell_otg_timer), GFP_KERNEL);
  113. if (timer == NULL)
  114. return timer;
  115. timer->function = function;
  116. timer->expires = expires;
  117. timer->data = data;
  118. return timer;
  119. }
  120. static struct langwell_otg_timer *a_wait_vrise_tmr, *a_aidl_bdis_tmr,
  121. *b_se0_srp_tmr, *b_srp_init_tmr;
  122. static struct list_head active_timers;
  123. static struct langwell_otg *the_transceiver;
  124. /* host/client notify transceiver when event affects HNP state */
  125. void langwell_update_transceiver(void)
  126. {
  127. struct langwell_otg *lnw = the_transceiver;
  128. dev_dbg(lnw->dev, "transceiver is updated\n");
  129. if (!lnw->qwork)
  130. return ;
  131. queue_work(lnw->qwork, &lnw->work);
  132. }
  133. EXPORT_SYMBOL(langwell_update_transceiver);
  134. static int langwell_otg_set_host(struct otg_transceiver *otg,
  135. struct usb_bus *host)
  136. {
  137. otg->host = host;
  138. return 0;
  139. }
  140. static int langwell_otg_set_peripheral(struct otg_transceiver *otg,
  141. struct usb_gadget *gadget)
  142. {
  143. otg->gadget = gadget;
  144. return 0;
  145. }
  146. static int langwell_otg_set_power(struct otg_transceiver *otg,
  147. unsigned mA)
  148. {
  149. return 0;
  150. }
  151. /* A-device drives vbus, controlled through IPC commands */
  152. static int langwell_otg_set_vbus(struct otg_transceiver *otg, bool enabled)
  153. {
  154. struct langwell_otg *lnw = the_transceiver;
  155. u8 sub_id;
  156. dev_dbg(lnw->dev, "%s <--- %s\n", __func__, enabled ? "on" : "off");
  157. if (enabled)
  158. sub_id = 0x8; /* Turn on the VBus */
  159. else
  160. sub_id = 0x9; /* Turn off the VBus */
  161. if (intel_scu_ipc_simple_command(0xef, sub_id)) {
  162. dev_dbg(lnw->dev, "Failed to set Vbus via IPC commands\n");
  163. return -EBUSY;
  164. }
  165. dev_dbg(lnw->dev, "%s --->\n", __func__);
  166. return 0;
  167. }
  168. /* charge vbus or discharge vbus through a resistor to ground */
  169. static void langwell_otg_chrg_vbus(int on)
  170. {
  171. struct langwell_otg *lnw = the_transceiver;
  172. u32 val;
  173. val = readl(lnw->iotg.base + CI_OTGSC);
  174. if (on)
  175. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VC,
  176. lnw->iotg.base + CI_OTGSC);
  177. else
  178. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VD,
  179. lnw->iotg.base + CI_OTGSC);
  180. }
  181. /* Start SRP */
  182. static int langwell_otg_start_srp(struct otg_transceiver *otg)
  183. {
  184. struct langwell_otg *lnw = the_transceiver;
  185. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  186. u32 val;
  187. dev_dbg(lnw->dev, "%s --->\n", __func__);
  188. val = readl(iotg->base + CI_OTGSC);
  189. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HADP,
  190. iotg->base + CI_OTGSC);
  191. /* Check if the data plus is finished or not */
  192. msleep(8);
  193. val = readl(iotg->base + CI_OTGSC);
  194. if (val & (OTGSC_HADP | OTGSC_DP))
  195. dev_dbg(lnw->dev, "DataLine SRP Error\n");
  196. /* Disable interrupt - b_sess_vld */
  197. val = readl(iotg->base + CI_OTGSC);
  198. val &= (~(OTGSC_BSVIE | OTGSC_BSEIE));
  199. writel(val, iotg->base + CI_OTGSC);
  200. /* Start VBus SRP, drive vbus to generate VBus pulse */
  201. iotg->otg.set_vbus(&iotg->otg, true);
  202. msleep(15);
  203. iotg->otg.set_vbus(&iotg->otg, false);
  204. /* Enable interrupt - b_sess_vld*/
  205. val = readl(iotg->base + CI_OTGSC);
  206. dev_dbg(lnw->dev, "after VBUS pulse otgsc = %x\n", val);
  207. val |= (OTGSC_BSVIE | OTGSC_BSEIE);
  208. writel(val, iotg->base + CI_OTGSC);
  209. /* If Vbus is valid, then update the hsm */
  210. if (val & OTGSC_BSV) {
  211. dev_dbg(lnw->dev, "no b_sess_vld interrupt\n");
  212. lnw->iotg.hsm.b_sess_vld = 1;
  213. langwell_update_transceiver();
  214. }
  215. dev_dbg(lnw->dev, "%s <---\n", __func__);
  216. return 0;
  217. }
  218. /* stop SOF via bus_suspend */
  219. static void langwell_otg_loc_sof(int on)
  220. {
  221. struct langwell_otg *lnw = the_transceiver;
  222. struct usb_hcd *hcd;
  223. int err;
  224. dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "suspend" : "resume");
  225. hcd = bus_to_hcd(lnw->iotg.otg.host);
  226. if (on)
  227. err = hcd->driver->bus_resume(hcd);
  228. else
  229. err = hcd->driver->bus_suspend(hcd);
  230. if (err)
  231. dev_dbg(lnw->dev, "Fail to resume/suspend USB bus - %d\n", err);
  232. dev_dbg(lnw->dev, "%s <---\n", __func__);
  233. }
  234. static int langwell_otg_check_otgsc(void)
  235. {
  236. struct langwell_otg *lnw = the_transceiver;
  237. u32 otgsc, usbcfg;
  238. dev_dbg(lnw->dev, "check sync OTGSC and USBCFG registers\n");
  239. otgsc = readl(lnw->iotg.base + CI_OTGSC);
  240. usbcfg = readl(lnw->usbcfg);
  241. dev_dbg(lnw->dev, "OTGSC = %08x, USBCFG = %08x\n",
  242. otgsc, usbcfg);
  243. dev_dbg(lnw->dev, "OTGSC_AVV = %d\n", !!(otgsc & OTGSC_AVV));
  244. dev_dbg(lnw->dev, "USBCFG.VBUSVAL = %d\n",
  245. !!(usbcfg & USBCFG_VBUSVAL));
  246. dev_dbg(lnw->dev, "OTGSC_ASV = %d\n", !!(otgsc & OTGSC_ASV));
  247. dev_dbg(lnw->dev, "USBCFG.AVALID = %d\n",
  248. !!(usbcfg & USBCFG_AVALID));
  249. dev_dbg(lnw->dev, "OTGSC_BSV = %d\n", !!(otgsc & OTGSC_BSV));
  250. dev_dbg(lnw->dev, "USBCFG.BVALID = %d\n",
  251. !!(usbcfg & USBCFG_BVALID));
  252. dev_dbg(lnw->dev, "OTGSC_BSE = %d\n", !!(otgsc & OTGSC_BSE));
  253. dev_dbg(lnw->dev, "USBCFG.SESEND = %d\n",
  254. !!(usbcfg & USBCFG_SESEND));
  255. /* Check USBCFG VBusValid/AValid/BValid/SessEnd */
  256. if (!!(otgsc & OTGSC_AVV) ^ !!(usbcfg & USBCFG_VBUSVAL)) {
  257. dev_dbg(lnw->dev, "OTGSC.AVV != USBCFG.VBUSVAL\n");
  258. goto err;
  259. }
  260. if (!!(otgsc & OTGSC_ASV) ^ !!(usbcfg & USBCFG_AVALID)) {
  261. dev_dbg(lnw->dev, "OTGSC.ASV != USBCFG.AVALID\n");
  262. goto err;
  263. }
  264. if (!!(otgsc & OTGSC_BSV) ^ !!(usbcfg & USBCFG_BVALID)) {
  265. dev_dbg(lnw->dev, "OTGSC.BSV != USBCFG.BVALID\n");
  266. goto err;
  267. }
  268. if (!!(otgsc & OTGSC_BSE) ^ !!(usbcfg & USBCFG_SESEND)) {
  269. dev_dbg(lnw->dev, "OTGSC.BSE != USBCFG.SESSEN\n");
  270. goto err;
  271. }
  272. dev_dbg(lnw->dev, "OTGSC and USBCFG are synced\n");
  273. return 0;
  274. err:
  275. dev_warn(lnw->dev, "OTGSC isn't equal to USBCFG\n");
  276. return -EPIPE;
  277. }
  278. static void langwell_otg_phy_low_power(int on)
  279. {
  280. struct langwell_otg *lnw = the_transceiver;
  281. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  282. u8 val, phcd;
  283. int retval;
  284. dev_dbg(lnw->dev, "%s ---> %s mode\n",
  285. __func__, on ? "Low power" : "Normal");
  286. phcd = 0x40;
  287. val = readb(iotg->base + CI_HOSTPC1 + 2);
  288. if (on) {
  289. /* Due to hardware issue, after set PHCD, sync will failed
  290. * between USBCFG and OTGSC, so before set PHCD, check if
  291. * sync is in process now. If the answer is "yes", then do
  292. * not touch PHCD bit */
  293. retval = langwell_otg_check_otgsc();
  294. if (retval) {
  295. dev_dbg(lnw->dev, "Skip PHCD programming..\n");
  296. return ;
  297. }
  298. writeb(val | phcd, iotg->base + CI_HOSTPC1 + 2);
  299. } else
  300. writeb(val & ~phcd, iotg->base + CI_HOSTPC1 + 2);
  301. dev_dbg(lnw->dev, "%s <--- done\n", __func__);
  302. }
  303. /* After drv vbus, add 5 ms delay to set PHCD */
  304. static void langwell_otg_phy_low_power_wait(int on)
  305. {
  306. struct langwell_otg *lnw = the_transceiver;
  307. dev_dbg(lnw->dev, "add 5ms delay before programing PHCD\n");
  308. mdelay(5);
  309. langwell_otg_phy_low_power(on);
  310. }
  311. /* Enable/Disable OTG interrupt */
  312. static void langwell_otg_intr(int on)
  313. {
  314. struct langwell_otg *lnw = the_transceiver;
  315. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  316. u32 val;
  317. dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
  318. val = readl(iotg->base + CI_OTGSC);
  319. /* OTGSC_INT_MASK doesn't contains 1msInt */
  320. if (on) {
  321. val = val | (OTGSC_INT_MASK);
  322. writel(val, iotg->base + CI_OTGSC);
  323. } else {
  324. val = val & ~(OTGSC_INT_MASK);
  325. writel(val, iotg->base + CI_OTGSC);
  326. }
  327. dev_dbg(lnw->dev, "%s <---\n", __func__);
  328. }
  329. /* set HAAR: Hardware Assist Auto-Reset */
  330. static void langwell_otg_HAAR(int on)
  331. {
  332. struct langwell_otg *lnw = the_transceiver;
  333. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  334. u32 val;
  335. dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
  336. val = readl(iotg->base + CI_OTGSC);
  337. if (on)
  338. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HAAR,
  339. iotg->base + CI_OTGSC);
  340. else
  341. writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HAAR,
  342. iotg->base + CI_OTGSC);
  343. dev_dbg(lnw->dev, "%s <---\n", __func__);
  344. }
  345. /* set HABA: Hardware Assist B-Disconnect to A-Connect */
  346. static void langwell_otg_HABA(int on)
  347. {
  348. struct langwell_otg *lnw = the_transceiver;
  349. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  350. u32 val;
  351. dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
  352. val = readl(iotg->base + CI_OTGSC);
  353. if (on)
  354. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HABA,
  355. iotg->base + CI_OTGSC);
  356. else
  357. writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HABA,
  358. iotg->base + CI_OTGSC);
  359. dev_dbg(lnw->dev, "%s <---\n", __func__);
  360. }
  361. static int langwell_otg_check_se0_srp(int on)
  362. {
  363. struct langwell_otg *lnw = the_transceiver;
  364. int delay_time = TB_SE0_SRP * 10;
  365. u32 val;
  366. dev_dbg(lnw->dev, "%s --->\n", __func__);
  367. do {
  368. udelay(100);
  369. if (!delay_time--)
  370. break;
  371. val = readl(lnw->iotg.base + CI_PORTSC1);
  372. val &= PORTSC_LS;
  373. } while (!val);
  374. dev_dbg(lnw->dev, "%s <---\n", __func__);
  375. return val;
  376. }
  377. /* The timeout callback function to set time out bit */
  378. static void set_tmout(unsigned long indicator)
  379. {
  380. *(int *)indicator = 1;
  381. }
  382. void langwell_otg_nsf_msg(unsigned long indicator)
  383. {
  384. struct langwell_otg *lnw = the_transceiver;
  385. switch (indicator) {
  386. case 2:
  387. case 4:
  388. case 6:
  389. case 7:
  390. dev_warn(lnw->dev,
  391. "OTG:NSF-%lu - deivce not responding\n", indicator);
  392. break;
  393. case 3:
  394. dev_warn(lnw->dev,
  395. "OTG:NSF-%lu - deivce not supported\n", indicator);
  396. break;
  397. default:
  398. dev_warn(lnw->dev, "Do not have this kind of NSF\n");
  399. break;
  400. }
  401. }
  402. /* Initialize timers */
  403. static int langwell_otg_init_timers(struct otg_hsm *hsm)
  404. {
  405. /* HSM used timers */
  406. a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
  407. (unsigned long)&hsm->a_wait_vrise_tmout);
  408. if (a_wait_vrise_tmr == NULL)
  409. return -ENOMEM;
  410. a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
  411. (unsigned long)&hsm->a_aidl_bdis_tmout);
  412. if (a_aidl_bdis_tmr == NULL)
  413. return -ENOMEM;
  414. b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
  415. (unsigned long)&hsm->b_se0_srp);
  416. if (b_se0_srp_tmr == NULL)
  417. return -ENOMEM;
  418. b_srp_init_tmr = otg_timer_initializer(&set_tmout, TB_SRP_INIT,
  419. (unsigned long)&hsm->b_srp_init_tmout);
  420. if (b_srp_init_tmr == NULL)
  421. return -ENOMEM;
  422. return 0;
  423. }
  424. /* Free timers */
  425. static void langwell_otg_free_timers(void)
  426. {
  427. kfree(a_wait_vrise_tmr);
  428. kfree(a_aidl_bdis_tmr);
  429. kfree(b_se0_srp_tmr);
  430. kfree(b_srp_init_tmr);
  431. }
  432. /* The timeout callback function to set time out bit */
  433. static void langwell_otg_timer_fn(unsigned long indicator)
  434. {
  435. struct langwell_otg *lnw = the_transceiver;
  436. *(int *)indicator = 1;
  437. dev_dbg(lnw->dev, "kernel timer - timeout\n");
  438. langwell_update_transceiver();
  439. }
  440. /* kernel timer used instead of HW based interrupt */
  441. static void langwell_otg_add_ktimer(enum langwell_otg_timer_type timers)
  442. {
  443. struct langwell_otg *lnw = the_transceiver;
  444. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  445. unsigned long j = jiffies;
  446. unsigned long data, time;
  447. switch (timers) {
  448. case TA_WAIT_VRISE_TMR:
  449. iotg->hsm.a_wait_vrise_tmout = 0;
  450. data = (unsigned long)&iotg->hsm.a_wait_vrise_tmout;
  451. time = TA_WAIT_VRISE;
  452. break;
  453. case TA_WAIT_BCON_TMR:
  454. iotg->hsm.a_wait_bcon_tmout = 0;
  455. data = (unsigned long)&iotg->hsm.a_wait_bcon_tmout;
  456. time = TA_WAIT_BCON;
  457. break;
  458. case TA_AIDL_BDIS_TMR:
  459. iotg->hsm.a_aidl_bdis_tmout = 0;
  460. data = (unsigned long)&iotg->hsm.a_aidl_bdis_tmout;
  461. time = TA_AIDL_BDIS;
  462. break;
  463. case TB_ASE0_BRST_TMR:
  464. iotg->hsm.b_ase0_brst_tmout = 0;
  465. data = (unsigned long)&iotg->hsm.b_ase0_brst_tmout;
  466. time = TB_ASE0_BRST;
  467. break;
  468. case TB_SRP_INIT_TMR:
  469. iotg->hsm.b_srp_init_tmout = 0;
  470. data = (unsigned long)&iotg->hsm.b_srp_init_tmout;
  471. time = TB_SRP_INIT;
  472. break;
  473. case TB_SRP_FAIL_TMR:
  474. iotg->hsm.b_srp_fail_tmout = 0;
  475. data = (unsigned long)&iotg->hsm.b_srp_fail_tmout;
  476. time = TB_SRP_FAIL;
  477. break;
  478. case TB_BUS_SUSPEND_TMR:
  479. iotg->hsm.b_bus_suspend_tmout = 0;
  480. data = (unsigned long)&iotg->hsm.b_bus_suspend_tmout;
  481. time = TB_BUS_SUSPEND;
  482. break;
  483. default:
  484. dev_dbg(lnw->dev, "unkown timer, cannot enable it\n");
  485. return;
  486. }
  487. lnw->hsm_timer.data = data;
  488. lnw->hsm_timer.function = langwell_otg_timer_fn;
  489. lnw->hsm_timer.expires = j + time * HZ / 1000; /* milliseconds */
  490. add_timer(&lnw->hsm_timer);
  491. dev_dbg(lnw->dev, "add timer successfully\n");
  492. }
  493. /* Add timer to timer list */
  494. static void langwell_otg_add_timer(void *gtimer)
  495. {
  496. struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer;
  497. struct langwell_otg_timer *tmp_timer;
  498. struct intel_mid_otg_xceiv *iotg = &the_transceiver->iotg;
  499. u32 val32;
  500. /* Check if the timer is already in the active list,
  501. * if so update timer count
  502. */
  503. list_for_each_entry(tmp_timer, &active_timers, list)
  504. if (tmp_timer == timer) {
  505. timer->count = timer->expires;
  506. return;
  507. }
  508. timer->count = timer->expires;
  509. if (list_empty(&active_timers)) {
  510. val32 = readl(iotg->base + CI_OTGSC);
  511. writel(val32 | OTGSC_1MSE, iotg->base + CI_OTGSC);
  512. }
  513. list_add_tail(&timer->list, &active_timers);
  514. }
  515. /* Remove timer from the timer list; clear timeout status */
  516. static void langwell_otg_del_timer(void *gtimer)
  517. {
  518. struct langwell_otg *lnw = the_transceiver;
  519. struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer;
  520. struct langwell_otg_timer *tmp_timer, *del_tmp;
  521. u32 val32;
  522. list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
  523. if (tmp_timer == timer)
  524. list_del(&timer->list);
  525. if (list_empty(&active_timers)) {
  526. val32 = readl(lnw->iotg.base + CI_OTGSC);
  527. writel(val32 & ~OTGSC_1MSE, lnw->iotg.base + CI_OTGSC);
  528. }
  529. }
  530. /* Reduce timer count by 1, and find timeout conditions.*/
  531. static int langwell_otg_tick_timer(u32 *int_sts)
  532. {
  533. struct langwell_otg *lnw = the_transceiver;
  534. struct langwell_otg_timer *tmp_timer, *del_tmp;
  535. int expired = 0;
  536. list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
  537. tmp_timer->count--;
  538. /* check if timer expires */
  539. if (!tmp_timer->count) {
  540. list_del(&tmp_timer->list);
  541. tmp_timer->function(tmp_timer->data);
  542. expired = 1;
  543. }
  544. }
  545. if (list_empty(&active_timers)) {
  546. dev_dbg(lnw->dev, "tick timer: disable 1ms int\n");
  547. *int_sts = *int_sts & ~OTGSC_1MSE;
  548. }
  549. return expired;
  550. }
  551. static void reset_otg(void)
  552. {
  553. struct langwell_otg *lnw = the_transceiver;
  554. int delay_time = 1000;
  555. u32 val;
  556. dev_dbg(lnw->dev, "reseting OTG controller ...\n");
  557. val = readl(lnw->iotg.base + CI_USBCMD);
  558. writel(val | USBCMD_RST, lnw->iotg.base + CI_USBCMD);
  559. do {
  560. udelay(100);
  561. if (!delay_time--)
  562. dev_dbg(lnw->dev, "reset timeout\n");
  563. val = readl(lnw->iotg.base + CI_USBCMD);
  564. val &= USBCMD_RST;
  565. } while (val != 0);
  566. dev_dbg(lnw->dev, "reset done.\n");
  567. }
  568. static void set_host_mode(void)
  569. {
  570. struct langwell_otg *lnw = the_transceiver;
  571. u32 val;
  572. reset_otg();
  573. val = readl(lnw->iotg.base + CI_USBMODE);
  574. val = (val & (~USBMODE_CM)) | USBMODE_HOST;
  575. writel(val, lnw->iotg.base + CI_USBMODE);
  576. }
  577. static void set_client_mode(void)
  578. {
  579. struct langwell_otg *lnw = the_transceiver;
  580. u32 val;
  581. reset_otg();
  582. val = readl(lnw->iotg.base + CI_USBMODE);
  583. val = (val & (~USBMODE_CM)) | USBMODE_DEVICE;
  584. writel(val, lnw->iotg.base + CI_USBMODE);
  585. }
  586. static void init_hsm(void)
  587. {
  588. struct langwell_otg *lnw = the_transceiver;
  589. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  590. u32 val32;
  591. /* read OTGSC after reset */
  592. val32 = readl(lnw->iotg.base + CI_OTGSC);
  593. dev_dbg(lnw->dev, "%s: OTGSC init value = 0x%x\n", __func__, val32);
  594. /* set init state */
  595. if (val32 & OTGSC_ID) {
  596. iotg->hsm.id = 1;
  597. iotg->otg.default_a = 0;
  598. set_client_mode();
  599. iotg->otg.state = OTG_STATE_B_IDLE;
  600. } else {
  601. iotg->hsm.id = 0;
  602. iotg->otg.default_a = 1;
  603. set_host_mode();
  604. iotg->otg.state = OTG_STATE_A_IDLE;
  605. }
  606. /* set session indicator */
  607. if (val32 & OTGSC_BSE)
  608. iotg->hsm.b_sess_end = 1;
  609. if (val32 & OTGSC_BSV)
  610. iotg->hsm.b_sess_vld = 1;
  611. if (val32 & OTGSC_ASV)
  612. iotg->hsm.a_sess_vld = 1;
  613. if (val32 & OTGSC_AVV)
  614. iotg->hsm.a_vbus_vld = 1;
  615. /* defautly power the bus */
  616. iotg->hsm.a_bus_req = 1;
  617. iotg->hsm.a_bus_drop = 0;
  618. /* defautly don't request bus as B device */
  619. iotg->hsm.b_bus_req = 0;
  620. /* no system error */
  621. iotg->hsm.a_clr_err = 0;
  622. langwell_otg_phy_low_power_wait(1);
  623. }
  624. static void update_hsm(void)
  625. {
  626. struct langwell_otg *lnw = the_transceiver;
  627. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  628. u32 val32;
  629. /* read OTGSC */
  630. val32 = readl(lnw->iotg.base + CI_OTGSC);
  631. dev_dbg(lnw->dev, "%s: OTGSC value = 0x%x\n", __func__, val32);
  632. iotg->hsm.id = !!(val32 & OTGSC_ID);
  633. iotg->hsm.b_sess_end = !!(val32 & OTGSC_BSE);
  634. iotg->hsm.b_sess_vld = !!(val32 & OTGSC_BSV);
  635. iotg->hsm.a_sess_vld = !!(val32 & OTGSC_ASV);
  636. iotg->hsm.a_vbus_vld = !!(val32 & OTGSC_AVV);
  637. }
  638. static irqreturn_t otg_dummy_irq(int irq, void *_dev)
  639. {
  640. struct langwell_otg *lnw = the_transceiver;
  641. void __iomem *reg_base = _dev;
  642. u32 val;
  643. u32 int_mask = 0;
  644. val = readl(reg_base + CI_USBMODE);
  645. if ((val & USBMODE_CM) != USBMODE_DEVICE)
  646. return IRQ_NONE;
  647. val = readl(reg_base + CI_USBSTS);
  648. int_mask = val & INTR_DUMMY_MASK;
  649. if (int_mask == 0)
  650. return IRQ_NONE;
  651. /* clear hsm.b_conn here since host driver can't detect it
  652. * otg_dummy_irq called means B-disconnect happened.
  653. */
  654. if (lnw->iotg.hsm.b_conn) {
  655. lnw->iotg.hsm.b_conn = 0;
  656. if (spin_trylock(&lnw->wq_lock)) {
  657. langwell_update_transceiver();
  658. spin_unlock(&lnw->wq_lock);
  659. }
  660. }
  661. /* Clear interrupts */
  662. writel(int_mask, reg_base + CI_USBSTS);
  663. return IRQ_HANDLED;
  664. }
  665. static irqreturn_t otg_irq(int irq, void *_dev)
  666. {
  667. struct langwell_otg *lnw = _dev;
  668. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  669. u32 int_sts, int_en;
  670. u32 int_mask = 0;
  671. int flag = 0;
  672. int_sts = readl(lnw->iotg.base + CI_OTGSC);
  673. int_en = (int_sts & OTGSC_INTEN_MASK) >> 8;
  674. int_mask = int_sts & int_en;
  675. if (int_mask == 0)
  676. return IRQ_NONE;
  677. if (int_mask & OTGSC_IDIS) {
  678. dev_dbg(lnw->dev, "%s: id change int\n", __func__);
  679. iotg->hsm.id = (int_sts & OTGSC_ID) ? 1 : 0;
  680. dev_dbg(lnw->dev, "id = %d\n", iotg->hsm.id);
  681. flag = 1;
  682. }
  683. if (int_mask & OTGSC_DPIS) {
  684. dev_dbg(lnw->dev, "%s: data pulse int\n", __func__);
  685. iotg->hsm.a_srp_det = (int_sts & OTGSC_DPS) ? 1 : 0;
  686. dev_dbg(lnw->dev, "data pulse = %d\n", iotg->hsm.a_srp_det);
  687. flag = 1;
  688. }
  689. if (int_mask & OTGSC_BSEIS) {
  690. dev_dbg(lnw->dev, "%s: b session end int\n", __func__);
  691. iotg->hsm.b_sess_end = (int_sts & OTGSC_BSE) ? 1 : 0;
  692. dev_dbg(lnw->dev, "b_sess_end = %d\n", iotg->hsm.b_sess_end);
  693. flag = 1;
  694. }
  695. if (int_mask & OTGSC_BSVIS) {
  696. dev_dbg(lnw->dev, "%s: b session valid int\n", __func__);
  697. iotg->hsm.b_sess_vld = (int_sts & OTGSC_BSV) ? 1 : 0;
  698. dev_dbg(lnw->dev, "b_sess_vld = %d\n", iotg->hsm.b_sess_end);
  699. flag = 1;
  700. }
  701. if (int_mask & OTGSC_ASVIS) {
  702. dev_dbg(lnw->dev, "%s: a session valid int\n", __func__);
  703. iotg->hsm.a_sess_vld = (int_sts & OTGSC_ASV) ? 1 : 0;
  704. dev_dbg(lnw->dev, "a_sess_vld = %d\n", iotg->hsm.a_sess_vld);
  705. flag = 1;
  706. }
  707. if (int_mask & OTGSC_AVVIS) {
  708. dev_dbg(lnw->dev, "%s: a vbus valid int\n", __func__);
  709. iotg->hsm.a_vbus_vld = (int_sts & OTGSC_AVV) ? 1 : 0;
  710. dev_dbg(lnw->dev, "a_vbus_vld = %d\n", iotg->hsm.a_vbus_vld);
  711. flag = 1;
  712. }
  713. if (int_mask & OTGSC_1MSS) {
  714. /* need to schedule otg_work if any timer is expired */
  715. if (langwell_otg_tick_timer(&int_sts))
  716. flag = 1;
  717. }
  718. writel((int_sts & ~OTGSC_INTSTS_MASK) | int_mask,
  719. lnw->iotg.base + CI_OTGSC);
  720. if (flag)
  721. langwell_update_transceiver();
  722. return IRQ_HANDLED;
  723. }
  724. static int langwell_otg_iotg_notify(struct notifier_block *nb,
  725. unsigned long action, void *data)
  726. {
  727. struct langwell_otg *lnw = the_transceiver;
  728. struct intel_mid_otg_xceiv *iotg = data;
  729. int flag = 0;
  730. if (iotg == NULL)
  731. return NOTIFY_BAD;
  732. if (lnw == NULL)
  733. return NOTIFY_BAD;
  734. switch (action) {
  735. case MID_OTG_NOTIFY_CONNECT:
  736. dev_dbg(lnw->dev, "Lnw OTG Notify Connect Event\n");
  737. if (iotg->otg.default_a == 1)
  738. iotg->hsm.b_conn = 1;
  739. else
  740. iotg->hsm.a_conn = 1;
  741. flag = 1;
  742. break;
  743. case MID_OTG_NOTIFY_DISCONN:
  744. dev_dbg(lnw->dev, "Lnw OTG Notify Disconnect Event\n");
  745. if (iotg->otg.default_a == 1)
  746. iotg->hsm.b_conn = 0;
  747. else
  748. iotg->hsm.a_conn = 0;
  749. flag = 1;
  750. break;
  751. case MID_OTG_NOTIFY_HSUSPEND:
  752. dev_dbg(lnw->dev, "Lnw OTG Notify Host Bus suspend Event\n");
  753. if (iotg->otg.default_a == 1)
  754. iotg->hsm.a_suspend_req = 1;
  755. else
  756. iotg->hsm.b_bus_req = 0;
  757. flag = 1;
  758. break;
  759. case MID_OTG_NOTIFY_HRESUME:
  760. dev_dbg(lnw->dev, "Lnw OTG Notify Host Bus resume Event\n");
  761. if (iotg->otg.default_a == 1)
  762. iotg->hsm.b_bus_resume = 1;
  763. flag = 1;
  764. break;
  765. case MID_OTG_NOTIFY_CSUSPEND:
  766. dev_dbg(lnw->dev, "Lnw OTG Notify Client Bus suspend Event\n");
  767. if (iotg->otg.default_a == 1) {
  768. if (iotg->hsm.b_bus_suspend_vld == 2) {
  769. iotg->hsm.b_bus_suspend = 1;
  770. iotg->hsm.b_bus_suspend_vld = 0;
  771. flag = 1;
  772. } else {
  773. iotg->hsm.b_bus_suspend_vld++;
  774. flag = 0;
  775. }
  776. } else {
  777. if (iotg->hsm.a_bus_suspend == 0) {
  778. iotg->hsm.a_bus_suspend = 1;
  779. flag = 1;
  780. }
  781. }
  782. break;
  783. case MID_OTG_NOTIFY_CRESUME:
  784. dev_dbg(lnw->dev, "Lnw OTG Notify Client Bus resume Event\n");
  785. if (iotg->otg.default_a == 0)
  786. iotg->hsm.a_bus_suspend = 0;
  787. flag = 0;
  788. break;
  789. case MID_OTG_NOTIFY_HOSTADD:
  790. dev_dbg(lnw->dev, "Lnw OTG Nofity Host Driver Add\n");
  791. flag = 1;
  792. break;
  793. case MID_OTG_NOTIFY_HOSTREMOVE:
  794. dev_dbg(lnw->dev, "Lnw OTG Nofity Host Driver remove\n");
  795. flag = 1;
  796. break;
  797. case MID_OTG_NOTIFY_CLIENTADD:
  798. dev_dbg(lnw->dev, "Lnw OTG Nofity Client Driver Add\n");
  799. flag = 1;
  800. break;
  801. case MID_OTG_NOTIFY_CLIENTREMOVE:
  802. dev_dbg(lnw->dev, "Lnw OTG Nofity Client Driver remove\n");
  803. flag = 1;
  804. break;
  805. default:
  806. dev_dbg(lnw->dev, "Lnw OTG Nofity unknown notify message\n");
  807. return NOTIFY_DONE;
  808. }
  809. if (flag)
  810. langwell_update_transceiver();
  811. return NOTIFY_OK;
  812. }
  813. static void langwell_otg_work(struct work_struct *work)
  814. {
  815. struct langwell_otg *lnw;
  816. struct intel_mid_otg_xceiv *iotg;
  817. int retval;
  818. struct pci_dev *pdev;
  819. lnw = container_of(work, struct langwell_otg, work);
  820. iotg = &lnw->iotg;
  821. pdev = to_pci_dev(lnw->dev);
  822. dev_dbg(lnw->dev, "%s: old state = %s\n", __func__,
  823. state_string(iotg->otg.state));
  824. switch (iotg->otg.state) {
  825. case OTG_STATE_UNDEFINED:
  826. case OTG_STATE_B_IDLE:
  827. if (!iotg->hsm.id) {
  828. langwell_otg_del_timer(b_srp_init_tmr);
  829. del_timer_sync(&lnw->hsm_timer);
  830. iotg->otg.default_a = 1;
  831. iotg->hsm.a_srp_det = 0;
  832. langwell_otg_chrg_vbus(0);
  833. set_host_mode();
  834. langwell_otg_phy_low_power(1);
  835. iotg->otg.state = OTG_STATE_A_IDLE;
  836. langwell_update_transceiver();
  837. } else if (iotg->hsm.b_sess_vld) {
  838. langwell_otg_del_timer(b_srp_init_tmr);
  839. del_timer_sync(&lnw->hsm_timer);
  840. iotg->hsm.b_sess_end = 0;
  841. iotg->hsm.a_bus_suspend = 0;
  842. langwell_otg_chrg_vbus(0);
  843. if (lnw->iotg.start_peripheral) {
  844. lnw->iotg.start_peripheral(&lnw->iotg);
  845. iotg->otg.state = OTG_STATE_B_PERIPHERAL;
  846. } else
  847. dev_dbg(lnw->dev, "client driver not loaded\n");
  848. } else if (iotg->hsm.b_srp_init_tmout) {
  849. iotg->hsm.b_srp_init_tmout = 0;
  850. dev_warn(lnw->dev, "SRP init timeout\n");
  851. } else if (iotg->hsm.b_srp_fail_tmout) {
  852. iotg->hsm.b_srp_fail_tmout = 0;
  853. iotg->hsm.b_bus_req = 0;
  854. /* No silence failure */
  855. langwell_otg_nsf_msg(6);
  856. } else if (iotg->hsm.b_bus_req && iotg->hsm.b_sess_end) {
  857. del_timer_sync(&lnw->hsm_timer);
  858. /* workaround for b_se0_srp detection */
  859. retval = langwell_otg_check_se0_srp(0);
  860. if (retval) {
  861. iotg->hsm.b_bus_req = 0;
  862. dev_dbg(lnw->dev, "LS isn't SE0, try later\n");
  863. } else {
  864. /* clear the PHCD before start srp */
  865. langwell_otg_phy_low_power(0);
  866. /* Start SRP */
  867. langwell_otg_add_timer(b_srp_init_tmr);
  868. iotg->otg.start_srp(&iotg->otg);
  869. langwell_otg_del_timer(b_srp_init_tmr);
  870. langwell_otg_add_ktimer(TB_SRP_FAIL_TMR);
  871. /* reset PHY low power mode here */
  872. langwell_otg_phy_low_power_wait(1);
  873. }
  874. }
  875. break;
  876. case OTG_STATE_B_SRP_INIT:
  877. if (!iotg->hsm.id) {
  878. iotg->otg.default_a = 1;
  879. iotg->hsm.a_srp_det = 0;
  880. /* Turn off VBus */
  881. iotg->otg.set_vbus(&iotg->otg, false);
  882. langwell_otg_chrg_vbus(0);
  883. set_host_mode();
  884. langwell_otg_phy_low_power(1);
  885. iotg->otg.state = OTG_STATE_A_IDLE;
  886. langwell_update_transceiver();
  887. } else if (iotg->hsm.b_sess_vld) {
  888. langwell_otg_chrg_vbus(0);
  889. if (lnw->iotg.start_peripheral) {
  890. lnw->iotg.start_peripheral(&lnw->iotg);
  891. iotg->otg.state = OTG_STATE_B_PERIPHERAL;
  892. } else
  893. dev_dbg(lnw->dev, "client driver not loaded\n");
  894. }
  895. break;
  896. case OTG_STATE_B_PERIPHERAL:
  897. if (!iotg->hsm.id) {
  898. iotg->otg.default_a = 1;
  899. iotg->hsm.a_srp_det = 0;
  900. langwell_otg_chrg_vbus(0);
  901. if (lnw->iotg.stop_peripheral)
  902. lnw->iotg.stop_peripheral(&lnw->iotg);
  903. else
  904. dev_dbg(lnw->dev,
  905. "client driver has been removed.\n");
  906. set_host_mode();
  907. langwell_otg_phy_low_power(1);
  908. iotg->otg.state = OTG_STATE_A_IDLE;
  909. langwell_update_transceiver();
  910. } else if (!iotg->hsm.b_sess_vld) {
  911. iotg->hsm.b_hnp_enable = 0;
  912. if (lnw->iotg.stop_peripheral)
  913. lnw->iotg.stop_peripheral(&lnw->iotg);
  914. else
  915. dev_dbg(lnw->dev,
  916. "client driver has been removed.\n");
  917. iotg->otg.state = OTG_STATE_B_IDLE;
  918. } else if (iotg->hsm.b_bus_req && iotg->otg.gadget &&
  919. iotg->otg.gadget->b_hnp_enable &&
  920. iotg->hsm.a_bus_suspend) {
  921. if (lnw->iotg.stop_peripheral)
  922. lnw->iotg.stop_peripheral(&lnw->iotg);
  923. else
  924. dev_dbg(lnw->dev,
  925. "client driver has been removed.\n");
  926. langwell_otg_HAAR(1);
  927. iotg->hsm.a_conn = 0;
  928. if (lnw->iotg.start_host) {
  929. lnw->iotg.start_host(&lnw->iotg);
  930. iotg->otg.state = OTG_STATE_B_WAIT_ACON;
  931. } else
  932. dev_dbg(lnw->dev,
  933. "host driver not loaded.\n");
  934. iotg->hsm.a_bus_resume = 0;
  935. langwell_otg_add_ktimer(TB_ASE0_BRST_TMR);
  936. }
  937. break;
  938. case OTG_STATE_B_WAIT_ACON:
  939. if (!iotg->hsm.id) {
  940. /* delete hsm timer for b_ase0_brst_tmr */
  941. del_timer_sync(&lnw->hsm_timer);
  942. iotg->otg.default_a = 1;
  943. iotg->hsm.a_srp_det = 0;
  944. langwell_otg_chrg_vbus(0);
  945. langwell_otg_HAAR(0);
  946. if (lnw->iotg.stop_host)
  947. lnw->iotg.stop_host(&lnw->iotg);
  948. else
  949. dev_dbg(lnw->dev,
  950. "host driver has been removed.\n");
  951. set_host_mode();
  952. langwell_otg_phy_low_power(1);
  953. iotg->otg.state = OTG_STATE_A_IDLE;
  954. langwell_update_transceiver();
  955. } else if (!iotg->hsm.b_sess_vld) {
  956. /* delete hsm timer for b_ase0_brst_tmr */
  957. del_timer_sync(&lnw->hsm_timer);
  958. iotg->hsm.b_hnp_enable = 0;
  959. iotg->hsm.b_bus_req = 0;
  960. langwell_otg_chrg_vbus(0);
  961. langwell_otg_HAAR(0);
  962. if (lnw->iotg.stop_host)
  963. lnw->iotg.stop_host(&lnw->iotg);
  964. else
  965. dev_dbg(lnw->dev,
  966. "host driver has been removed.\n");
  967. set_client_mode();
  968. langwell_otg_phy_low_power(1);
  969. iotg->otg.state = OTG_STATE_B_IDLE;
  970. } else if (iotg->hsm.a_conn) {
  971. /* delete hsm timer for b_ase0_brst_tmr */
  972. del_timer_sync(&lnw->hsm_timer);
  973. langwell_otg_HAAR(0);
  974. iotg->otg.state = OTG_STATE_B_HOST;
  975. langwell_update_transceiver();
  976. } else if (iotg->hsm.a_bus_resume ||
  977. iotg->hsm.b_ase0_brst_tmout) {
  978. /* delete hsm timer for b_ase0_brst_tmr */
  979. del_timer_sync(&lnw->hsm_timer);
  980. langwell_otg_HAAR(0);
  981. langwell_otg_nsf_msg(7);
  982. if (lnw->iotg.stop_host)
  983. lnw->iotg.stop_host(&lnw->iotg);
  984. else
  985. dev_dbg(lnw->dev,
  986. "host driver has been removed.\n");
  987. iotg->hsm.a_bus_suspend = 0;
  988. iotg->hsm.b_bus_req = 0;
  989. if (lnw->iotg.start_peripheral)
  990. lnw->iotg.start_peripheral(&lnw->iotg);
  991. else
  992. dev_dbg(lnw->dev,
  993. "client driver not loaded.\n");
  994. iotg->otg.state = OTG_STATE_B_PERIPHERAL;
  995. }
  996. break;
  997. case OTG_STATE_B_HOST:
  998. if (!iotg->hsm.id) {
  999. iotg->otg.default_a = 1;
  1000. iotg->hsm.a_srp_det = 0;
  1001. langwell_otg_chrg_vbus(0);
  1002. if (lnw->iotg.stop_host)
  1003. lnw->iotg.stop_host(&lnw->iotg);
  1004. else
  1005. dev_dbg(lnw->dev,
  1006. "host driver has been removed.\n");
  1007. set_host_mode();
  1008. langwell_otg_phy_low_power(1);
  1009. iotg->otg.state = OTG_STATE_A_IDLE;
  1010. langwell_update_transceiver();
  1011. } else if (!iotg->hsm.b_sess_vld) {
  1012. iotg->hsm.b_hnp_enable = 0;
  1013. iotg->hsm.b_bus_req = 0;
  1014. langwell_otg_chrg_vbus(0);
  1015. if (lnw->iotg.stop_host)
  1016. lnw->iotg.stop_host(&lnw->iotg);
  1017. else
  1018. dev_dbg(lnw->dev,
  1019. "host driver has been removed.\n");
  1020. set_client_mode();
  1021. langwell_otg_phy_low_power(1);
  1022. iotg->otg.state = OTG_STATE_B_IDLE;
  1023. } else if ((!iotg->hsm.b_bus_req) ||
  1024. (!iotg->hsm.a_conn)) {
  1025. iotg->hsm.b_bus_req = 0;
  1026. langwell_otg_loc_sof(0);
  1027. if (lnw->iotg.stop_host)
  1028. lnw->iotg.stop_host(&lnw->iotg);
  1029. else
  1030. dev_dbg(lnw->dev,
  1031. "host driver has been removed.\n");
  1032. iotg->hsm.a_bus_suspend = 0;
  1033. if (lnw->iotg.start_peripheral)
  1034. lnw->iotg.start_peripheral(&lnw->iotg);
  1035. else
  1036. dev_dbg(lnw->dev,
  1037. "client driver not loaded.\n");
  1038. iotg->otg.state = OTG_STATE_B_PERIPHERAL;
  1039. }
  1040. break;
  1041. case OTG_STATE_A_IDLE:
  1042. iotg->otg.default_a = 1;
  1043. if (iotg->hsm.id) {
  1044. iotg->otg.default_a = 0;
  1045. iotg->hsm.b_bus_req = 0;
  1046. iotg->hsm.vbus_srp_up = 0;
  1047. langwell_otg_chrg_vbus(0);
  1048. set_client_mode();
  1049. langwell_otg_phy_low_power(1);
  1050. iotg->otg.state = OTG_STATE_B_IDLE;
  1051. langwell_update_transceiver();
  1052. } else if (!iotg->hsm.a_bus_drop &&
  1053. (iotg->hsm.a_srp_det || iotg->hsm.a_bus_req)) {
  1054. langwell_otg_phy_low_power(0);
  1055. /* Turn on VBus */
  1056. iotg->otg.set_vbus(&iotg->otg, true);
  1057. iotg->hsm.vbus_srp_up = 0;
  1058. iotg->hsm.a_wait_vrise_tmout = 0;
  1059. langwell_otg_add_timer(a_wait_vrise_tmr);
  1060. iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
  1061. langwell_update_transceiver();
  1062. } else if (!iotg->hsm.a_bus_drop && iotg->hsm.a_sess_vld) {
  1063. iotg->hsm.vbus_srp_up = 1;
  1064. } else if (!iotg->hsm.a_sess_vld && iotg->hsm.vbus_srp_up) {
  1065. msleep(10);
  1066. langwell_otg_phy_low_power(0);
  1067. /* Turn on VBus */
  1068. iotg->otg.set_vbus(&iotg->otg, true);
  1069. iotg->hsm.a_srp_det = 1;
  1070. iotg->hsm.vbus_srp_up = 0;
  1071. iotg->hsm.a_wait_vrise_tmout = 0;
  1072. langwell_otg_add_timer(a_wait_vrise_tmr);
  1073. iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
  1074. langwell_update_transceiver();
  1075. } else if (!iotg->hsm.a_sess_vld &&
  1076. !iotg->hsm.vbus_srp_up) {
  1077. langwell_otg_phy_low_power(1);
  1078. }
  1079. break;
  1080. case OTG_STATE_A_WAIT_VRISE:
  1081. if (iotg->hsm.id) {
  1082. langwell_otg_del_timer(a_wait_vrise_tmr);
  1083. iotg->hsm.b_bus_req = 0;
  1084. iotg->otg.default_a = 0;
  1085. /* Turn off VBus */
  1086. iotg->otg.set_vbus(&iotg->otg, false);
  1087. set_client_mode();
  1088. langwell_otg_phy_low_power_wait(1);
  1089. iotg->otg.state = OTG_STATE_B_IDLE;
  1090. } else if (iotg->hsm.a_vbus_vld) {
  1091. langwell_otg_del_timer(a_wait_vrise_tmr);
  1092. iotg->hsm.b_conn = 0;
  1093. if (lnw->iotg.start_host)
  1094. lnw->iotg.start_host(&lnw->iotg);
  1095. else {
  1096. dev_dbg(lnw->dev, "host driver not loaded.\n");
  1097. break;
  1098. }
  1099. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1100. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1101. } else if (iotg->hsm.a_wait_vrise_tmout) {
  1102. iotg->hsm.b_conn = 0;
  1103. if (iotg->hsm.a_vbus_vld) {
  1104. if (lnw->iotg.start_host)
  1105. lnw->iotg.start_host(&lnw->iotg);
  1106. else {
  1107. dev_dbg(lnw->dev,
  1108. "host driver not loaded.\n");
  1109. break;
  1110. }
  1111. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1112. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1113. } else {
  1114. /* Turn off VBus */
  1115. iotg->otg.set_vbus(&iotg->otg, false);
  1116. langwell_otg_phy_low_power_wait(1);
  1117. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1118. }
  1119. }
  1120. break;
  1121. case OTG_STATE_A_WAIT_BCON:
  1122. if (iotg->hsm.id) {
  1123. /* delete hsm timer for a_wait_bcon_tmr */
  1124. del_timer_sync(&lnw->hsm_timer);
  1125. iotg->otg.default_a = 0;
  1126. iotg->hsm.b_bus_req = 0;
  1127. if (lnw->iotg.stop_host)
  1128. lnw->iotg.stop_host(&lnw->iotg);
  1129. else
  1130. dev_dbg(lnw->dev,
  1131. "host driver has been removed.\n");
  1132. /* Turn off VBus */
  1133. iotg->otg.set_vbus(&iotg->otg, false);
  1134. set_client_mode();
  1135. langwell_otg_phy_low_power_wait(1);
  1136. iotg->otg.state = OTG_STATE_B_IDLE;
  1137. langwell_update_transceiver();
  1138. } else if (!iotg->hsm.a_vbus_vld) {
  1139. /* delete hsm timer for a_wait_bcon_tmr */
  1140. del_timer_sync(&lnw->hsm_timer);
  1141. if (lnw->iotg.stop_host)
  1142. lnw->iotg.stop_host(&lnw->iotg);
  1143. else
  1144. dev_dbg(lnw->dev,
  1145. "host driver has been removed.\n");
  1146. /* Turn off VBus */
  1147. iotg->otg.set_vbus(&iotg->otg, false);
  1148. langwell_otg_phy_low_power_wait(1);
  1149. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1150. } else if (iotg->hsm.a_bus_drop ||
  1151. (iotg->hsm.a_wait_bcon_tmout &&
  1152. !iotg->hsm.a_bus_req)) {
  1153. /* delete hsm timer for a_wait_bcon_tmr */
  1154. del_timer_sync(&lnw->hsm_timer);
  1155. if (lnw->iotg.stop_host)
  1156. lnw->iotg.stop_host(&lnw->iotg);
  1157. else
  1158. dev_dbg(lnw->dev,
  1159. "host driver has been removed.\n");
  1160. /* Turn off VBus */
  1161. iotg->otg.set_vbus(&iotg->otg, false);
  1162. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1163. } else if (iotg->hsm.b_conn) {
  1164. /* delete hsm timer for a_wait_bcon_tmr */
  1165. del_timer_sync(&lnw->hsm_timer);
  1166. iotg->hsm.a_suspend_req = 0;
  1167. iotg->otg.state = OTG_STATE_A_HOST;
  1168. if (iotg->hsm.a_srp_det && iotg->otg.host &&
  1169. !iotg->otg.host->b_hnp_enable) {
  1170. /* SRP capable peripheral-only device */
  1171. iotg->hsm.a_bus_req = 1;
  1172. iotg->hsm.a_srp_det = 0;
  1173. } else if (!iotg->hsm.a_bus_req && iotg->otg.host &&
  1174. iotg->otg.host->b_hnp_enable) {
  1175. /* It is not safe enough to do a fast
  1176. * transistion from A_WAIT_BCON to
  1177. * A_SUSPEND */
  1178. msleep(10000);
  1179. if (iotg->hsm.a_bus_req)
  1180. break;
  1181. if (request_irq(pdev->irq,
  1182. otg_dummy_irq, IRQF_SHARED,
  1183. driver_name, iotg->base) != 0) {
  1184. dev_dbg(lnw->dev,
  1185. "request interrupt %d fail\n",
  1186. pdev->irq);
  1187. }
  1188. langwell_otg_HABA(1);
  1189. iotg->hsm.b_bus_resume = 0;
  1190. iotg->hsm.a_aidl_bdis_tmout = 0;
  1191. langwell_otg_loc_sof(0);
  1192. /* clear PHCD to enable HW timer */
  1193. langwell_otg_phy_low_power(0);
  1194. langwell_otg_add_timer(a_aidl_bdis_tmr);
  1195. iotg->otg.state = OTG_STATE_A_SUSPEND;
  1196. } else if (!iotg->hsm.a_bus_req && iotg->otg.host &&
  1197. !iotg->otg.host->b_hnp_enable) {
  1198. if (lnw->iotg.stop_host)
  1199. lnw->iotg.stop_host(&lnw->iotg);
  1200. else
  1201. dev_dbg(lnw->dev,
  1202. "host driver removed.\n");
  1203. /* Turn off VBus */
  1204. iotg->otg.set_vbus(&iotg->otg, false);
  1205. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1206. }
  1207. }
  1208. break;
  1209. case OTG_STATE_A_HOST:
  1210. if (iotg->hsm.id) {
  1211. iotg->otg.default_a = 0;
  1212. iotg->hsm.b_bus_req = 0;
  1213. if (lnw->iotg.stop_host)
  1214. lnw->iotg.stop_host(&lnw->iotg);
  1215. else
  1216. dev_dbg(lnw->dev,
  1217. "host driver has been removed.\n");
  1218. /* Turn off VBus */
  1219. iotg->otg.set_vbus(&iotg->otg, false);
  1220. set_client_mode();
  1221. langwell_otg_phy_low_power_wait(1);
  1222. iotg->otg.state = OTG_STATE_B_IDLE;
  1223. langwell_update_transceiver();
  1224. } else if (iotg->hsm.a_bus_drop ||
  1225. (iotg->otg.host &&
  1226. !iotg->otg.host->b_hnp_enable &&
  1227. !iotg->hsm.a_bus_req)) {
  1228. if (lnw->iotg.stop_host)
  1229. lnw->iotg.stop_host(&lnw->iotg);
  1230. else
  1231. dev_dbg(lnw->dev,
  1232. "host driver has been removed.\n");
  1233. /* Turn off VBus */
  1234. iotg->otg.set_vbus(&iotg->otg, false);
  1235. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1236. } else if (!iotg->hsm.a_vbus_vld) {
  1237. if (lnw->iotg.stop_host)
  1238. lnw->iotg.stop_host(&lnw->iotg);
  1239. else
  1240. dev_dbg(lnw->dev,
  1241. "host driver has been removed.\n");
  1242. /* Turn off VBus */
  1243. iotg->otg.set_vbus(&iotg->otg, false);
  1244. langwell_otg_phy_low_power_wait(1);
  1245. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1246. } else if (iotg->otg.host &&
  1247. iotg->otg.host->b_hnp_enable &&
  1248. !iotg->hsm.a_bus_req) {
  1249. /* Set HABA to enable hardware assistance to signal
  1250. * A-connect after receiver B-disconnect. Hardware
  1251. * will then set client mode and enable URE, SLE and
  1252. * PCE after the assistance. otg_dummy_irq is used to
  1253. * clean these ints when client driver is not resumed.
  1254. */
  1255. if (request_irq(pdev->irq, otg_dummy_irq, IRQF_SHARED,
  1256. driver_name, iotg->base) != 0) {
  1257. dev_dbg(lnw->dev,
  1258. "request interrupt %d failed\n",
  1259. pdev->irq);
  1260. }
  1261. /* set HABA */
  1262. langwell_otg_HABA(1);
  1263. iotg->hsm.b_bus_resume = 0;
  1264. iotg->hsm.a_aidl_bdis_tmout = 0;
  1265. langwell_otg_loc_sof(0);
  1266. /* clear PHCD to enable HW timer */
  1267. langwell_otg_phy_low_power(0);
  1268. langwell_otg_add_timer(a_aidl_bdis_tmr);
  1269. iotg->otg.state = OTG_STATE_A_SUSPEND;
  1270. } else if (!iotg->hsm.b_conn || !iotg->hsm.a_bus_req) {
  1271. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1272. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1273. }
  1274. break;
  1275. case OTG_STATE_A_SUSPEND:
  1276. if (iotg->hsm.id) {
  1277. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1278. langwell_otg_HABA(0);
  1279. free_irq(pdev->irq, iotg->base);
  1280. iotg->otg.default_a = 0;
  1281. iotg->hsm.b_bus_req = 0;
  1282. if (lnw->iotg.stop_host)
  1283. lnw->iotg.stop_host(&lnw->iotg);
  1284. else
  1285. dev_dbg(lnw->dev,
  1286. "host driver has been removed.\n");
  1287. /* Turn off VBus */
  1288. iotg->otg.set_vbus(&iotg->otg, false);
  1289. set_client_mode();
  1290. langwell_otg_phy_low_power(1);
  1291. iotg->otg.state = OTG_STATE_B_IDLE;
  1292. langwell_update_transceiver();
  1293. } else if (iotg->hsm.a_bus_req ||
  1294. iotg->hsm.b_bus_resume) {
  1295. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1296. langwell_otg_HABA(0);
  1297. free_irq(pdev->irq, iotg->base);
  1298. iotg->hsm.a_suspend_req = 0;
  1299. langwell_otg_loc_sof(1);
  1300. iotg->otg.state = OTG_STATE_A_HOST;
  1301. } else if (iotg->hsm.a_aidl_bdis_tmout ||
  1302. iotg->hsm.a_bus_drop) {
  1303. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1304. langwell_otg_HABA(0);
  1305. free_irq(pdev->irq, iotg->base);
  1306. if (lnw->iotg.stop_host)
  1307. lnw->iotg.stop_host(&lnw->iotg);
  1308. else
  1309. dev_dbg(lnw->dev,
  1310. "host driver has been removed.\n");
  1311. /* Turn off VBus */
  1312. iotg->otg.set_vbus(&iotg->otg, false);
  1313. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1314. } else if (!iotg->hsm.b_conn && iotg->otg.host &&
  1315. iotg->otg.host->b_hnp_enable) {
  1316. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1317. langwell_otg_HABA(0);
  1318. free_irq(pdev->irq, iotg->base);
  1319. if (lnw->iotg.stop_host)
  1320. lnw->iotg.stop_host(&lnw->iotg);
  1321. else
  1322. dev_dbg(lnw->dev,
  1323. "host driver has been removed.\n");
  1324. iotg->hsm.b_bus_suspend = 0;
  1325. iotg->hsm.b_bus_suspend_vld = 0;
  1326. /* msleep(200); */
  1327. if (lnw->iotg.start_peripheral)
  1328. lnw->iotg.start_peripheral(&lnw->iotg);
  1329. else
  1330. dev_dbg(lnw->dev,
  1331. "client driver not loaded.\n");
  1332. langwell_otg_add_ktimer(TB_BUS_SUSPEND_TMR);
  1333. iotg->otg.state = OTG_STATE_A_PERIPHERAL;
  1334. break;
  1335. } else if (!iotg->hsm.a_vbus_vld) {
  1336. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1337. langwell_otg_HABA(0);
  1338. free_irq(pdev->irq, iotg->base);
  1339. if (lnw->iotg.stop_host)
  1340. lnw->iotg.stop_host(&lnw->iotg);
  1341. else
  1342. dev_dbg(lnw->dev,
  1343. "host driver has been removed.\n");
  1344. /* Turn off VBus */
  1345. iotg->otg.set_vbus(&iotg->otg, false);
  1346. langwell_otg_phy_low_power_wait(1);
  1347. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1348. }
  1349. break;
  1350. case OTG_STATE_A_PERIPHERAL:
  1351. if (iotg->hsm.id) {
  1352. /* delete hsm timer for b_bus_suspend_tmr */
  1353. del_timer_sync(&lnw->hsm_timer);
  1354. iotg->otg.default_a = 0;
  1355. iotg->hsm.b_bus_req = 0;
  1356. if (lnw->iotg.stop_peripheral)
  1357. lnw->iotg.stop_peripheral(&lnw->iotg);
  1358. else
  1359. dev_dbg(lnw->dev,
  1360. "client driver has been removed.\n");
  1361. /* Turn off VBus */
  1362. iotg->otg.set_vbus(&iotg->otg, false);
  1363. set_client_mode();
  1364. langwell_otg_phy_low_power_wait(1);
  1365. iotg->otg.state = OTG_STATE_B_IDLE;
  1366. langwell_update_transceiver();
  1367. } else if (!iotg->hsm.a_vbus_vld) {
  1368. /* delete hsm timer for b_bus_suspend_tmr */
  1369. del_timer_sync(&lnw->hsm_timer);
  1370. if (lnw->iotg.stop_peripheral)
  1371. lnw->iotg.stop_peripheral(&lnw->iotg);
  1372. else
  1373. dev_dbg(lnw->dev,
  1374. "client driver has been removed.\n");
  1375. /* Turn off VBus */
  1376. iotg->otg.set_vbus(&iotg->otg, false);
  1377. langwell_otg_phy_low_power_wait(1);
  1378. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1379. } else if (iotg->hsm.a_bus_drop) {
  1380. /* delete hsm timer for b_bus_suspend_tmr */
  1381. del_timer_sync(&lnw->hsm_timer);
  1382. if (lnw->iotg.stop_peripheral)
  1383. lnw->iotg.stop_peripheral(&lnw->iotg);
  1384. else
  1385. dev_dbg(lnw->dev,
  1386. "client driver has been removed.\n");
  1387. /* Turn off VBus */
  1388. iotg->otg.set_vbus(&iotg->otg, false);
  1389. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1390. } else if (iotg->hsm.b_bus_suspend) {
  1391. /* delete hsm timer for b_bus_suspend_tmr */
  1392. del_timer_sync(&lnw->hsm_timer);
  1393. if (lnw->iotg.stop_peripheral)
  1394. lnw->iotg.stop_peripheral(&lnw->iotg);
  1395. else
  1396. dev_dbg(lnw->dev,
  1397. "client driver has been removed.\n");
  1398. if (lnw->iotg.start_host)
  1399. lnw->iotg.start_host(&lnw->iotg);
  1400. else
  1401. dev_dbg(lnw->dev,
  1402. "host driver not loaded.\n");
  1403. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1404. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1405. } else if (iotg->hsm.b_bus_suspend_tmout) {
  1406. u32 val;
  1407. val = readl(lnw->iotg.base + CI_PORTSC1);
  1408. if (!(val & PORTSC_SUSP))
  1409. break;
  1410. if (lnw->iotg.stop_peripheral)
  1411. lnw->iotg.stop_peripheral(&lnw->iotg);
  1412. else
  1413. dev_dbg(lnw->dev,
  1414. "client driver has been removed.\n");
  1415. if (lnw->iotg.start_host)
  1416. lnw->iotg.start_host(&lnw->iotg);
  1417. else
  1418. dev_dbg(lnw->dev,
  1419. "host driver not loaded.\n");
  1420. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1421. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1422. }
  1423. break;
  1424. case OTG_STATE_A_VBUS_ERR:
  1425. if (iotg->hsm.id) {
  1426. iotg->otg.default_a = 0;
  1427. iotg->hsm.a_clr_err = 0;
  1428. iotg->hsm.a_srp_det = 0;
  1429. set_client_mode();
  1430. langwell_otg_phy_low_power(1);
  1431. iotg->otg.state = OTG_STATE_B_IDLE;
  1432. langwell_update_transceiver();
  1433. } else if (iotg->hsm.a_clr_err) {
  1434. iotg->hsm.a_clr_err = 0;
  1435. iotg->hsm.a_srp_det = 0;
  1436. reset_otg();
  1437. init_hsm();
  1438. if (iotg->otg.state == OTG_STATE_A_IDLE)
  1439. langwell_update_transceiver();
  1440. } else {
  1441. /* FW will clear PHCD bit when any VBus
  1442. * event detected. Reset PHCD to 1 again */
  1443. langwell_otg_phy_low_power(1);
  1444. }
  1445. break;
  1446. case OTG_STATE_A_WAIT_VFALL:
  1447. if (iotg->hsm.id) {
  1448. iotg->otg.default_a = 0;
  1449. set_client_mode();
  1450. langwell_otg_phy_low_power(1);
  1451. iotg->otg.state = OTG_STATE_B_IDLE;
  1452. langwell_update_transceiver();
  1453. } else if (iotg->hsm.a_bus_req) {
  1454. /* Turn on VBus */
  1455. iotg->otg.set_vbus(&iotg->otg, true);
  1456. iotg->hsm.a_wait_vrise_tmout = 0;
  1457. langwell_otg_add_timer(a_wait_vrise_tmr);
  1458. iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
  1459. } else if (!iotg->hsm.a_sess_vld) {
  1460. iotg->hsm.a_srp_det = 0;
  1461. set_host_mode();
  1462. langwell_otg_phy_low_power(1);
  1463. iotg->otg.state = OTG_STATE_A_IDLE;
  1464. }
  1465. break;
  1466. default:
  1467. ;
  1468. }
  1469. dev_dbg(lnw->dev, "%s: new state = %s\n", __func__,
  1470. state_string(iotg->otg.state));
  1471. }
  1472. static ssize_t
  1473. show_registers(struct device *_dev, struct device_attribute *attr, char *buf)
  1474. {
  1475. struct langwell_otg *lnw = the_transceiver;
  1476. char *next;
  1477. unsigned size, t;
  1478. next = buf;
  1479. size = PAGE_SIZE;
  1480. t = scnprintf(next, size,
  1481. "\n"
  1482. "USBCMD = 0x%08x\n"
  1483. "USBSTS = 0x%08x\n"
  1484. "USBINTR = 0x%08x\n"
  1485. "ASYNCLISTADDR = 0x%08x\n"
  1486. "PORTSC1 = 0x%08x\n"
  1487. "HOSTPC1 = 0x%08x\n"
  1488. "OTGSC = 0x%08x\n"
  1489. "USBMODE = 0x%08x\n",
  1490. readl(lnw->iotg.base + 0x30),
  1491. readl(lnw->iotg.base + 0x34),
  1492. readl(lnw->iotg.base + 0x38),
  1493. readl(lnw->iotg.base + 0x48),
  1494. readl(lnw->iotg.base + 0x74),
  1495. readl(lnw->iotg.base + 0xb4),
  1496. readl(lnw->iotg.base + 0xf4),
  1497. readl(lnw->iotg.base + 0xf8)
  1498. );
  1499. size -= t;
  1500. next += t;
  1501. return PAGE_SIZE - size;
  1502. }
  1503. static DEVICE_ATTR(registers, S_IRUGO, show_registers, NULL);
  1504. static ssize_t
  1505. show_hsm(struct device *_dev, struct device_attribute *attr, char *buf)
  1506. {
  1507. struct langwell_otg *lnw = the_transceiver;
  1508. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1509. char *next;
  1510. unsigned size, t;
  1511. next = buf;
  1512. size = PAGE_SIZE;
  1513. if (iotg->otg.host)
  1514. iotg->hsm.a_set_b_hnp_en = iotg->otg.host->b_hnp_enable;
  1515. if (iotg->otg.gadget)
  1516. iotg->hsm.b_hnp_enable = iotg->otg.gadget->b_hnp_enable;
  1517. t = scnprintf(next, size,
  1518. "\n"
  1519. "current state = %s\n"
  1520. "a_bus_resume = \t%d\n"
  1521. "a_bus_suspend = \t%d\n"
  1522. "a_conn = \t%d\n"
  1523. "a_sess_vld = \t%d\n"
  1524. "a_srp_det = \t%d\n"
  1525. "a_vbus_vld = \t%d\n"
  1526. "b_bus_resume = \t%d\n"
  1527. "b_bus_suspend = \t%d\n"
  1528. "b_conn = \t%d\n"
  1529. "b_se0_srp = \t%d\n"
  1530. "b_sess_end = \t%d\n"
  1531. "b_sess_vld = \t%d\n"
  1532. "id = \t%d\n"
  1533. "a_set_b_hnp_en = \t%d\n"
  1534. "b_srp_done = \t%d\n"
  1535. "b_hnp_enable = \t%d\n"
  1536. "a_wait_vrise_tmout = \t%d\n"
  1537. "a_wait_bcon_tmout = \t%d\n"
  1538. "a_aidl_bdis_tmout = \t%d\n"
  1539. "b_ase0_brst_tmout = \t%d\n"
  1540. "a_bus_drop = \t%d\n"
  1541. "a_bus_req = \t%d\n"
  1542. "a_clr_err = \t%d\n"
  1543. "a_suspend_req = \t%d\n"
  1544. "b_bus_req = \t%d\n"
  1545. "b_bus_suspend_tmout = \t%d\n"
  1546. "b_bus_suspend_vld = \t%d\n",
  1547. state_string(iotg->otg.state),
  1548. iotg->hsm.a_bus_resume,
  1549. iotg->hsm.a_bus_suspend,
  1550. iotg->hsm.a_conn,
  1551. iotg->hsm.a_sess_vld,
  1552. iotg->hsm.a_srp_det,
  1553. iotg->hsm.a_vbus_vld,
  1554. iotg->hsm.b_bus_resume,
  1555. iotg->hsm.b_bus_suspend,
  1556. iotg->hsm.b_conn,
  1557. iotg->hsm.b_se0_srp,
  1558. iotg->hsm.b_sess_end,
  1559. iotg->hsm.b_sess_vld,
  1560. iotg->hsm.id,
  1561. iotg->hsm.a_set_b_hnp_en,
  1562. iotg->hsm.b_srp_done,
  1563. iotg->hsm.b_hnp_enable,
  1564. iotg->hsm.a_wait_vrise_tmout,
  1565. iotg->hsm.a_wait_bcon_tmout,
  1566. iotg->hsm.a_aidl_bdis_tmout,
  1567. iotg->hsm.b_ase0_brst_tmout,
  1568. iotg->hsm.a_bus_drop,
  1569. iotg->hsm.a_bus_req,
  1570. iotg->hsm.a_clr_err,
  1571. iotg->hsm.a_suspend_req,
  1572. iotg->hsm.b_bus_req,
  1573. iotg->hsm.b_bus_suspend_tmout,
  1574. iotg->hsm.b_bus_suspend_vld
  1575. );
  1576. size -= t;
  1577. next += t;
  1578. return PAGE_SIZE - size;
  1579. }
  1580. static DEVICE_ATTR(hsm, S_IRUGO, show_hsm, NULL);
  1581. static ssize_t
  1582. get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  1583. {
  1584. struct langwell_otg *lnw = the_transceiver;
  1585. char *next;
  1586. unsigned size, t;
  1587. next = buf;
  1588. size = PAGE_SIZE;
  1589. t = scnprintf(next, size, "%d", lnw->iotg.hsm.a_bus_req);
  1590. size -= t;
  1591. next += t;
  1592. return PAGE_SIZE - size;
  1593. }
  1594. static ssize_t
  1595. set_a_bus_req(struct device *dev, struct device_attribute *attr,
  1596. const char *buf, size_t count)
  1597. {
  1598. struct langwell_otg *lnw = the_transceiver;
  1599. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1600. if (!iotg->otg.default_a)
  1601. return -1;
  1602. if (count > 2)
  1603. return -1;
  1604. if (buf[0] == '0') {
  1605. iotg->hsm.a_bus_req = 0;
  1606. dev_dbg(lnw->dev, "User request: a_bus_req = 0\n");
  1607. } else if (buf[0] == '1') {
  1608. /* If a_bus_drop is TRUE, a_bus_req can't be set */
  1609. if (iotg->hsm.a_bus_drop)
  1610. return -1;
  1611. iotg->hsm.a_bus_req = 1;
  1612. dev_dbg(lnw->dev, "User request: a_bus_req = 1\n");
  1613. }
  1614. if (spin_trylock(&lnw->wq_lock)) {
  1615. langwell_update_transceiver();
  1616. spin_unlock(&lnw->wq_lock);
  1617. }
  1618. return count;
  1619. }
  1620. static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req, set_a_bus_req);
  1621. static ssize_t
  1622. get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf)
  1623. {
  1624. struct langwell_otg *lnw = the_transceiver;
  1625. char *next;
  1626. unsigned size, t;
  1627. next = buf;
  1628. size = PAGE_SIZE;
  1629. t = scnprintf(next, size, "%d", lnw->iotg.hsm.a_bus_drop);
  1630. size -= t;
  1631. next += t;
  1632. return PAGE_SIZE - size;
  1633. }
  1634. static ssize_t
  1635. set_a_bus_drop(struct device *dev, struct device_attribute *attr,
  1636. const char *buf, size_t count)
  1637. {
  1638. struct langwell_otg *lnw = the_transceiver;
  1639. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1640. if (!iotg->otg.default_a)
  1641. return -1;
  1642. if (count > 2)
  1643. return -1;
  1644. if (buf[0] == '0') {
  1645. iotg->hsm.a_bus_drop = 0;
  1646. dev_dbg(lnw->dev, "User request: a_bus_drop = 0\n");
  1647. } else if (buf[0] == '1') {
  1648. iotg->hsm.a_bus_drop = 1;
  1649. iotg->hsm.a_bus_req = 0;
  1650. dev_dbg(lnw->dev, "User request: a_bus_drop = 1\n");
  1651. dev_dbg(lnw->dev, "User request: and a_bus_req = 0\n");
  1652. }
  1653. if (spin_trylock(&lnw->wq_lock)) {
  1654. langwell_update_transceiver();
  1655. spin_unlock(&lnw->wq_lock);
  1656. }
  1657. return count;
  1658. }
  1659. static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR, get_a_bus_drop, set_a_bus_drop);
  1660. static ssize_t
  1661. get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  1662. {
  1663. struct langwell_otg *lnw = the_transceiver;
  1664. char *next;
  1665. unsigned size, t;
  1666. next = buf;
  1667. size = PAGE_SIZE;
  1668. t = scnprintf(next, size, "%d", lnw->iotg.hsm.b_bus_req);
  1669. size -= t;
  1670. next += t;
  1671. return PAGE_SIZE - size;
  1672. }
  1673. static ssize_t
  1674. set_b_bus_req(struct device *dev, struct device_attribute *attr,
  1675. const char *buf, size_t count)
  1676. {
  1677. struct langwell_otg *lnw = the_transceiver;
  1678. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1679. if (iotg->otg.default_a)
  1680. return -1;
  1681. if (count > 2)
  1682. return -1;
  1683. if (buf[0] == '0') {
  1684. iotg->hsm.b_bus_req = 0;
  1685. dev_dbg(lnw->dev, "User request: b_bus_req = 0\n");
  1686. } else if (buf[0] == '1') {
  1687. iotg->hsm.b_bus_req = 1;
  1688. dev_dbg(lnw->dev, "User request: b_bus_req = 1\n");
  1689. }
  1690. if (spin_trylock(&lnw->wq_lock)) {
  1691. langwell_update_transceiver();
  1692. spin_unlock(&lnw->wq_lock);
  1693. }
  1694. return count;
  1695. }
  1696. static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUSR, get_b_bus_req, set_b_bus_req);
  1697. static ssize_t
  1698. set_a_clr_err(struct device *dev, struct device_attribute *attr,
  1699. const char *buf, size_t count)
  1700. {
  1701. struct langwell_otg *lnw = the_transceiver;
  1702. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1703. if (!iotg->otg.default_a)
  1704. return -1;
  1705. if (count > 2)
  1706. return -1;
  1707. if (buf[0] == '1') {
  1708. iotg->hsm.a_clr_err = 1;
  1709. dev_dbg(lnw->dev, "User request: a_clr_err = 1\n");
  1710. }
  1711. if (spin_trylock(&lnw->wq_lock)) {
  1712. langwell_update_transceiver();
  1713. spin_unlock(&lnw->wq_lock);
  1714. }
  1715. return count;
  1716. }
  1717. static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
  1718. static struct attribute *inputs_attrs[] = {
  1719. &dev_attr_a_bus_req.attr,
  1720. &dev_attr_a_bus_drop.attr,
  1721. &dev_attr_b_bus_req.attr,
  1722. &dev_attr_a_clr_err.attr,
  1723. NULL,
  1724. };
  1725. static struct attribute_group debug_dev_attr_group = {
  1726. .name = "inputs",
  1727. .attrs = inputs_attrs,
  1728. };
  1729. static int langwell_otg_probe(struct pci_dev *pdev,
  1730. const struct pci_device_id *id)
  1731. {
  1732. unsigned long resource, len;
  1733. void __iomem *base = NULL;
  1734. int retval;
  1735. u32 val32;
  1736. struct langwell_otg *lnw;
  1737. char qname[] = "langwell_otg_queue";
  1738. retval = 0;
  1739. dev_dbg(&pdev->dev, "\notg controller is detected.\n");
  1740. if (pci_enable_device(pdev) < 0) {
  1741. retval = -ENODEV;
  1742. goto done;
  1743. }
  1744. lnw = kzalloc(sizeof *lnw, GFP_KERNEL);
  1745. if (lnw == NULL) {
  1746. retval = -ENOMEM;
  1747. goto done;
  1748. }
  1749. the_transceiver = lnw;
  1750. /* control register: BAR 0 */
  1751. resource = pci_resource_start(pdev, 0);
  1752. len = pci_resource_len(pdev, 0);
  1753. if (!request_mem_region(resource, len, driver_name)) {
  1754. retval = -EBUSY;
  1755. goto err;
  1756. }
  1757. lnw->region = 1;
  1758. base = ioremap_nocache(resource, len);
  1759. if (base == NULL) {
  1760. retval = -EFAULT;
  1761. goto err;
  1762. }
  1763. lnw->iotg.base = base;
  1764. if (!request_mem_region(USBCFG_ADDR, USBCFG_LEN, driver_name)) {
  1765. retval = -EBUSY;
  1766. goto err;
  1767. }
  1768. lnw->cfg_region = 1;
  1769. /* For the SCCB.USBCFG register */
  1770. base = ioremap_nocache(USBCFG_ADDR, USBCFG_LEN);
  1771. if (base == NULL) {
  1772. retval = -EFAULT;
  1773. goto err;
  1774. }
  1775. lnw->usbcfg = base;
  1776. if (!pdev->irq) {
  1777. dev_dbg(&pdev->dev, "No IRQ.\n");
  1778. retval = -ENODEV;
  1779. goto err;
  1780. }
  1781. lnw->qwork = create_singlethread_workqueue(qname);
  1782. if (!lnw->qwork) {
  1783. dev_dbg(&pdev->dev, "cannot create workqueue %s\n", qname);
  1784. retval = -ENOMEM;
  1785. goto err;
  1786. }
  1787. INIT_WORK(&lnw->work, langwell_otg_work);
  1788. /* OTG common part */
  1789. lnw->dev = &pdev->dev;
  1790. lnw->iotg.otg.dev = lnw->dev;
  1791. lnw->iotg.otg.label = driver_name;
  1792. lnw->iotg.otg.set_host = langwell_otg_set_host;
  1793. lnw->iotg.otg.set_peripheral = langwell_otg_set_peripheral;
  1794. lnw->iotg.otg.set_power = langwell_otg_set_power;
  1795. lnw->iotg.otg.set_vbus = langwell_otg_set_vbus;
  1796. lnw->iotg.otg.start_srp = langwell_otg_start_srp;
  1797. lnw->iotg.otg.state = OTG_STATE_UNDEFINED;
  1798. if (otg_set_transceiver(&lnw->iotg.otg)) {
  1799. dev_dbg(lnw->dev, "can't set transceiver\n");
  1800. retval = -EBUSY;
  1801. goto err;
  1802. }
  1803. reset_otg();
  1804. init_hsm();
  1805. spin_lock_init(&lnw->lock);
  1806. spin_lock_init(&lnw->wq_lock);
  1807. INIT_LIST_HEAD(&active_timers);
  1808. retval = langwell_otg_init_timers(&lnw->iotg.hsm);
  1809. if (retval) {
  1810. dev_dbg(&pdev->dev, "Failed to init timers\n");
  1811. goto err;
  1812. }
  1813. init_timer(&lnw->hsm_timer);
  1814. ATOMIC_INIT_NOTIFIER_HEAD(&lnw->iotg.iotg_notifier);
  1815. lnw->iotg_notifier.notifier_call = langwell_otg_iotg_notify;
  1816. retval = intel_mid_otg_register_notifier(&lnw->iotg,
  1817. &lnw->iotg_notifier);
  1818. if (retval) {
  1819. dev_dbg(lnw->dev, "Failed to register notifier\n");
  1820. goto err;
  1821. }
  1822. if (request_irq(pdev->irq, otg_irq, IRQF_SHARED,
  1823. driver_name, lnw) != 0) {
  1824. dev_dbg(lnw->dev, "request interrupt %d failed\n", pdev->irq);
  1825. retval = -EBUSY;
  1826. goto err;
  1827. }
  1828. /* enable OTGSC int */
  1829. val32 = OTGSC_DPIE | OTGSC_BSEIE | OTGSC_BSVIE |
  1830. OTGSC_ASVIE | OTGSC_AVVIE | OTGSC_IDIE | OTGSC_IDPU;
  1831. writel(val32, lnw->iotg.base + CI_OTGSC);
  1832. retval = device_create_file(&pdev->dev, &dev_attr_registers);
  1833. if (retval < 0) {
  1834. dev_dbg(lnw->dev,
  1835. "Can't register sysfs attribute: %d\n", retval);
  1836. goto err;
  1837. }
  1838. retval = device_create_file(&pdev->dev, &dev_attr_hsm);
  1839. if (retval < 0) {
  1840. dev_dbg(lnw->dev, "Can't hsm sysfs attribute: %d\n", retval);
  1841. goto err;
  1842. }
  1843. retval = sysfs_create_group(&pdev->dev.kobj, &debug_dev_attr_group);
  1844. if (retval < 0) {
  1845. dev_dbg(lnw->dev,
  1846. "Can't register sysfs attr group: %d\n", retval);
  1847. goto err;
  1848. }
  1849. if (lnw->iotg.otg.state == OTG_STATE_A_IDLE)
  1850. langwell_update_transceiver();
  1851. return 0;
  1852. err:
  1853. if (the_transceiver)
  1854. langwell_otg_remove(pdev);
  1855. done:
  1856. return retval;
  1857. }
  1858. static void langwell_otg_remove(struct pci_dev *pdev)
  1859. {
  1860. struct langwell_otg *lnw = the_transceiver;
  1861. if (lnw->qwork) {
  1862. flush_workqueue(lnw->qwork);
  1863. destroy_workqueue(lnw->qwork);
  1864. }
  1865. intel_mid_otg_unregister_notifier(&lnw->iotg, &lnw->iotg_notifier);
  1866. langwell_otg_free_timers();
  1867. /* disable OTGSC interrupt as OTGSC doesn't change in reset */
  1868. writel(0, lnw->iotg.base + CI_OTGSC);
  1869. if (pdev->irq)
  1870. free_irq(pdev->irq, lnw);
  1871. if (lnw->usbcfg)
  1872. iounmap(lnw->usbcfg);
  1873. if (lnw->cfg_region)
  1874. release_mem_region(USBCFG_ADDR, USBCFG_LEN);
  1875. if (lnw->iotg.base)
  1876. iounmap(lnw->iotg.base);
  1877. if (lnw->region)
  1878. release_mem_region(pci_resource_start(pdev, 0),
  1879. pci_resource_len(pdev, 0));
  1880. otg_set_transceiver(NULL);
  1881. pci_disable_device(pdev);
  1882. sysfs_remove_group(&pdev->dev.kobj, &debug_dev_attr_group);
  1883. device_remove_file(&pdev->dev, &dev_attr_hsm);
  1884. device_remove_file(&pdev->dev, &dev_attr_registers);
  1885. kfree(lnw);
  1886. lnw = NULL;
  1887. }
  1888. static void transceiver_suspend(struct pci_dev *pdev)
  1889. {
  1890. pci_save_state(pdev);
  1891. pci_set_power_state(pdev, PCI_D3hot);
  1892. langwell_otg_phy_low_power(1);
  1893. }
  1894. static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message)
  1895. {
  1896. struct langwell_otg *lnw = the_transceiver;
  1897. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1898. int ret = 0;
  1899. /* Disbale OTG interrupts */
  1900. langwell_otg_intr(0);
  1901. if (pdev->irq)
  1902. free_irq(pdev->irq, lnw);
  1903. /* Prevent more otg_work */
  1904. flush_workqueue(lnw->qwork);
  1905. destroy_workqueue(lnw->qwork);
  1906. lnw->qwork = NULL;
  1907. /* start actions */
  1908. switch (iotg->otg.state) {
  1909. case OTG_STATE_A_WAIT_VFALL:
  1910. iotg->otg.state = OTG_STATE_A_IDLE;
  1911. case OTG_STATE_A_IDLE:
  1912. case OTG_STATE_B_IDLE:
  1913. case OTG_STATE_A_VBUS_ERR:
  1914. transceiver_suspend(pdev);
  1915. break;
  1916. case OTG_STATE_A_WAIT_VRISE:
  1917. langwell_otg_del_timer(a_wait_vrise_tmr);
  1918. iotg->hsm.a_srp_det = 0;
  1919. /* Turn off VBus */
  1920. iotg->otg.set_vbus(&iotg->otg, false);
  1921. iotg->otg.state = OTG_STATE_A_IDLE;
  1922. transceiver_suspend(pdev);
  1923. break;
  1924. case OTG_STATE_A_WAIT_BCON:
  1925. del_timer_sync(&lnw->hsm_timer);
  1926. if (lnw->iotg.stop_host)
  1927. lnw->iotg.stop_host(&lnw->iotg);
  1928. else
  1929. dev_dbg(&pdev->dev, "host driver has been removed.\n");
  1930. iotg->hsm.a_srp_det = 0;
  1931. /* Turn off VBus */
  1932. iotg->otg.set_vbus(&iotg->otg, false);
  1933. iotg->otg.state = OTG_STATE_A_IDLE;
  1934. transceiver_suspend(pdev);
  1935. break;
  1936. case OTG_STATE_A_HOST:
  1937. if (lnw->iotg.stop_host)
  1938. lnw->iotg.stop_host(&lnw->iotg);
  1939. else
  1940. dev_dbg(&pdev->dev, "host driver has been removed.\n");
  1941. iotg->hsm.a_srp_det = 0;
  1942. /* Turn off VBus */
  1943. iotg->otg.set_vbus(&iotg->otg, false);
  1944. iotg->otg.state = OTG_STATE_A_IDLE;
  1945. transceiver_suspend(pdev);
  1946. break;
  1947. case OTG_STATE_A_SUSPEND:
  1948. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1949. langwell_otg_HABA(0);
  1950. if (lnw->iotg.stop_host)
  1951. lnw->iotg.stop_host(&lnw->iotg);
  1952. else
  1953. dev_dbg(lnw->dev, "host driver has been removed.\n");
  1954. iotg->hsm.a_srp_det = 0;
  1955. /* Turn off VBus */
  1956. iotg->otg.set_vbus(&iotg->otg, false);
  1957. iotg->otg.state = OTG_STATE_A_IDLE;
  1958. transceiver_suspend(pdev);
  1959. break;
  1960. case OTG_STATE_A_PERIPHERAL:
  1961. del_timer_sync(&lnw->hsm_timer);
  1962. if (lnw->iotg.stop_peripheral)
  1963. lnw->iotg.stop_peripheral(&lnw->iotg);
  1964. else
  1965. dev_dbg(&pdev->dev,
  1966. "client driver has been removed.\n");
  1967. iotg->hsm.a_srp_det = 0;
  1968. /* Turn off VBus */
  1969. iotg->otg.set_vbus(&iotg->otg, false);
  1970. iotg->otg.state = OTG_STATE_A_IDLE;
  1971. transceiver_suspend(pdev);
  1972. break;
  1973. case OTG_STATE_B_HOST:
  1974. if (lnw->iotg.stop_host)
  1975. lnw->iotg.stop_host(&lnw->iotg);
  1976. else
  1977. dev_dbg(&pdev->dev, "host driver has been removed.\n");
  1978. iotg->hsm.b_bus_req = 0;
  1979. iotg->otg.state = OTG_STATE_B_IDLE;
  1980. transceiver_suspend(pdev);
  1981. break;
  1982. case OTG_STATE_B_PERIPHERAL:
  1983. if (lnw->iotg.stop_peripheral)
  1984. lnw->iotg.stop_peripheral(&lnw->iotg);
  1985. else
  1986. dev_dbg(&pdev->dev,
  1987. "client driver has been removed.\n");
  1988. iotg->otg.state = OTG_STATE_B_IDLE;
  1989. transceiver_suspend(pdev);
  1990. break;
  1991. case OTG_STATE_B_WAIT_ACON:
  1992. /* delete hsm timer for b_ase0_brst_tmr */
  1993. del_timer_sync(&lnw->hsm_timer);
  1994. langwell_otg_HAAR(0);
  1995. if (lnw->iotg.stop_host)
  1996. lnw->iotg.stop_host(&lnw->iotg);
  1997. else
  1998. dev_dbg(&pdev->dev, "host driver has been removed.\n");
  1999. iotg->hsm.b_bus_req = 0;
  2000. iotg->otg.state = OTG_STATE_B_IDLE;
  2001. transceiver_suspend(pdev);
  2002. break;
  2003. default:
  2004. dev_dbg(lnw->dev, "error state before suspend\n");
  2005. break;
  2006. }
  2007. return ret;
  2008. }
  2009. static void transceiver_resume(struct pci_dev *pdev)
  2010. {
  2011. pci_restore_state(pdev);
  2012. pci_set_power_state(pdev, PCI_D0);
  2013. }
  2014. static int langwell_otg_resume(struct pci_dev *pdev)
  2015. {
  2016. struct langwell_otg *lnw = the_transceiver;
  2017. int ret = 0;
  2018. transceiver_resume(pdev);
  2019. lnw->qwork = create_singlethread_workqueue("langwell_otg_queue");
  2020. if (!lnw->qwork) {
  2021. dev_dbg(&pdev->dev, "cannot create langwell otg workqueuen");
  2022. ret = -ENOMEM;
  2023. goto error;
  2024. }
  2025. if (request_irq(pdev->irq, otg_irq, IRQF_SHARED,
  2026. driver_name, lnw) != 0) {
  2027. dev_dbg(&pdev->dev, "request interrupt %d failed\n", pdev->irq);
  2028. ret = -EBUSY;
  2029. goto error;
  2030. }
  2031. /* enable OTG interrupts */
  2032. langwell_otg_intr(1);
  2033. update_hsm();
  2034. langwell_update_transceiver();
  2035. return ret;
  2036. error:
  2037. langwell_otg_intr(0);
  2038. transceiver_suspend(pdev);
  2039. return ret;
  2040. }
  2041. static int __init langwell_otg_init(void)
  2042. {
  2043. return pci_register_driver(&otg_pci_driver);
  2044. }
  2045. module_init(langwell_otg_init);
  2046. static void __exit langwell_otg_cleanup(void)
  2047. {
  2048. pci_unregister_driver(&otg_pci_driver);
  2049. }
  2050. module_exit(langwell_otg_cleanup);