omap2430.c 13 KB

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  1. /*
  2. * Copyright (C) 2005-2007 by Texas Instruments
  3. * Some code has been taken from tusb6010.c
  4. * Copyrights for that are attributable to:
  5. * Copyright (C) 2006 Nokia Corporation
  6. * Tony Lindgren <tony@atomide.com>
  7. *
  8. * This file is part of the Inventra Controller Driver for Linux.
  9. *
  10. * The Inventra Controller Driver for Linux is free software; you
  11. * can redistribute it and/or modify it under the terms of the GNU
  12. * General Public License version 2 as published by the Free Software
  13. * Foundation.
  14. *
  15. * The Inventra Controller Driver for Linux is distributed in
  16. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17. * without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  19. * License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with The Inventra Controller Driver for Linux ; if not,
  23. * write to the Free Software Foundation, Inc., 59 Temple Place,
  24. * Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/sched.h>
  30. #include <linux/init.h>
  31. #include <linux/list.h>
  32. #include <linux/clk.h>
  33. #include <linux/io.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/err.h>
  38. #include "musb_core.h"
  39. #include "omap2430.h"
  40. struct omap2430_glue {
  41. struct device *dev;
  42. struct platform_device *musb;
  43. };
  44. #define glue_to_musb(g) platform_get_drvdata(g->musb)
  45. static struct timer_list musb_idle_timer;
  46. static void musb_do_idle(unsigned long _musb)
  47. {
  48. struct musb *musb = (void *)_musb;
  49. unsigned long flags;
  50. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  51. u8 power;
  52. #endif
  53. u8 devctl;
  54. spin_lock_irqsave(&musb->lock, flags);
  55. switch (musb->xceiv->state) {
  56. case OTG_STATE_A_WAIT_BCON:
  57. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  58. if (devctl & MUSB_DEVCTL_BDEVICE) {
  59. musb->xceiv->state = OTG_STATE_B_IDLE;
  60. MUSB_DEV_MODE(musb);
  61. } else {
  62. musb->xceiv->state = OTG_STATE_A_IDLE;
  63. MUSB_HST_MODE(musb);
  64. }
  65. break;
  66. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  67. case OTG_STATE_A_SUSPEND:
  68. /* finish RESUME signaling? */
  69. if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
  70. power = musb_readb(musb->mregs, MUSB_POWER);
  71. power &= ~MUSB_POWER_RESUME;
  72. DBG(1, "root port resume stopped, power %02x\n", power);
  73. musb_writeb(musb->mregs, MUSB_POWER, power);
  74. musb->is_active = 1;
  75. musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
  76. | MUSB_PORT_STAT_RESUME);
  77. musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
  78. usb_hcd_poll_rh_status(musb_to_hcd(musb));
  79. /* NOTE: it might really be A_WAIT_BCON ... */
  80. musb->xceiv->state = OTG_STATE_A_HOST;
  81. }
  82. break;
  83. #endif
  84. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  85. case OTG_STATE_A_HOST:
  86. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  87. if (devctl & MUSB_DEVCTL_BDEVICE)
  88. musb->xceiv->state = OTG_STATE_B_IDLE;
  89. else
  90. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  91. #endif
  92. default:
  93. break;
  94. }
  95. spin_unlock_irqrestore(&musb->lock, flags);
  96. }
  97. static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
  98. {
  99. unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
  100. static unsigned long last_timer;
  101. if (timeout == 0)
  102. timeout = default_timeout;
  103. /* Never idle if active, or when VBUS timeout is not set as host */
  104. if (musb->is_active || ((musb->a_wait_bcon == 0)
  105. && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
  106. DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
  107. del_timer(&musb_idle_timer);
  108. last_timer = jiffies;
  109. return;
  110. }
  111. if (time_after(last_timer, timeout)) {
  112. if (!timer_pending(&musb_idle_timer))
  113. last_timer = timeout;
  114. else {
  115. DBG(4, "Longer idle timer already pending, ignoring\n");
  116. return;
  117. }
  118. }
  119. last_timer = timeout;
  120. DBG(4, "%s inactive, for idle timer for %lu ms\n",
  121. otg_state_string(musb),
  122. (unsigned long)jiffies_to_msecs(timeout - jiffies));
  123. mod_timer(&musb_idle_timer, timeout);
  124. }
  125. static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
  126. {
  127. u8 devctl;
  128. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  129. int ret = 1;
  130. /* HDRC controls CPEN, but beware current surges during device
  131. * connect. They can trigger transient overcurrent conditions
  132. * that must be ignored.
  133. */
  134. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  135. if (is_on) {
  136. if (musb->xceiv->state == OTG_STATE_A_IDLE) {
  137. /* start the session */
  138. devctl |= MUSB_DEVCTL_SESSION;
  139. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  140. /*
  141. * Wait for the musb to set as A device to enable the
  142. * VBUS
  143. */
  144. while (musb_readb(musb->mregs, MUSB_DEVCTL) & 0x80) {
  145. cpu_relax();
  146. if (time_after(jiffies, timeout)) {
  147. dev_err(musb->controller,
  148. "configured as A device timeout");
  149. ret = -EINVAL;
  150. break;
  151. }
  152. }
  153. if (ret && musb->xceiv->set_vbus)
  154. otg_set_vbus(musb->xceiv, 1);
  155. } else {
  156. musb->is_active = 1;
  157. musb->xceiv->default_a = 1;
  158. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  159. devctl |= MUSB_DEVCTL_SESSION;
  160. MUSB_HST_MODE(musb);
  161. }
  162. } else {
  163. musb->is_active = 0;
  164. /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
  165. * jumping right to B_IDLE...
  166. */
  167. musb->xceiv->default_a = 0;
  168. musb->xceiv->state = OTG_STATE_B_IDLE;
  169. devctl &= ~MUSB_DEVCTL_SESSION;
  170. MUSB_DEV_MODE(musb);
  171. }
  172. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  173. DBG(1, "VBUS %s, devctl %02x "
  174. /* otg %3x conf %08x prcm %08x */ "\n",
  175. otg_state_string(musb),
  176. musb_readb(musb->mregs, MUSB_DEVCTL));
  177. }
  178. static int omap2430_musb_set_mode(struct musb *musb, u8 musb_mode)
  179. {
  180. u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  181. devctl |= MUSB_DEVCTL_SESSION;
  182. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  183. return 0;
  184. }
  185. static inline void omap2430_low_level_exit(struct musb *musb)
  186. {
  187. u32 l;
  188. /* in any role */
  189. l = musb_readl(musb->mregs, OTG_FORCESTDBY);
  190. l |= ENABLEFORCE; /* enable MSTANDBY */
  191. musb_writel(musb->mregs, OTG_FORCESTDBY, l);
  192. }
  193. static inline void omap2430_low_level_init(struct musb *musb)
  194. {
  195. u32 l;
  196. l = musb_readl(musb->mregs, OTG_FORCESTDBY);
  197. l &= ~ENABLEFORCE; /* disable MSTANDBY */
  198. musb_writel(musb->mregs, OTG_FORCESTDBY, l);
  199. }
  200. /* blocking notifier support */
  201. static int musb_otg_notifications(struct notifier_block *nb,
  202. unsigned long event, void *unused)
  203. {
  204. struct musb *musb = container_of(nb, struct musb, nb);
  205. struct device *dev = musb->controller;
  206. struct musb_hdrc_platform_data *pdata = dev->platform_data;
  207. struct omap_musb_board_data *data = pdata->board_data;
  208. switch (event) {
  209. case USB_EVENT_ID:
  210. DBG(4, "ID GND\n");
  211. if (is_otg_enabled(musb)) {
  212. #ifdef CONFIG_USB_GADGET_MUSB_HDRC
  213. if (musb->gadget_driver) {
  214. pm_runtime_get_sync(musb->controller);
  215. otg_init(musb->xceiv);
  216. omap2430_musb_set_vbus(musb, 1);
  217. }
  218. #endif
  219. } else {
  220. pm_runtime_get_sync(musb->controller);
  221. otg_init(musb->xceiv);
  222. omap2430_musb_set_vbus(musb, 1);
  223. }
  224. break;
  225. case USB_EVENT_VBUS:
  226. DBG(4, "VBUS Connect\n");
  227. if (musb->gadget_driver)
  228. pm_runtime_get_sync(musb->controller);
  229. otg_init(musb->xceiv);
  230. break;
  231. case USB_EVENT_NONE:
  232. DBG(4, "VBUS Disconnect\n");
  233. #ifdef CONFIG_USB_GADGET_MUSB_HDRC
  234. if (is_otg_enabled(musb))
  235. if (musb->gadget_driver)
  236. #endif
  237. {
  238. pm_runtime_mark_last_busy(musb->controller);
  239. pm_runtime_put_autosuspend(musb->controller);
  240. }
  241. if (data->interface_type == MUSB_INTERFACE_UTMI) {
  242. if (musb->xceiv->set_vbus)
  243. otg_set_vbus(musb->xceiv, 0);
  244. }
  245. otg_shutdown(musb->xceiv);
  246. break;
  247. default:
  248. DBG(4, "ID float\n");
  249. return NOTIFY_DONE;
  250. }
  251. return NOTIFY_OK;
  252. }
  253. static int omap2430_musb_init(struct musb *musb)
  254. {
  255. u32 l, status = 0;
  256. struct device *dev = musb->controller;
  257. struct musb_hdrc_platform_data *plat = dev->platform_data;
  258. struct omap_musb_board_data *data = plat->board_data;
  259. /* We require some kind of external transceiver, hooked
  260. * up through ULPI. TWL4030-family PMICs include one,
  261. * which needs a driver, drivers aren't always needed.
  262. */
  263. musb->xceiv = otg_get_transceiver();
  264. if (!musb->xceiv) {
  265. pr_err("HS USB OTG: no transceiver configured\n");
  266. return -ENODEV;
  267. }
  268. status = pm_runtime_get_sync(dev);
  269. if (status < 0) {
  270. dev_err(dev, "pm_runtime_get_sync FAILED");
  271. goto err1;
  272. }
  273. l = musb_readl(musb->mregs, OTG_INTERFSEL);
  274. if (data->interface_type == MUSB_INTERFACE_UTMI) {
  275. /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
  276. l &= ~ULPI_12PIN; /* Disable ULPI */
  277. l |= UTMI_8BIT; /* Enable UTMI */
  278. } else {
  279. l |= ULPI_12PIN;
  280. }
  281. musb_writel(musb->mregs, OTG_INTERFSEL, l);
  282. pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
  283. "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
  284. musb_readl(musb->mregs, OTG_REVISION),
  285. musb_readl(musb->mregs, OTG_SYSCONFIG),
  286. musb_readl(musb->mregs, OTG_SYSSTATUS),
  287. musb_readl(musb->mregs, OTG_INTERFSEL),
  288. musb_readl(musb->mregs, OTG_SIMENABLE));
  289. musb->nb.notifier_call = musb_otg_notifications;
  290. status = otg_register_notifier(musb->xceiv, &musb->nb);
  291. if (status)
  292. DBG(1, "notification register failed\n");
  293. setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
  294. return 0;
  295. err1:
  296. pm_runtime_disable(dev);
  297. return status;
  298. }
  299. static void omap2430_musb_enable(struct musb *musb)
  300. {
  301. u8 devctl;
  302. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  303. struct device *dev = musb->controller;
  304. struct musb_hdrc_platform_data *pdata = dev->platform_data;
  305. struct omap_musb_board_data *data = pdata->board_data;
  306. switch (musb->xceiv->last_event) {
  307. case USB_EVENT_ID:
  308. otg_init(musb->xceiv);
  309. if (data->interface_type == MUSB_INTERFACE_UTMI) {
  310. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  311. /* start the session */
  312. devctl |= MUSB_DEVCTL_SESSION;
  313. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  314. while (musb_readb(musb->mregs, MUSB_DEVCTL) &
  315. MUSB_DEVCTL_BDEVICE) {
  316. cpu_relax();
  317. if (time_after(jiffies, timeout)) {
  318. dev_err(musb->controller,
  319. "configured as A device timeout");
  320. break;
  321. }
  322. }
  323. }
  324. break;
  325. case USB_EVENT_VBUS:
  326. otg_init(musb->xceiv);
  327. break;
  328. default:
  329. break;
  330. }
  331. }
  332. static void omap2430_musb_disable(struct musb *musb)
  333. {
  334. if (musb->xceiv->last_event)
  335. otg_shutdown(musb->xceiv);
  336. }
  337. static int omap2430_musb_exit(struct musb *musb)
  338. {
  339. del_timer_sync(&musb_idle_timer);
  340. omap2430_low_level_exit(musb);
  341. otg_put_transceiver(musb->xceiv);
  342. return 0;
  343. }
  344. static const struct musb_platform_ops omap2430_ops = {
  345. .init = omap2430_musb_init,
  346. .exit = omap2430_musb_exit,
  347. .set_mode = omap2430_musb_set_mode,
  348. .try_idle = omap2430_musb_try_idle,
  349. .set_vbus = omap2430_musb_set_vbus,
  350. .enable = omap2430_musb_enable,
  351. .disable = omap2430_musb_disable,
  352. };
  353. static u64 omap2430_dmamask = DMA_BIT_MASK(32);
  354. static int __init omap2430_probe(struct platform_device *pdev)
  355. {
  356. struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
  357. struct platform_device *musb;
  358. struct omap2430_glue *glue;
  359. int ret = -ENOMEM;
  360. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  361. if (!glue) {
  362. dev_err(&pdev->dev, "failed to allocate glue context\n");
  363. goto err0;
  364. }
  365. musb = platform_device_alloc("musb-hdrc", -1);
  366. if (!musb) {
  367. dev_err(&pdev->dev, "failed to allocate musb device\n");
  368. goto err1;
  369. }
  370. musb->dev.parent = &pdev->dev;
  371. musb->dev.dma_mask = &omap2430_dmamask;
  372. musb->dev.coherent_dma_mask = omap2430_dmamask;
  373. glue->dev = &pdev->dev;
  374. glue->musb = musb;
  375. pdata->platform_ops = &omap2430_ops;
  376. platform_set_drvdata(pdev, glue);
  377. ret = platform_device_add_resources(musb, pdev->resource,
  378. pdev->num_resources);
  379. if (ret) {
  380. dev_err(&pdev->dev, "failed to add resources\n");
  381. goto err2;
  382. }
  383. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  384. if (ret) {
  385. dev_err(&pdev->dev, "failed to add platform_data\n");
  386. goto err2;
  387. }
  388. ret = platform_device_add(musb);
  389. if (ret) {
  390. dev_err(&pdev->dev, "failed to register musb device\n");
  391. goto err2;
  392. }
  393. pm_runtime_enable(&pdev->dev);
  394. return 0;
  395. err2:
  396. platform_device_put(musb);
  397. err1:
  398. kfree(glue);
  399. err0:
  400. return ret;
  401. }
  402. static int __exit omap2430_remove(struct platform_device *pdev)
  403. {
  404. struct omap2430_glue *glue = platform_get_drvdata(pdev);
  405. platform_device_del(glue->musb);
  406. platform_device_put(glue->musb);
  407. pm_runtime_put(&pdev->dev);
  408. pm_runtime_disable(&pdev->dev);
  409. kfree(glue);
  410. return 0;
  411. }
  412. #ifdef CONFIG_PM
  413. static int omap2430_runtime_suspend(struct device *dev)
  414. {
  415. struct omap2430_glue *glue = dev_get_drvdata(dev);
  416. struct musb *musb = glue_to_musb(glue);
  417. omap2430_low_level_exit(musb);
  418. otg_set_suspend(musb->xceiv, 1);
  419. return 0;
  420. }
  421. static int omap2430_runtime_resume(struct device *dev)
  422. {
  423. struct omap2430_glue *glue = dev_get_drvdata(dev);
  424. struct musb *musb = glue_to_musb(glue);
  425. omap2430_low_level_init(musb);
  426. otg_set_suspend(musb->xceiv, 0);
  427. return 0;
  428. }
  429. static struct dev_pm_ops omap2430_pm_ops = {
  430. .runtime_suspend = omap2430_runtime_suspend,
  431. .runtime_resume = omap2430_runtime_resume,
  432. };
  433. #define DEV_PM_OPS (&omap2430_pm_ops)
  434. #else
  435. #define DEV_PM_OPS NULL
  436. #endif
  437. static struct platform_driver omap2430_driver = {
  438. .remove = __exit_p(omap2430_remove),
  439. .driver = {
  440. .name = "musb-omap2430",
  441. .pm = DEV_PM_OPS,
  442. },
  443. };
  444. MODULE_DESCRIPTION("OMAP2PLUS MUSB Glue Layer");
  445. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  446. MODULE_LICENSE("GPL v2");
  447. static int __init omap2430_init(void)
  448. {
  449. return platform_driver_probe(&omap2430_driver, omap2430_probe);
  450. }
  451. subsys_initcall(omap2430_init);
  452. static void __exit omap2430_exit(void)
  453. {
  454. platform_driver_unregister(&omap2430_driver);
  455. }
  456. module_exit(omap2430_exit);