ohci-pci.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439
  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * [ Initialisation is based on Linus' ]
  8. * [ uhci code and gregs ohci fragments ]
  9. * [ (C) Copyright 1999 Linus Torvalds ]
  10. * [ (C) Copyright 1999 Gregory P. Smith]
  11. *
  12. * PCI Bus Glue
  13. *
  14. * This file is licenced under the GPL.
  15. */
  16. #ifndef CONFIG_PCI
  17. #error "This file is PCI bus glue. CONFIG_PCI must be defined."
  18. #endif
  19. #include <linux/pci.h>
  20. #include <linux/io.h>
  21. /*-------------------------------------------------------------------------*/
  22. static int broken_suspend(struct usb_hcd *hcd)
  23. {
  24. device_init_wakeup(&hcd->self.root_hub->dev, 0);
  25. return 0;
  26. }
  27. /* AMD 756, for most chips (early revs), corrupts register
  28. * values on read ... so enable the vendor workaround.
  29. */
  30. static int ohci_quirk_amd756(struct usb_hcd *hcd)
  31. {
  32. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  33. ohci->flags = OHCI_QUIRK_AMD756;
  34. ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
  35. /* also erratum 10 (suspend/resume issues) */
  36. return broken_suspend(hcd);
  37. }
  38. /* Apple's OHCI driver has a lot of bizarre workarounds
  39. * for this chip. Evidently control and bulk lists
  40. * can get confused. (B&W G3 models, and ...)
  41. */
  42. static int ohci_quirk_opti(struct usb_hcd *hcd)
  43. {
  44. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  45. ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
  46. return 0;
  47. }
  48. /* Check for NSC87560. We have to look at the bridge (fn1) to
  49. * identify the USB (fn2). This quirk might apply to more or
  50. * even all NSC stuff.
  51. */
  52. static int ohci_quirk_ns(struct usb_hcd *hcd)
  53. {
  54. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  55. struct pci_dev *b;
  56. b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
  57. if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
  58. && b->vendor == PCI_VENDOR_ID_NS) {
  59. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  60. ohci->flags |= OHCI_QUIRK_SUPERIO;
  61. ohci_dbg (ohci, "Using NSC SuperIO setup\n");
  62. }
  63. pci_dev_put(b);
  64. return 0;
  65. }
  66. /* Check for Compaq's ZFMicro chipset, which needs short
  67. * delays before control or bulk queues get re-activated
  68. * in finish_unlinks()
  69. */
  70. static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
  71. {
  72. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  73. ohci->flags |= OHCI_QUIRK_ZFMICRO;
  74. ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
  75. return 0;
  76. }
  77. /* Check for Toshiba SCC OHCI which has big endian registers
  78. * and little endian in memory data structures
  79. */
  80. static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
  81. {
  82. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  83. /* That chip is only present in the southbridge of some
  84. * cell based platforms which are supposed to select
  85. * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
  86. * that was the case though.
  87. */
  88. #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
  89. ohci->flags |= OHCI_QUIRK_BE_MMIO;
  90. ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
  91. return 0;
  92. #else
  93. ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
  94. return -ENXIO;
  95. #endif
  96. }
  97. /* Check for NEC chip and apply quirk for allegedly lost interrupts.
  98. */
  99. static void ohci_quirk_nec_worker(struct work_struct *work)
  100. {
  101. struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
  102. int status;
  103. status = ohci_init(ohci);
  104. if (status != 0) {
  105. ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
  106. "ohci_init", status);
  107. return;
  108. }
  109. status = ohci_restart(ohci);
  110. if (status != 0)
  111. ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
  112. "ohci_restart", status);
  113. }
  114. static int ohci_quirk_nec(struct usb_hcd *hcd)
  115. {
  116. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  117. ohci->flags |= OHCI_QUIRK_NEC;
  118. INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
  119. ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
  120. return 0;
  121. }
  122. static int ohci_quirk_amd700(struct usb_hcd *hcd)
  123. {
  124. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  125. struct pci_dev *amd_smbus_dev;
  126. u8 rev;
  127. if (usb_amd_find_chipset_info())
  128. ohci->flags |= OHCI_QUIRK_AMD_PLL;
  129. amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
  130. PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
  131. if (!amd_smbus_dev)
  132. return 0;
  133. rev = amd_smbus_dev->revision;
  134. /* SB800 needs pre-fetch fix */
  135. if ((rev >= 0x40) && (rev <= 0x4f)) {
  136. ohci->flags |= OHCI_QUIRK_AMD_PREFETCH;
  137. ohci_dbg(ohci, "enabled AMD prefetch quirk\n");
  138. }
  139. pci_dev_put(amd_smbus_dev);
  140. amd_smbus_dev = NULL;
  141. return 0;
  142. }
  143. /* nVidia controllers continue to drive Reset signalling on the bus
  144. * even after system shutdown, wasting power. This flag tells the
  145. * shutdown routine to leave the controller OPERATIONAL instead of RESET.
  146. */
  147. static int ohci_quirk_nvidia_shutdown(struct usb_hcd *hcd)
  148. {
  149. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  150. ohci->flags |= OHCI_QUIRK_SHUTDOWN;
  151. ohci_dbg(ohci, "enabled nVidia shutdown quirk\n");
  152. return 0;
  153. }
  154. static void sb800_prefetch(struct ohci_hcd *ohci, int on)
  155. {
  156. struct pci_dev *pdev;
  157. u16 misc;
  158. pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
  159. pci_read_config_word(pdev, 0x50, &misc);
  160. if (on == 0)
  161. pci_write_config_word(pdev, 0x50, misc & 0xfcff);
  162. else
  163. pci_write_config_word(pdev, 0x50, misc | 0x0300);
  164. }
  165. /* List of quirks for OHCI */
  166. static const struct pci_device_id ohci_pci_quirks[] = {
  167. {
  168. PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
  169. .driver_data = (unsigned long)ohci_quirk_amd756,
  170. },
  171. {
  172. PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
  173. .driver_data = (unsigned long)ohci_quirk_opti,
  174. },
  175. {
  176. PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
  177. .driver_data = (unsigned long)ohci_quirk_ns,
  178. },
  179. {
  180. PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
  181. .driver_data = (unsigned long)ohci_quirk_zfmicro,
  182. },
  183. {
  184. PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
  185. .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
  186. },
  187. {
  188. PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
  189. .driver_data = (unsigned long)ohci_quirk_nec,
  190. },
  191. {
  192. /* Toshiba portege 4000 */
  193. .vendor = PCI_VENDOR_ID_AL,
  194. .device = 0x5237,
  195. .subvendor = PCI_VENDOR_ID_TOSHIBA,
  196. .subdevice = 0x0004,
  197. .driver_data = (unsigned long) broken_suspend,
  198. },
  199. {
  200. PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
  201. .driver_data = (unsigned long) broken_suspend,
  202. },
  203. {
  204. PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397),
  205. .driver_data = (unsigned long)ohci_quirk_amd700,
  206. },
  207. {
  208. PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398),
  209. .driver_data = (unsigned long)ohci_quirk_amd700,
  210. },
  211. {
  212. PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399),
  213. .driver_data = (unsigned long)ohci_quirk_amd700,
  214. },
  215. {
  216. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  217. .driver_data = (unsigned long) ohci_quirk_nvidia_shutdown,
  218. },
  219. /* FIXME for some of the early AMD 760 southbridges, OHCI
  220. * won't work at all. blacklist them.
  221. */
  222. {},
  223. };
  224. static int ohci_pci_reset (struct usb_hcd *hcd)
  225. {
  226. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  227. int ret = 0;
  228. if (hcd->self.controller) {
  229. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  230. const struct pci_device_id *quirk_id;
  231. quirk_id = pci_match_id(ohci_pci_quirks, pdev);
  232. if (quirk_id != NULL) {
  233. int (*quirk)(struct usb_hcd *ohci);
  234. quirk = (void *)quirk_id->driver_data;
  235. ret = quirk(hcd);
  236. }
  237. }
  238. if (ret == 0) {
  239. ohci_hcd_init (ohci);
  240. return ohci_init (ohci);
  241. }
  242. return ret;
  243. }
  244. static int __devinit ohci_pci_start (struct usb_hcd *hcd)
  245. {
  246. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  247. int ret;
  248. #ifdef CONFIG_PM /* avoid warnings about unused pdev */
  249. if (hcd->self.controller) {
  250. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  251. /* RWC may not be set for add-in PCI cards, since boot
  252. * firmware probably ignored them. This transfers PCI
  253. * PM wakeup capabilities.
  254. */
  255. if (device_can_wakeup(&pdev->dev))
  256. ohci->hc_control |= OHCI_CTRL_RWC;
  257. }
  258. #endif /* CONFIG_PM */
  259. ret = ohci_run (ohci);
  260. if (ret < 0) {
  261. ohci_err (ohci, "can't start\n");
  262. ohci_stop (hcd);
  263. }
  264. return ret;
  265. }
  266. #ifdef CONFIG_PM
  267. static int ohci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
  268. {
  269. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  270. unsigned long flags;
  271. int rc = 0;
  272. /* Root hub was already suspended. Disable irq emission and
  273. * mark HW unaccessible, bail out if RH has been resumed. Use
  274. * the spinlock to properly synchronize with possible pending
  275. * RH suspend or resume activity.
  276. *
  277. * This is still racy as hcd->state is manipulated outside of
  278. * any locks =P But that will be a different fix.
  279. */
  280. spin_lock_irqsave (&ohci->lock, flags);
  281. if (hcd->state != HC_STATE_SUSPENDED) {
  282. rc = -EINVAL;
  283. goto bail;
  284. }
  285. ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  286. (void)ohci_readl(ohci, &ohci->regs->intrdisable);
  287. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  288. bail:
  289. spin_unlock_irqrestore (&ohci->lock, flags);
  290. return rc;
  291. }
  292. static int ohci_pci_resume(struct usb_hcd *hcd, bool hibernated)
  293. {
  294. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  295. /* Make sure resume from hibernation re-enumerates everything */
  296. if (hibernated)
  297. ohci_usb_reset(hcd_to_ohci(hcd));
  298. ohci_finish_controller_resume(hcd);
  299. return 0;
  300. }
  301. #endif /* CONFIG_PM */
  302. /*-------------------------------------------------------------------------*/
  303. static const struct hc_driver ohci_pci_hc_driver = {
  304. .description = hcd_name,
  305. .product_desc = "OHCI Host Controller",
  306. .hcd_priv_size = sizeof(struct ohci_hcd),
  307. /*
  308. * generic hardware linkage
  309. */
  310. .irq = ohci_irq,
  311. .flags = HCD_MEMORY | HCD_USB11,
  312. /*
  313. * basic lifecycle operations
  314. */
  315. .reset = ohci_pci_reset,
  316. .start = ohci_pci_start,
  317. .stop = ohci_stop,
  318. .shutdown = ohci_shutdown,
  319. #ifdef CONFIG_PM
  320. .pci_suspend = ohci_pci_suspend,
  321. .pci_resume = ohci_pci_resume,
  322. #endif
  323. /*
  324. * managing i/o requests and associated device resources
  325. */
  326. .urb_enqueue = ohci_urb_enqueue,
  327. .urb_dequeue = ohci_urb_dequeue,
  328. .endpoint_disable = ohci_endpoint_disable,
  329. /*
  330. * scheduling support
  331. */
  332. .get_frame_number = ohci_get_frame,
  333. /*
  334. * root hub support
  335. */
  336. .hub_status_data = ohci_hub_status_data,
  337. .hub_control = ohci_hub_control,
  338. #ifdef CONFIG_PM
  339. .bus_suspend = ohci_bus_suspend,
  340. .bus_resume = ohci_bus_resume,
  341. #endif
  342. .start_port_reset = ohci_start_port_reset,
  343. };
  344. /*-------------------------------------------------------------------------*/
  345. static const struct pci_device_id pci_ids [] = { {
  346. /* handle any USB OHCI controller */
  347. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
  348. .driver_data = (unsigned long) &ohci_pci_hc_driver,
  349. }, { /* end: all zeroes */ }
  350. };
  351. MODULE_DEVICE_TABLE (pci, pci_ids);
  352. /* pci driver glue; this is a "new style" PCI driver module */
  353. static struct pci_driver ohci_pci_driver = {
  354. .name = (char *) hcd_name,
  355. .id_table = pci_ids,
  356. .probe = usb_hcd_pci_probe,
  357. .remove = usb_hcd_pci_remove,
  358. .shutdown = usb_hcd_pci_shutdown,
  359. #ifdef CONFIG_PM_SLEEP
  360. .driver = {
  361. .pm = &usb_hcd_pci_pm_ops
  362. },
  363. #endif
  364. };