ohci-hcd.c 33 KB

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  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * [ Initialisation is based on Linus' ]
  8. * [ uhci code and gregs ohci fragments ]
  9. * [ (C) Copyright 1999 Linus Torvalds ]
  10. * [ (C) Copyright 1999 Gregory P. Smith]
  11. *
  12. *
  13. * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  14. * interfaces (though some non-x86 Intel chips use it). It supports
  15. * smarter hardware than UHCI. A download link for the spec available
  16. * through the http://www.usb.org website.
  17. *
  18. * This file is licenced under the GPL.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/moduleparam.h>
  22. #include <linux/pci.h>
  23. #include <linux/kernel.h>
  24. #include <linux/delay.h>
  25. #include <linux/ioport.h>
  26. #include <linux/sched.h>
  27. #include <linux/slab.h>
  28. #include <linux/errno.h>
  29. #include <linux/init.h>
  30. #include <linux/timer.h>
  31. #include <linux/list.h>
  32. #include <linux/usb.h>
  33. #include <linux/usb/otg.h>
  34. #include <linux/usb/hcd.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/dmapool.h>
  37. #include <linux/workqueue.h>
  38. #include <linux/debugfs.h>
  39. #include <asm/io.h>
  40. #include <asm/irq.h>
  41. #include <asm/system.h>
  42. #include <asm/unaligned.h>
  43. #include <asm/byteorder.h>
  44. #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  45. #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  46. /*-------------------------------------------------------------------------*/
  47. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  48. /* For initializing controller (mask in an HCFS mode too) */
  49. #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
  50. #define OHCI_INTR_INIT \
  51. (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  52. | OHCI_INTR_RD | OHCI_INTR_WDH)
  53. #ifdef __hppa__
  54. /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  55. #define IR_DISABLE
  56. #endif
  57. #ifdef CONFIG_ARCH_OMAP
  58. /* OMAP doesn't support IR (no SMM; not needed) */
  59. #define IR_DISABLE
  60. #endif
  61. /*-------------------------------------------------------------------------*/
  62. static const char hcd_name [] = "ohci_hcd";
  63. #define STATECHANGE_DELAY msecs_to_jiffies(300)
  64. #include "ohci.h"
  65. #include "pci-quirks.h"
  66. static void ohci_dump (struct ohci_hcd *ohci, int verbose);
  67. static int ohci_init (struct ohci_hcd *ohci);
  68. static void ohci_stop (struct usb_hcd *hcd);
  69. #if defined(CONFIG_PM) || defined(CONFIG_PCI)
  70. static int ohci_restart (struct ohci_hcd *ohci);
  71. #endif
  72. #ifdef CONFIG_PCI
  73. static void sb800_prefetch(struct ohci_hcd *ohci, int on);
  74. #else
  75. static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
  76. {
  77. return;
  78. }
  79. #endif
  80. #include "ohci-hub.c"
  81. #include "ohci-dbg.c"
  82. #include "ohci-mem.c"
  83. #include "ohci-q.c"
  84. /*
  85. * On architectures with edge-triggered interrupts we must never return
  86. * IRQ_NONE.
  87. */
  88. #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
  89. #define IRQ_NOTMINE IRQ_HANDLED
  90. #else
  91. #define IRQ_NOTMINE IRQ_NONE
  92. #endif
  93. /* Some boards misreport power switching/overcurrent */
  94. static int distrust_firmware = 1;
  95. module_param (distrust_firmware, bool, 0);
  96. MODULE_PARM_DESC (distrust_firmware,
  97. "true to distrust firmware power/overcurrent setup");
  98. /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
  99. static int no_handshake = 0;
  100. module_param (no_handshake, bool, 0);
  101. MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
  102. /*-------------------------------------------------------------------------*/
  103. /*
  104. * queue up an urb for anything except the root hub
  105. */
  106. static int ohci_urb_enqueue (
  107. struct usb_hcd *hcd,
  108. struct urb *urb,
  109. gfp_t mem_flags
  110. ) {
  111. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  112. struct ed *ed;
  113. urb_priv_t *urb_priv;
  114. unsigned int pipe = urb->pipe;
  115. int i, size = 0;
  116. unsigned long flags;
  117. int retval = 0;
  118. #ifdef OHCI_VERBOSE_DEBUG
  119. urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
  120. #endif
  121. /* every endpoint has a ed, locate and maybe (re)initialize it */
  122. if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
  123. return -ENOMEM;
  124. /* for the private part of the URB we need the number of TDs (size) */
  125. switch (ed->type) {
  126. case PIPE_CONTROL:
  127. /* td_submit_urb() doesn't yet handle these */
  128. if (urb->transfer_buffer_length > 4096)
  129. return -EMSGSIZE;
  130. /* 1 TD for setup, 1 for ACK, plus ... */
  131. size = 2;
  132. /* FALLTHROUGH */
  133. // case PIPE_INTERRUPT:
  134. // case PIPE_BULK:
  135. default:
  136. /* one TD for every 4096 Bytes (can be upto 8K) */
  137. size += urb->transfer_buffer_length / 4096;
  138. /* ... and for any remaining bytes ... */
  139. if ((urb->transfer_buffer_length % 4096) != 0)
  140. size++;
  141. /* ... and maybe a zero length packet to wrap it up */
  142. if (size == 0)
  143. size++;
  144. else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
  145. && (urb->transfer_buffer_length
  146. % usb_maxpacket (urb->dev, pipe,
  147. usb_pipeout (pipe))) == 0)
  148. size++;
  149. break;
  150. case PIPE_ISOCHRONOUS: /* number of packets from URB */
  151. size = urb->number_of_packets;
  152. break;
  153. }
  154. /* allocate the private part of the URB */
  155. urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
  156. mem_flags);
  157. if (!urb_priv)
  158. return -ENOMEM;
  159. INIT_LIST_HEAD (&urb_priv->pending);
  160. urb_priv->length = size;
  161. urb_priv->ed = ed;
  162. /* allocate the TDs (deferring hash chain updates) */
  163. for (i = 0; i < size; i++) {
  164. urb_priv->td [i] = td_alloc (ohci, mem_flags);
  165. if (!urb_priv->td [i]) {
  166. urb_priv->length = i;
  167. urb_free_priv (ohci, urb_priv);
  168. return -ENOMEM;
  169. }
  170. }
  171. spin_lock_irqsave (&ohci->lock, flags);
  172. /* don't submit to a dead HC */
  173. if (!HCD_HW_ACCESSIBLE(hcd)) {
  174. retval = -ENODEV;
  175. goto fail;
  176. }
  177. if (!HC_IS_RUNNING(hcd->state)) {
  178. retval = -ENODEV;
  179. goto fail;
  180. }
  181. retval = usb_hcd_link_urb_to_ep(hcd, urb);
  182. if (retval)
  183. goto fail;
  184. /* schedule the ed if needed */
  185. if (ed->state == ED_IDLE) {
  186. retval = ed_schedule (ohci, ed);
  187. if (retval < 0) {
  188. usb_hcd_unlink_urb_from_ep(hcd, urb);
  189. goto fail;
  190. }
  191. if (ed->type == PIPE_ISOCHRONOUS) {
  192. u16 frame = ohci_frame_no(ohci);
  193. /* delay a few frames before the first TD */
  194. frame += max_t (u16, 8, ed->interval);
  195. frame &= ~(ed->interval - 1);
  196. frame |= ed->branch;
  197. urb->start_frame = frame;
  198. /* yes, only URB_ISO_ASAP is supported, and
  199. * urb->start_frame is never used as input.
  200. */
  201. }
  202. } else if (ed->type == PIPE_ISOCHRONOUS)
  203. urb->start_frame = ed->last_iso + ed->interval;
  204. /* fill the TDs and link them to the ed; and
  205. * enable that part of the schedule, if needed
  206. * and update count of queued periodic urbs
  207. */
  208. urb->hcpriv = urb_priv;
  209. td_submit_urb (ohci, urb);
  210. fail:
  211. if (retval)
  212. urb_free_priv (ohci, urb_priv);
  213. spin_unlock_irqrestore (&ohci->lock, flags);
  214. return retval;
  215. }
  216. /*
  217. * decouple the URB from the HC queues (TDs, urb_priv).
  218. * reporting is always done
  219. * asynchronously, and we might be dealing with an urb that's
  220. * partially transferred, or an ED with other urbs being unlinked.
  221. */
  222. static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  223. {
  224. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  225. unsigned long flags;
  226. int rc;
  227. #ifdef OHCI_VERBOSE_DEBUG
  228. urb_print(urb, "UNLINK", 1, status);
  229. #endif
  230. spin_lock_irqsave (&ohci->lock, flags);
  231. rc = usb_hcd_check_unlink_urb(hcd, urb, status);
  232. if (rc) {
  233. ; /* Do nothing */
  234. } else if (HC_IS_RUNNING(hcd->state)) {
  235. urb_priv_t *urb_priv;
  236. /* Unless an IRQ completed the unlink while it was being
  237. * handed to us, flag it for unlink and giveback, and force
  238. * some upcoming INTR_SF to call finish_unlinks()
  239. */
  240. urb_priv = urb->hcpriv;
  241. if (urb_priv) {
  242. if (urb_priv->ed->state == ED_OPER)
  243. start_ed_unlink (ohci, urb_priv->ed);
  244. }
  245. } else {
  246. /*
  247. * with HC dead, we won't respect hc queue pointers
  248. * any more ... just clean up every urb's memory.
  249. */
  250. if (urb->hcpriv)
  251. finish_urb(ohci, urb, status);
  252. }
  253. spin_unlock_irqrestore (&ohci->lock, flags);
  254. return rc;
  255. }
  256. /*-------------------------------------------------------------------------*/
  257. /* frees config/altsetting state for endpoints,
  258. * including ED memory, dummy TD, and bulk/intr data toggle
  259. */
  260. static void
  261. ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
  262. {
  263. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  264. unsigned long flags;
  265. struct ed *ed = ep->hcpriv;
  266. unsigned limit = 1000;
  267. /* ASSERT: any requests/urbs are being unlinked */
  268. /* ASSERT: nobody can be submitting urbs for this any more */
  269. if (!ed)
  270. return;
  271. rescan:
  272. spin_lock_irqsave (&ohci->lock, flags);
  273. if (!HC_IS_RUNNING (hcd->state)) {
  274. sanitize:
  275. ed->state = ED_IDLE;
  276. if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
  277. ohci->eds_scheduled--;
  278. finish_unlinks (ohci, 0);
  279. }
  280. switch (ed->state) {
  281. case ED_UNLINK: /* wait for hw to finish? */
  282. /* major IRQ delivery trouble loses INTR_SF too... */
  283. if (limit-- == 0) {
  284. ohci_warn(ohci, "ED unlink timeout\n");
  285. if (quirk_zfmicro(ohci)) {
  286. ohci_warn(ohci, "Attempting ZF TD recovery\n");
  287. ohci->ed_to_check = ed;
  288. ohci->zf_delay = 2;
  289. }
  290. goto sanitize;
  291. }
  292. spin_unlock_irqrestore (&ohci->lock, flags);
  293. schedule_timeout_uninterruptible(1);
  294. goto rescan;
  295. case ED_IDLE: /* fully unlinked */
  296. if (list_empty (&ed->td_list)) {
  297. td_free (ohci, ed->dummy);
  298. ed_free (ohci, ed);
  299. break;
  300. }
  301. /* else FALL THROUGH */
  302. default:
  303. /* caller was supposed to have unlinked any requests;
  304. * that's not our job. can't recover; must leak ed.
  305. */
  306. ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
  307. ed, ep->desc.bEndpointAddress, ed->state,
  308. list_empty (&ed->td_list) ? "" : " (has tds)");
  309. td_free (ohci, ed->dummy);
  310. break;
  311. }
  312. ep->hcpriv = NULL;
  313. spin_unlock_irqrestore (&ohci->lock, flags);
  314. }
  315. static int ohci_get_frame (struct usb_hcd *hcd)
  316. {
  317. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  318. return ohci_frame_no(ohci);
  319. }
  320. static void ohci_usb_reset (struct ohci_hcd *ohci)
  321. {
  322. ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
  323. ohci->hc_control &= OHCI_CTRL_RWC;
  324. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  325. }
  326. /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
  327. * other cases where the next software may expect clean state from the
  328. * "firmware". this is bus-neutral, unlike shutdown() methods.
  329. */
  330. static void
  331. ohci_shutdown (struct usb_hcd *hcd)
  332. {
  333. struct ohci_hcd *ohci;
  334. ohci = hcd_to_ohci (hcd);
  335. ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  336. ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
  337. /* If the SHUTDOWN quirk is set, don't put the controller in RESET */
  338. ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ?
  339. OHCI_CTRL_RWC | OHCI_CTRL_HCFS :
  340. OHCI_CTRL_RWC);
  341. ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
  342. /* flush the writes */
  343. (void) ohci_readl (ohci, &ohci->regs->control);
  344. }
  345. static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
  346. {
  347. return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
  348. && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
  349. == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
  350. && !list_empty(&ed->td_list);
  351. }
  352. /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
  353. * an interrupt TD but neglects to add it to the donelist. On systems with
  354. * this chipset, we need to periodically check the state of the queues to look
  355. * for such "lost" TDs.
  356. */
  357. static void unlink_watchdog_func(unsigned long _ohci)
  358. {
  359. unsigned long flags;
  360. unsigned max;
  361. unsigned seen_count = 0;
  362. unsigned i;
  363. struct ed **seen = NULL;
  364. struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
  365. spin_lock_irqsave(&ohci->lock, flags);
  366. max = ohci->eds_scheduled;
  367. if (!max)
  368. goto done;
  369. if (ohci->ed_to_check)
  370. goto out;
  371. seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
  372. if (!seen)
  373. goto out;
  374. for (i = 0; i < NUM_INTS; i++) {
  375. struct ed *ed = ohci->periodic[i];
  376. while (ed) {
  377. unsigned temp;
  378. /* scan this branch of the periodic schedule tree */
  379. for (temp = 0; temp < seen_count; temp++) {
  380. if (seen[temp] == ed) {
  381. /* we've checked it and what's after */
  382. ed = NULL;
  383. break;
  384. }
  385. }
  386. if (!ed)
  387. break;
  388. seen[seen_count++] = ed;
  389. if (!check_ed(ohci, ed)) {
  390. ed = ed->ed_next;
  391. continue;
  392. }
  393. /* HC's TD list is empty, but HCD sees at least one
  394. * TD that's not been sent through the donelist.
  395. */
  396. ohci->ed_to_check = ed;
  397. ohci->zf_delay = 2;
  398. /* The HC may wait until the next frame to report the
  399. * TD as done through the donelist and INTR_WDH. (We
  400. * just *assume* it's not a multi-TD interrupt URB;
  401. * those could defer the IRQ more than one frame, using
  402. * DI...) Check again after the next INTR_SF.
  403. */
  404. ohci_writel(ohci, OHCI_INTR_SF,
  405. &ohci->regs->intrstatus);
  406. ohci_writel(ohci, OHCI_INTR_SF,
  407. &ohci->regs->intrenable);
  408. /* flush those writes */
  409. (void) ohci_readl(ohci, &ohci->regs->control);
  410. goto out;
  411. }
  412. }
  413. out:
  414. kfree(seen);
  415. if (ohci->eds_scheduled)
  416. mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
  417. done:
  418. spin_unlock_irqrestore(&ohci->lock, flags);
  419. }
  420. /*-------------------------------------------------------------------------*
  421. * HC functions
  422. *-------------------------------------------------------------------------*/
  423. /* init memory, and kick BIOS/SMM off */
  424. static int ohci_init (struct ohci_hcd *ohci)
  425. {
  426. int ret;
  427. struct usb_hcd *hcd = ohci_to_hcd(ohci);
  428. if (distrust_firmware)
  429. ohci->flags |= OHCI_QUIRK_HUB_POWER;
  430. disable (ohci);
  431. ohci->regs = hcd->regs;
  432. /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
  433. * was never needed for most non-PCI systems ... remove the code?
  434. */
  435. #ifndef IR_DISABLE
  436. /* SMM owns the HC? not for long! */
  437. if (!no_handshake && ohci_readl (ohci,
  438. &ohci->regs->control) & OHCI_CTRL_IR) {
  439. u32 temp;
  440. ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
  441. /* this timeout is arbitrary. we make it long, so systems
  442. * depending on usb keyboards may be usable even if the
  443. * BIOS/SMM code seems pretty broken.
  444. */
  445. temp = 500; /* arbitrary: five seconds */
  446. ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
  447. ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
  448. while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
  449. msleep (10);
  450. if (--temp == 0) {
  451. ohci_err (ohci, "USB HC takeover failed!"
  452. " (BIOS/SMM bug)\n");
  453. return -EBUSY;
  454. }
  455. }
  456. ohci_usb_reset (ohci);
  457. }
  458. #endif
  459. /* Disable HC interrupts */
  460. ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  461. /* flush the writes, and save key bits like RWC */
  462. if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
  463. ohci->hc_control |= OHCI_CTRL_RWC;
  464. /* Read the number of ports unless overridden */
  465. if (ohci->num_ports == 0)
  466. ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
  467. if (ohci->hcca)
  468. return 0;
  469. ohci->hcca = dma_alloc_coherent (hcd->self.controller,
  470. sizeof *ohci->hcca, &ohci->hcca_dma, 0);
  471. if (!ohci->hcca)
  472. return -ENOMEM;
  473. if ((ret = ohci_mem_init (ohci)) < 0)
  474. ohci_stop (hcd);
  475. else {
  476. create_debug_files (ohci);
  477. }
  478. return ret;
  479. }
  480. /*-------------------------------------------------------------------------*/
  481. /* Start an OHCI controller, set the BUS operational
  482. * resets USB and controller
  483. * enable interrupts
  484. */
  485. static int ohci_run (struct ohci_hcd *ohci)
  486. {
  487. u32 mask, val;
  488. int first = ohci->fminterval == 0;
  489. struct usb_hcd *hcd = ohci_to_hcd(ohci);
  490. disable (ohci);
  491. /* boot firmware should have set this up (5.1.1.3.1) */
  492. if (first) {
  493. val = ohci_readl (ohci, &ohci->regs->fminterval);
  494. ohci->fminterval = val & 0x3fff;
  495. if (ohci->fminterval != FI)
  496. ohci_dbg (ohci, "fminterval delta %d\n",
  497. ohci->fminterval - FI);
  498. ohci->fminterval |= FSMP (ohci->fminterval) << 16;
  499. /* also: power/overcurrent flags in roothub.a */
  500. }
  501. /* Reset USB nearly "by the book". RemoteWakeupConnected has
  502. * to be checked in case boot firmware (BIOS/SMM/...) has set up
  503. * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
  504. * If the bus glue detected wakeup capability then it should
  505. * already be enabled; if so we'll just enable it again.
  506. */
  507. if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
  508. device_set_wakeup_capable(hcd->self.controller, 1);
  509. switch (ohci->hc_control & OHCI_CTRL_HCFS) {
  510. case OHCI_USB_OPER:
  511. val = 0;
  512. break;
  513. case OHCI_USB_SUSPEND:
  514. case OHCI_USB_RESUME:
  515. ohci->hc_control &= OHCI_CTRL_RWC;
  516. ohci->hc_control |= OHCI_USB_RESUME;
  517. val = 10 /* msec wait */;
  518. break;
  519. // case OHCI_USB_RESET:
  520. default:
  521. ohci->hc_control &= OHCI_CTRL_RWC;
  522. ohci->hc_control |= OHCI_USB_RESET;
  523. val = 50 /* msec wait */;
  524. break;
  525. }
  526. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  527. // flush the writes
  528. (void) ohci_readl (ohci, &ohci->regs->control);
  529. msleep(val);
  530. memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
  531. /* 2msec timelimit here means no irqs/preempt */
  532. spin_lock_irq (&ohci->lock);
  533. retry:
  534. /* HC Reset requires max 10 us delay */
  535. ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
  536. val = 30; /* ... allow extra time */
  537. while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  538. if (--val == 0) {
  539. spin_unlock_irq (&ohci->lock);
  540. ohci_err (ohci, "USB HC reset timed out!\n");
  541. return -1;
  542. }
  543. udelay (1);
  544. }
  545. /* now we're in the SUSPEND state ... must go OPERATIONAL
  546. * within 2msec else HC enters RESUME
  547. *
  548. * ... but some hardware won't init fmInterval "by the book"
  549. * (SiS, OPTi ...), so reset again instead. SiS doesn't need
  550. * this if we write fmInterval after we're OPERATIONAL.
  551. * Unclear about ALi, ServerWorks, and others ... this could
  552. * easily be a longstanding bug in chip init on Linux.
  553. */
  554. if (ohci->flags & OHCI_QUIRK_INITRESET) {
  555. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  556. // flush those writes
  557. (void) ohci_readl (ohci, &ohci->regs->control);
  558. }
  559. /* Tell the controller where the control and bulk lists are
  560. * The lists are empty now. */
  561. ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
  562. ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
  563. /* a reset clears this */
  564. ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
  565. periodic_reinit (ohci);
  566. /* some OHCI implementations are finicky about how they init.
  567. * bogus values here mean not even enumeration could work.
  568. */
  569. if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
  570. || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
  571. if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
  572. ohci->flags |= OHCI_QUIRK_INITRESET;
  573. ohci_dbg (ohci, "enabling initreset quirk\n");
  574. goto retry;
  575. }
  576. spin_unlock_irq (&ohci->lock);
  577. ohci_err (ohci, "init err (%08x %04x)\n",
  578. ohci_readl (ohci, &ohci->regs->fminterval),
  579. ohci_readl (ohci, &ohci->regs->periodicstart));
  580. return -EOVERFLOW;
  581. }
  582. /* use rhsc irqs after khubd is fully initialized */
  583. set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  584. hcd->uses_new_polling = 1;
  585. /* start controller operations */
  586. ohci->hc_control &= OHCI_CTRL_RWC;
  587. ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
  588. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  589. hcd->state = HC_STATE_RUNNING;
  590. /* wake on ConnectStatusChange, matching external hubs */
  591. ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
  592. /* Choose the interrupts we care about now, others later on demand */
  593. mask = OHCI_INTR_INIT;
  594. ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
  595. ohci_writel (ohci, mask, &ohci->regs->intrenable);
  596. /* handle root hub init quirks ... */
  597. val = roothub_a (ohci);
  598. val &= ~(RH_A_PSM | RH_A_OCPM);
  599. if (ohci->flags & OHCI_QUIRK_SUPERIO) {
  600. /* NSC 87560 and maybe others */
  601. val |= RH_A_NOCP;
  602. val &= ~(RH_A_POTPGT | RH_A_NPS);
  603. ohci_writel (ohci, val, &ohci->regs->roothub.a);
  604. } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
  605. (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
  606. /* hub power always on; required for AMD-756 and some
  607. * Mac platforms. ganged overcurrent reporting, if any.
  608. */
  609. val |= RH_A_NPS;
  610. ohci_writel (ohci, val, &ohci->regs->roothub.a);
  611. }
  612. ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
  613. ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
  614. &ohci->regs->roothub.b);
  615. // flush those writes
  616. (void) ohci_readl (ohci, &ohci->regs->control);
  617. ohci->next_statechange = jiffies + STATECHANGE_DELAY;
  618. spin_unlock_irq (&ohci->lock);
  619. // POTPGT delay is bits 24-31, in 2 ms units.
  620. mdelay ((val >> 23) & 0x1fe);
  621. hcd->state = HC_STATE_RUNNING;
  622. if (quirk_zfmicro(ohci)) {
  623. /* Create timer to watch for bad queue state on ZF Micro */
  624. setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
  625. (unsigned long) ohci);
  626. ohci->eds_scheduled = 0;
  627. ohci->ed_to_check = NULL;
  628. }
  629. ohci_dump (ohci, 1);
  630. return 0;
  631. }
  632. /*-------------------------------------------------------------------------*/
  633. /* an interrupt happens */
  634. static irqreturn_t ohci_irq (struct usb_hcd *hcd)
  635. {
  636. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  637. struct ohci_regs __iomem *regs = ohci->regs;
  638. int ints;
  639. /* Read interrupt status (and flush pending writes). We ignore the
  640. * optimization of checking the LSB of hcca->done_head; it doesn't
  641. * work on all systems (edge triggering for OHCI can be a factor).
  642. */
  643. ints = ohci_readl(ohci, &regs->intrstatus);
  644. /* Check for an all 1's result which is a typical consequence
  645. * of dead, unclocked, or unplugged (CardBus...) devices
  646. */
  647. if (ints == ~(u32)0) {
  648. disable (ohci);
  649. ohci_dbg (ohci, "device removed!\n");
  650. return IRQ_HANDLED;
  651. }
  652. /* We only care about interrupts that are enabled */
  653. ints &= ohci_readl(ohci, &regs->intrenable);
  654. /* interrupt for some other device? */
  655. if (ints == 0)
  656. return IRQ_NOTMINE;
  657. if (ints & OHCI_INTR_UE) {
  658. // e.g. due to PCI Master/Target Abort
  659. if (quirk_nec(ohci)) {
  660. /* Workaround for a silicon bug in some NEC chips used
  661. * in Apple's PowerBooks. Adapted from Darwin code.
  662. */
  663. ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
  664. ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
  665. schedule_work (&ohci->nec_work);
  666. } else {
  667. disable (ohci);
  668. ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
  669. }
  670. ohci_dump (ohci, 1);
  671. ohci_usb_reset (ohci);
  672. }
  673. if (ints & OHCI_INTR_RHSC) {
  674. ohci_vdbg(ohci, "rhsc\n");
  675. ohci->next_statechange = jiffies + STATECHANGE_DELAY;
  676. ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
  677. &regs->intrstatus);
  678. /* NOTE: Vendors didn't always make the same implementation
  679. * choices for RHSC. Many followed the spec; RHSC triggers
  680. * on an edge, like setting and maybe clearing a port status
  681. * change bit. With others it's level-triggered, active
  682. * until khubd clears all the port status change bits. We'll
  683. * always disable it here and rely on polling until khubd
  684. * re-enables it.
  685. */
  686. ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
  687. usb_hcd_poll_rh_status(hcd);
  688. }
  689. /* For connect and disconnect events, we expect the controller
  690. * to turn on RHSC along with RD. But for remote wakeup events
  691. * this might not happen.
  692. */
  693. else if (ints & OHCI_INTR_RD) {
  694. ohci_vdbg(ohci, "resume detect\n");
  695. ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
  696. set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  697. if (ohci->autostop) {
  698. spin_lock (&ohci->lock);
  699. ohci_rh_resume (ohci);
  700. spin_unlock (&ohci->lock);
  701. } else
  702. usb_hcd_resume_root_hub(hcd);
  703. }
  704. if (ints & OHCI_INTR_WDH) {
  705. spin_lock (&ohci->lock);
  706. dl_done_list (ohci);
  707. spin_unlock (&ohci->lock);
  708. }
  709. if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
  710. spin_lock(&ohci->lock);
  711. if (ohci->ed_to_check) {
  712. struct ed *ed = ohci->ed_to_check;
  713. if (check_ed(ohci, ed)) {
  714. /* HC thinks the TD list is empty; HCD knows
  715. * at least one TD is outstanding
  716. */
  717. if (--ohci->zf_delay == 0) {
  718. struct td *td = list_entry(
  719. ed->td_list.next,
  720. struct td, td_list);
  721. ohci_warn(ohci,
  722. "Reclaiming orphan TD %p\n",
  723. td);
  724. takeback_td(ohci, td);
  725. ohci->ed_to_check = NULL;
  726. }
  727. } else
  728. ohci->ed_to_check = NULL;
  729. }
  730. spin_unlock(&ohci->lock);
  731. }
  732. /* could track INTR_SO to reduce available PCI/... bandwidth */
  733. /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
  734. * when there's still unlinking to be done (next frame).
  735. */
  736. spin_lock (&ohci->lock);
  737. if (ohci->ed_rm_list)
  738. finish_unlinks (ohci, ohci_frame_no(ohci));
  739. if ((ints & OHCI_INTR_SF) != 0
  740. && !ohci->ed_rm_list
  741. && !ohci->ed_to_check
  742. && HC_IS_RUNNING(hcd->state))
  743. ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
  744. spin_unlock (&ohci->lock);
  745. if (HC_IS_RUNNING(hcd->state)) {
  746. ohci_writel (ohci, ints, &regs->intrstatus);
  747. ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
  748. // flush those writes
  749. (void) ohci_readl (ohci, &ohci->regs->control);
  750. }
  751. return IRQ_HANDLED;
  752. }
  753. /*-------------------------------------------------------------------------*/
  754. static void ohci_stop (struct usb_hcd *hcd)
  755. {
  756. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  757. ohci_dump (ohci, 1);
  758. if (quirk_nec(ohci))
  759. flush_work_sync(&ohci->nec_work);
  760. ohci_usb_reset (ohci);
  761. ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  762. free_irq(hcd->irq, hcd);
  763. hcd->irq = -1;
  764. if (quirk_zfmicro(ohci))
  765. del_timer(&ohci->unlink_watchdog);
  766. if (quirk_amdiso(ohci))
  767. usb_amd_dev_put();
  768. remove_debug_files (ohci);
  769. ohci_mem_cleanup (ohci);
  770. if (ohci->hcca) {
  771. dma_free_coherent (hcd->self.controller,
  772. sizeof *ohci->hcca,
  773. ohci->hcca, ohci->hcca_dma);
  774. ohci->hcca = NULL;
  775. ohci->hcca_dma = 0;
  776. }
  777. }
  778. /*-------------------------------------------------------------------------*/
  779. #if defined(CONFIG_PM) || defined(CONFIG_PCI)
  780. /* must not be called from interrupt context */
  781. static int ohci_restart (struct ohci_hcd *ohci)
  782. {
  783. int temp;
  784. int i;
  785. struct urb_priv *priv;
  786. spin_lock_irq(&ohci->lock);
  787. disable (ohci);
  788. /* Recycle any "live" eds/tds (and urbs). */
  789. if (!list_empty (&ohci->pending))
  790. ohci_dbg(ohci, "abort schedule...\n");
  791. list_for_each_entry (priv, &ohci->pending, pending) {
  792. struct urb *urb = priv->td[0]->urb;
  793. struct ed *ed = priv->ed;
  794. switch (ed->state) {
  795. case ED_OPER:
  796. ed->state = ED_UNLINK;
  797. ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
  798. ed_deschedule (ohci, ed);
  799. ed->ed_next = ohci->ed_rm_list;
  800. ed->ed_prev = NULL;
  801. ohci->ed_rm_list = ed;
  802. /* FALLTHROUGH */
  803. case ED_UNLINK:
  804. break;
  805. default:
  806. ohci_dbg(ohci, "bogus ed %p state %d\n",
  807. ed, ed->state);
  808. }
  809. if (!urb->unlinked)
  810. urb->unlinked = -ESHUTDOWN;
  811. }
  812. finish_unlinks (ohci, 0);
  813. spin_unlock_irq(&ohci->lock);
  814. /* paranoia, in case that didn't work: */
  815. /* empty the interrupt branches */
  816. for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
  817. for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
  818. /* no EDs to remove */
  819. ohci->ed_rm_list = NULL;
  820. /* empty control and bulk lists */
  821. ohci->ed_controltail = NULL;
  822. ohci->ed_bulktail = NULL;
  823. if ((temp = ohci_run (ohci)) < 0) {
  824. ohci_err (ohci, "can't restart, %d\n", temp);
  825. return temp;
  826. }
  827. ohci_dbg(ohci, "restart complete\n");
  828. return 0;
  829. }
  830. #endif
  831. /*-------------------------------------------------------------------------*/
  832. MODULE_AUTHOR (DRIVER_AUTHOR);
  833. MODULE_DESCRIPTION(DRIVER_DESC);
  834. MODULE_LICENSE ("GPL");
  835. #ifdef CONFIG_PCI
  836. #include "ohci-pci.c"
  837. #define PCI_DRIVER ohci_pci_driver
  838. #endif
  839. #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
  840. #include "ohci-sa1111.c"
  841. #define SA1111_DRIVER ohci_hcd_sa1111_driver
  842. #endif
  843. #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
  844. #include "ohci-s3c2410.c"
  845. #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
  846. #endif
  847. #ifdef CONFIG_USB_OHCI_HCD_OMAP1
  848. #include "ohci-omap.c"
  849. #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
  850. #endif
  851. #ifdef CONFIG_USB_OHCI_HCD_OMAP3
  852. #include "ohci-omap3.c"
  853. #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
  854. #endif
  855. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  856. #include "ohci-pxa27x.c"
  857. #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
  858. #endif
  859. #ifdef CONFIG_ARCH_EP93XX
  860. #include "ohci-ep93xx.c"
  861. #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
  862. #endif
  863. #ifdef CONFIG_MIPS_ALCHEMY
  864. #include "ohci-au1xxx.c"
  865. #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
  866. #endif
  867. #ifdef CONFIG_PNX8550
  868. #include "ohci-pnx8550.c"
  869. #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
  870. #endif
  871. #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
  872. #include "ohci-ppc-soc.c"
  873. #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
  874. #endif
  875. #ifdef CONFIG_ARCH_AT91
  876. #include "ohci-at91.c"
  877. #define PLATFORM_DRIVER ohci_hcd_at91_driver
  878. #endif
  879. #ifdef CONFIG_ARCH_PNX4008
  880. #include "ohci-pnx4008.c"
  881. #define PLATFORM_DRIVER usb_hcd_pnx4008_driver
  882. #endif
  883. #ifdef CONFIG_ARCH_DAVINCI_DA8XX
  884. #include "ohci-da8xx.c"
  885. #define PLATFORM_DRIVER ohci_hcd_da8xx_driver
  886. #endif
  887. #ifdef CONFIG_USB_OHCI_SH
  888. #include "ohci-sh.c"
  889. #define PLATFORM_DRIVER ohci_hcd_sh_driver
  890. #endif
  891. #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
  892. #include "ohci-ppc-of.c"
  893. #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
  894. #endif
  895. #ifdef CONFIG_PLAT_SPEAR
  896. #include "ohci-spear.c"
  897. #define PLATFORM_DRIVER spear_ohci_hcd_driver
  898. #endif
  899. #ifdef CONFIG_PPC_PS3
  900. #include "ohci-ps3.c"
  901. #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
  902. #endif
  903. #ifdef CONFIG_USB_OHCI_HCD_SSB
  904. #include "ohci-ssb.c"
  905. #define SSB_OHCI_DRIVER ssb_ohci_driver
  906. #endif
  907. #ifdef CONFIG_MFD_SM501
  908. #include "ohci-sm501.c"
  909. #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
  910. #endif
  911. #ifdef CONFIG_MFD_TC6393XB
  912. #include "ohci-tmio.c"
  913. #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
  914. #endif
  915. #ifdef CONFIG_MACH_JZ4740
  916. #include "ohci-jz4740.c"
  917. #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
  918. #endif
  919. #ifdef CONFIG_USB_OCTEON_OHCI
  920. #include "ohci-octeon.c"
  921. #define PLATFORM_DRIVER ohci_octeon_driver
  922. #endif
  923. #ifdef CONFIG_USB_CNS3XXX_OHCI
  924. #include "ohci-cns3xxx.c"
  925. #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver
  926. #endif
  927. #if !defined(PCI_DRIVER) && \
  928. !defined(PLATFORM_DRIVER) && \
  929. !defined(OMAP1_PLATFORM_DRIVER) && \
  930. !defined(OMAP3_PLATFORM_DRIVER) && \
  931. !defined(OF_PLATFORM_DRIVER) && \
  932. !defined(SA1111_DRIVER) && \
  933. !defined(PS3_SYSTEM_BUS_DRIVER) && \
  934. !defined(SM501_OHCI_DRIVER) && \
  935. !defined(TMIO_OHCI_DRIVER) && \
  936. !defined(SSB_OHCI_DRIVER)
  937. #error "missing bus glue for ohci-hcd"
  938. #endif
  939. static int __init ohci_hcd_mod_init(void)
  940. {
  941. int retval = 0;
  942. if (usb_disabled())
  943. return -ENODEV;
  944. printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
  945. pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
  946. sizeof (struct ed), sizeof (struct td));
  947. set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
  948. #ifdef DEBUG
  949. ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
  950. if (!ohci_debug_root) {
  951. retval = -ENOENT;
  952. goto error_debug;
  953. }
  954. #endif
  955. #ifdef PS3_SYSTEM_BUS_DRIVER
  956. retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
  957. if (retval < 0)
  958. goto error_ps3;
  959. #endif
  960. #ifdef PLATFORM_DRIVER
  961. retval = platform_driver_register(&PLATFORM_DRIVER);
  962. if (retval < 0)
  963. goto error_platform;
  964. #endif
  965. #ifdef OMAP1_PLATFORM_DRIVER
  966. retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
  967. if (retval < 0)
  968. goto error_omap1_platform;
  969. #endif
  970. #ifdef OMAP3_PLATFORM_DRIVER
  971. retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
  972. if (retval < 0)
  973. goto error_omap3_platform;
  974. #endif
  975. #ifdef OF_PLATFORM_DRIVER
  976. retval = platform_driver_register(&OF_PLATFORM_DRIVER);
  977. if (retval < 0)
  978. goto error_of_platform;
  979. #endif
  980. #ifdef SA1111_DRIVER
  981. retval = sa1111_driver_register(&SA1111_DRIVER);
  982. if (retval < 0)
  983. goto error_sa1111;
  984. #endif
  985. #ifdef PCI_DRIVER
  986. retval = pci_register_driver(&PCI_DRIVER);
  987. if (retval < 0)
  988. goto error_pci;
  989. #endif
  990. #ifdef SSB_OHCI_DRIVER
  991. retval = ssb_driver_register(&SSB_OHCI_DRIVER);
  992. if (retval)
  993. goto error_ssb;
  994. #endif
  995. #ifdef SM501_OHCI_DRIVER
  996. retval = platform_driver_register(&SM501_OHCI_DRIVER);
  997. if (retval < 0)
  998. goto error_sm501;
  999. #endif
  1000. #ifdef TMIO_OHCI_DRIVER
  1001. retval = platform_driver_register(&TMIO_OHCI_DRIVER);
  1002. if (retval < 0)
  1003. goto error_tmio;
  1004. #endif
  1005. return retval;
  1006. /* Error path */
  1007. #ifdef TMIO_OHCI_DRIVER
  1008. platform_driver_unregister(&TMIO_OHCI_DRIVER);
  1009. error_tmio:
  1010. #endif
  1011. #ifdef SM501_OHCI_DRIVER
  1012. platform_driver_unregister(&SM501_OHCI_DRIVER);
  1013. error_sm501:
  1014. #endif
  1015. #ifdef SSB_OHCI_DRIVER
  1016. ssb_driver_unregister(&SSB_OHCI_DRIVER);
  1017. error_ssb:
  1018. #endif
  1019. #ifdef PCI_DRIVER
  1020. pci_unregister_driver(&PCI_DRIVER);
  1021. error_pci:
  1022. #endif
  1023. #ifdef SA1111_DRIVER
  1024. sa1111_driver_unregister(&SA1111_DRIVER);
  1025. error_sa1111:
  1026. #endif
  1027. #ifdef OF_PLATFORM_DRIVER
  1028. platform_driver_unregister(&OF_PLATFORM_DRIVER);
  1029. error_of_platform:
  1030. #endif
  1031. #ifdef PLATFORM_DRIVER
  1032. platform_driver_unregister(&PLATFORM_DRIVER);
  1033. error_platform:
  1034. #endif
  1035. #ifdef OMAP1_PLATFORM_DRIVER
  1036. platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
  1037. error_omap1_platform:
  1038. #endif
  1039. #ifdef OMAP3_PLATFORM_DRIVER
  1040. platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
  1041. error_omap3_platform:
  1042. #endif
  1043. #ifdef PS3_SYSTEM_BUS_DRIVER
  1044. ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
  1045. error_ps3:
  1046. #endif
  1047. #ifdef DEBUG
  1048. debugfs_remove(ohci_debug_root);
  1049. ohci_debug_root = NULL;
  1050. error_debug:
  1051. #endif
  1052. clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
  1053. return retval;
  1054. }
  1055. module_init(ohci_hcd_mod_init);
  1056. static void __exit ohci_hcd_mod_exit(void)
  1057. {
  1058. #ifdef TMIO_OHCI_DRIVER
  1059. platform_driver_unregister(&TMIO_OHCI_DRIVER);
  1060. #endif
  1061. #ifdef SM501_OHCI_DRIVER
  1062. platform_driver_unregister(&SM501_OHCI_DRIVER);
  1063. #endif
  1064. #ifdef SSB_OHCI_DRIVER
  1065. ssb_driver_unregister(&SSB_OHCI_DRIVER);
  1066. #endif
  1067. #ifdef PCI_DRIVER
  1068. pci_unregister_driver(&PCI_DRIVER);
  1069. #endif
  1070. #ifdef SA1111_DRIVER
  1071. sa1111_driver_unregister(&SA1111_DRIVER);
  1072. #endif
  1073. #ifdef OF_PLATFORM_DRIVER
  1074. platform_driver_unregister(&OF_PLATFORM_DRIVER);
  1075. #endif
  1076. #ifdef PLATFORM_DRIVER
  1077. platform_driver_unregister(&PLATFORM_DRIVER);
  1078. #endif
  1079. #ifdef OMAP3_PLATFORM_DRIVER
  1080. platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
  1081. #endif
  1082. #ifdef PS3_SYSTEM_BUS_DRIVER
  1083. ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
  1084. #endif
  1085. #ifdef DEBUG
  1086. debugfs_remove(ohci_debug_root);
  1087. #endif
  1088. clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
  1089. }
  1090. module_exit(ohci_hcd_mod_exit);