ehci-fsl.c 12 KB

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  1. /*
  2. * Copyright 2005-2009 MontaVista Software, Inc.
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20. * by Hunter Wu.
  21. * Power Management support by Dave Liu <daveliu@freescale.com>,
  22. * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23. * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/fsl_devices.h>
  31. #include "ehci-fsl.h"
  32. /* configure so an HC device and id are always provided */
  33. /* always called with process context; sleeping is OK */
  34. /**
  35. * usb_hcd_fsl_probe - initialize FSL-based HCDs
  36. * @drvier: Driver to be used for this HCD
  37. * @pdev: USB Host Controller being probed
  38. * Context: !in_interrupt()
  39. *
  40. * Allocates basic resources for this USB host controller.
  41. *
  42. */
  43. static int usb_hcd_fsl_probe(const struct hc_driver *driver,
  44. struct platform_device *pdev)
  45. {
  46. struct fsl_usb2_platform_data *pdata;
  47. struct usb_hcd *hcd;
  48. struct resource *res;
  49. int irq;
  50. int retval;
  51. pr_debug("initializing FSL-SOC USB Controller\n");
  52. /* Need platform data for setup */
  53. pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
  54. if (!pdata) {
  55. dev_err(&pdev->dev,
  56. "No platform data for %s.\n", dev_name(&pdev->dev));
  57. return -ENODEV;
  58. }
  59. /*
  60. * This is a host mode driver, verify that we're supposed to be
  61. * in host mode.
  62. */
  63. if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  64. (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  65. (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  66. dev_err(&pdev->dev,
  67. "Non Host Mode configured for %s. Wrong driver linked.\n",
  68. dev_name(&pdev->dev));
  69. return -ENODEV;
  70. }
  71. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  72. if (!res) {
  73. dev_err(&pdev->dev,
  74. "Found HC with no IRQ. Check %s setup!\n",
  75. dev_name(&pdev->dev));
  76. return -ENODEV;
  77. }
  78. irq = res->start;
  79. hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
  80. if (!hcd) {
  81. retval = -ENOMEM;
  82. goto err1;
  83. }
  84. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  85. if (!res) {
  86. dev_err(&pdev->dev,
  87. "Found HC with no register addr. Check %s setup!\n",
  88. dev_name(&pdev->dev));
  89. retval = -ENODEV;
  90. goto err2;
  91. }
  92. hcd->rsrc_start = res->start;
  93. hcd->rsrc_len = res->end - res->start + 1;
  94. if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
  95. driver->description)) {
  96. dev_dbg(&pdev->dev, "controller already in use\n");
  97. retval = -EBUSY;
  98. goto err2;
  99. }
  100. hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
  101. if (hcd->regs == NULL) {
  102. dev_dbg(&pdev->dev, "error mapping memory\n");
  103. retval = -EFAULT;
  104. goto err3;
  105. }
  106. pdata->regs = hcd->regs;
  107. /*
  108. * do platform specific init: check the clock, grab/config pins, etc.
  109. */
  110. if (pdata->init && pdata->init(pdev)) {
  111. retval = -ENODEV;
  112. goto err3;
  113. }
  114. /* Enable USB controller, 83xx or 8536 */
  115. if (pdata->have_sysif_regs)
  116. setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
  117. /* Don't need to set host mode here. It will be done by tdi_reset() */
  118. retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
  119. if (retval != 0)
  120. goto err4;
  121. return retval;
  122. err4:
  123. iounmap(hcd->regs);
  124. err3:
  125. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  126. err2:
  127. usb_put_hcd(hcd);
  128. err1:
  129. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
  130. if (pdata->exit)
  131. pdata->exit(pdev);
  132. return retval;
  133. }
  134. /* may be called without controller electrically present */
  135. /* may be called with controller, bus, and devices active */
  136. /**
  137. * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
  138. * @dev: USB Host Controller being removed
  139. * Context: !in_interrupt()
  140. *
  141. * Reverses the effect of usb_hcd_fsl_probe().
  142. *
  143. */
  144. static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
  145. struct platform_device *pdev)
  146. {
  147. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  148. usb_remove_hcd(hcd);
  149. /*
  150. * do platform specific un-initialization:
  151. * release iomux pins, disable clock, etc.
  152. */
  153. if (pdata->exit)
  154. pdata->exit(pdev);
  155. iounmap(hcd->regs);
  156. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  157. usb_put_hcd(hcd);
  158. }
  159. static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
  160. enum fsl_usb2_phy_modes phy_mode,
  161. unsigned int port_offset)
  162. {
  163. u32 portsc;
  164. portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
  165. portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
  166. switch (phy_mode) {
  167. case FSL_USB2_PHY_ULPI:
  168. portsc |= PORT_PTS_ULPI;
  169. break;
  170. case FSL_USB2_PHY_SERIAL:
  171. portsc |= PORT_PTS_SERIAL;
  172. break;
  173. case FSL_USB2_PHY_UTMI_WIDE:
  174. portsc |= PORT_PTS_PTW;
  175. /* fall through */
  176. case FSL_USB2_PHY_UTMI:
  177. portsc |= PORT_PTS_UTMI;
  178. break;
  179. case FSL_USB2_PHY_NONE:
  180. break;
  181. }
  182. ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
  183. }
  184. static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
  185. {
  186. struct usb_hcd *hcd = ehci_to_hcd(ehci);
  187. struct fsl_usb2_platform_data *pdata;
  188. void __iomem *non_ehci = hcd->regs;
  189. u32 temp;
  190. pdata = hcd->self.controller->platform_data;
  191. /* Enable PHY interface in the control reg. */
  192. if (pdata->have_sysif_regs) {
  193. temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  194. out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004);
  195. out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b);
  196. }
  197. #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
  198. /*
  199. * Turn on cache snooping hardware, since some PowerPC platforms
  200. * wholly rely on hardware to deal with cache coherent
  201. */
  202. /* Setup Snooping for all the 4GB space */
  203. /* SNOOP1 starts from 0x0, size 2G */
  204. out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
  205. /* SNOOP2 starts from 0x80000000, size 2G */
  206. out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
  207. #endif
  208. if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  209. (pdata->operating_mode == FSL_USB2_DR_OTG))
  210. ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
  211. if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
  212. unsigned int chip, rev, svr;
  213. svr = mfspr(SPRN_SVR);
  214. chip = svr >> 16;
  215. rev = (svr >> 4) & 0xf;
  216. /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
  217. if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
  218. ehci->has_fsl_port_bug = 1;
  219. if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
  220. ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
  221. if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
  222. ehci_fsl_setup_phy(ehci, pdata->phy_mode, 1);
  223. }
  224. if (pdata->have_sysif_regs) {
  225. #ifdef CONFIG_PPC_85xx
  226. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
  227. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
  228. #else
  229. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
  230. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
  231. #endif
  232. out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
  233. }
  234. }
  235. /* called after powerup, by probe or system-pm "wakeup" */
  236. static int ehci_fsl_reinit(struct ehci_hcd *ehci)
  237. {
  238. ehci_fsl_usb_setup(ehci);
  239. ehci_port_power(ehci, 0);
  240. return 0;
  241. }
  242. /* called during probe() after chip reset completes */
  243. static int ehci_fsl_setup(struct usb_hcd *hcd)
  244. {
  245. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  246. int retval;
  247. struct fsl_usb2_platform_data *pdata;
  248. pdata = hcd->self.controller->platform_data;
  249. ehci->big_endian_desc = pdata->big_endian_desc;
  250. ehci->big_endian_mmio = pdata->big_endian_mmio;
  251. /* EHCI registers start at offset 0x100 */
  252. ehci->caps = hcd->regs + 0x100;
  253. ehci->regs = hcd->regs + 0x100 +
  254. HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
  255. dbg_hcs_params(ehci, "reset");
  256. dbg_hcc_params(ehci, "reset");
  257. /* cache this readonly data; minimize chip reads */
  258. ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
  259. hcd->has_tt = 1;
  260. retval = ehci_halt(ehci);
  261. if (retval)
  262. return retval;
  263. /* data structure init */
  264. retval = ehci_init(hcd);
  265. if (retval)
  266. return retval;
  267. ehci->sbrn = 0x20;
  268. ehci_reset(ehci);
  269. retval = ehci_fsl_reinit(ehci);
  270. return retval;
  271. }
  272. struct ehci_fsl {
  273. struct ehci_hcd ehci;
  274. #ifdef CONFIG_PM
  275. /* Saved USB PHY settings, need to restore after deep sleep. */
  276. u32 usb_ctrl;
  277. #endif
  278. };
  279. #ifdef CONFIG_PM
  280. static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
  281. {
  282. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  283. return container_of(ehci, struct ehci_fsl, ehci);
  284. }
  285. static int ehci_fsl_drv_suspend(struct device *dev)
  286. {
  287. struct usb_hcd *hcd = dev_get_drvdata(dev);
  288. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  289. void __iomem *non_ehci = hcd->regs;
  290. ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
  291. device_may_wakeup(dev));
  292. if (!fsl_deep_sleep())
  293. return 0;
  294. ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  295. return 0;
  296. }
  297. static int ehci_fsl_drv_resume(struct device *dev)
  298. {
  299. struct usb_hcd *hcd = dev_get_drvdata(dev);
  300. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  301. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  302. void __iomem *non_ehci = hcd->regs;
  303. ehci_prepare_ports_for_controller_resume(ehci);
  304. if (!fsl_deep_sleep())
  305. return 0;
  306. usb_root_hub_lost_power(hcd->self.root_hub);
  307. /* Restore USB PHY settings and enable the controller. */
  308. out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
  309. ehci_reset(ehci);
  310. ehci_fsl_reinit(ehci);
  311. return 0;
  312. }
  313. static int ehci_fsl_drv_restore(struct device *dev)
  314. {
  315. struct usb_hcd *hcd = dev_get_drvdata(dev);
  316. usb_root_hub_lost_power(hcd->self.root_hub);
  317. return 0;
  318. }
  319. static struct dev_pm_ops ehci_fsl_pm_ops = {
  320. .suspend = ehci_fsl_drv_suspend,
  321. .resume = ehci_fsl_drv_resume,
  322. .restore = ehci_fsl_drv_restore,
  323. };
  324. #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
  325. #else
  326. #define EHCI_FSL_PM_OPS NULL
  327. #endif /* CONFIG_PM */
  328. static const struct hc_driver ehci_fsl_hc_driver = {
  329. .description = hcd_name,
  330. .product_desc = "Freescale On-Chip EHCI Host Controller",
  331. .hcd_priv_size = sizeof(struct ehci_fsl),
  332. /*
  333. * generic hardware linkage
  334. */
  335. .irq = ehci_irq,
  336. .flags = HCD_USB2 | HCD_MEMORY,
  337. /*
  338. * basic lifecycle operations
  339. */
  340. .reset = ehci_fsl_setup,
  341. .start = ehci_run,
  342. .stop = ehci_stop,
  343. .shutdown = ehci_shutdown,
  344. /*
  345. * managing i/o requests and associated device resources
  346. */
  347. .urb_enqueue = ehci_urb_enqueue,
  348. .urb_dequeue = ehci_urb_dequeue,
  349. .endpoint_disable = ehci_endpoint_disable,
  350. .endpoint_reset = ehci_endpoint_reset,
  351. /*
  352. * scheduling support
  353. */
  354. .get_frame_number = ehci_get_frame,
  355. /*
  356. * root hub support
  357. */
  358. .hub_status_data = ehci_hub_status_data,
  359. .hub_control = ehci_hub_control,
  360. .bus_suspend = ehci_bus_suspend,
  361. .bus_resume = ehci_bus_resume,
  362. .relinquish_port = ehci_relinquish_port,
  363. .port_handed_over = ehci_port_handed_over,
  364. .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
  365. };
  366. static int ehci_fsl_drv_probe(struct platform_device *pdev)
  367. {
  368. if (usb_disabled())
  369. return -ENODEV;
  370. /* FIXME we only want one one probe() not two */
  371. return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
  372. }
  373. static int ehci_fsl_drv_remove(struct platform_device *pdev)
  374. {
  375. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  376. /* FIXME we only want one one remove() not two */
  377. usb_hcd_fsl_remove(hcd, pdev);
  378. return 0;
  379. }
  380. MODULE_ALIAS("platform:fsl-ehci");
  381. static struct platform_driver ehci_fsl_driver = {
  382. .probe = ehci_fsl_drv_probe,
  383. .remove = ehci_fsl_drv_remove,
  384. .shutdown = usb_hcd_platform_shutdown,
  385. .driver = {
  386. .name = "fsl-ehci",
  387. .pm = EHCI_FSL_PM_OPS,
  388. },
  389. };