langwell_udc.h 6.0 KB

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  1. /*
  2. * Intel Langwell USB Device Controller driver
  3. * Copyright (C) 2008-2009, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. #include <linux/usb/langwell_udc.h>
  20. #include <linux/usb/langwell_otg.h>
  21. /*-------------------------------------------------------------------------*/
  22. /* driver data structures and utilities */
  23. /*
  24. * dTD: Device Endpoint Transfer Descriptor
  25. * describe to the device controller the location and quantity of
  26. * data to be send/received for given transfer
  27. */
  28. struct langwell_dtd {
  29. u32 dtd_next;
  30. /* bits 31:5, next transfer element pointer */
  31. #define DTD_NEXT(d) (((d)>>5)&0x7ffffff)
  32. #define DTD_NEXT_MASK (0x7ffffff << 5)
  33. /* terminate */
  34. #define DTD_TERM BIT(0)
  35. /* bits 7:0, execution back states */
  36. u32 dtd_status:8;
  37. #define DTD_STATUS(d) (((d)>>0)&0xff)
  38. #define DTD_STS_ACTIVE BIT(7) /* active */
  39. #define DTD_STS_HALTED BIT(6) /* halted */
  40. #define DTD_STS_DBE BIT(5) /* data buffer error */
  41. #define DTD_STS_TRE BIT(3) /* transaction error */
  42. /* bits 9:8 */
  43. u32 dtd_res0:2;
  44. /* bits 11:10, multipier override */
  45. u32 dtd_multo:2;
  46. #define DTD_MULTO (BIT(11) | BIT(10))
  47. /* bits 14:12 */
  48. u32 dtd_res1:3;
  49. /* bit 15, interrupt on complete */
  50. u32 dtd_ioc:1;
  51. #define DTD_IOC BIT(15)
  52. /* bits 30:16, total bytes */
  53. u32 dtd_total:15;
  54. #define DTD_TOTAL(d) (((d)>>16)&0x7fff)
  55. #define DTD_MAX_TRANSFER_LENGTH 0x4000
  56. /* bit 31 */
  57. u32 dtd_res2:1;
  58. /* dTD buffer pointer page 0 to 4 */
  59. u32 dtd_buf[5];
  60. #define DTD_OFFSET_MASK 0xfff
  61. /* bits 31:12, buffer pointer */
  62. #define DTD_BUFFER(d) (((d)>>12)&0x3ff)
  63. /* bits 11:0, current offset */
  64. #define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
  65. /* bits 10:0, frame number */
  66. #define DTD_FRAME(d) (((d)>>0)&0x7ff)
  67. /* driver-private parts */
  68. /* dtd dma address */
  69. dma_addr_t dtd_dma;
  70. /* next dtd virtual address */
  71. struct langwell_dtd *next_dtd_virt;
  72. };
  73. /*
  74. * dQH: Device Endpoint Queue Head
  75. * describe where all transfers are managed
  76. * 48-byte data structure, aligned on 64-byte boundary
  77. *
  78. * These are associated with dTD structure
  79. */
  80. struct langwell_dqh {
  81. /* endpoint capabilities and characteristics */
  82. u32 dqh_res0:15; /* bits 14:0 */
  83. u32 dqh_ios:1; /* bit 15, interrupt on setup */
  84. #define DQH_IOS BIT(15)
  85. u32 dqh_mpl:11; /* bits 26:16, maximum packet length */
  86. #define DQH_MPL (0x7ff << 16)
  87. u32 dqh_res1:2; /* bits 28:27 */
  88. u32 dqh_zlt:1; /* bit 29, zero length termination */
  89. #define DQH_ZLT BIT(29)
  90. u32 dqh_mult:2; /* bits 31:30 */
  91. #define DQH_MULT (BIT(30) | BIT(31))
  92. /* current dTD pointer */
  93. u32 dqh_current; /* locate the transfer in progress */
  94. #define DQH_C_DTD(e) \
  95. (((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */
  96. /* transfer overlay, hardware parts of a struct langwell_dtd */
  97. u32 dtd_next;
  98. u32 dtd_status:8; /* bits 7:0, execution back states */
  99. u32 dtd_res0:2; /* bits 9:8 */
  100. u32 dtd_multo:2; /* bits 11:10, multipier override */
  101. u32 dtd_res1:3; /* bits 14:12 */
  102. u32 dtd_ioc:1; /* bit 15, interrupt on complete */
  103. u32 dtd_total:15; /* bits 30:16, total bytes */
  104. u32 dtd_res2:1; /* bit 31 */
  105. u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */
  106. u32 dqh_res2;
  107. struct usb_ctrlrequest dqh_setup; /* setup packet buffer */
  108. } __attribute__ ((aligned(64)));
  109. /* endpoint data structure */
  110. struct langwell_ep {
  111. struct usb_ep ep;
  112. dma_addr_t dma;
  113. struct langwell_udc *dev;
  114. unsigned long irqs;
  115. struct list_head queue;
  116. struct langwell_dqh *dqh;
  117. const struct usb_endpoint_descriptor *desc;
  118. char name[14];
  119. unsigned stopped:1,
  120. ep_type:2,
  121. ep_num:8;
  122. };
  123. /* request data structure */
  124. struct langwell_request {
  125. struct usb_request req;
  126. struct langwell_dtd *dtd, *head, *tail;
  127. struct langwell_ep *ep;
  128. dma_addr_t dtd_dma;
  129. struct list_head queue;
  130. unsigned dtd_count;
  131. unsigned mapped:1;
  132. };
  133. /* ep0 transfer state */
  134. enum ep0_state {
  135. WAIT_FOR_SETUP,
  136. DATA_STATE_XMIT,
  137. DATA_STATE_NEED_ZLP,
  138. WAIT_FOR_OUT_STATUS,
  139. DATA_STATE_RECV,
  140. };
  141. /* device suspend state */
  142. enum lpm_state {
  143. LPM_L0, /* on */
  144. LPM_L1, /* LPM L1 sleep */
  145. LPM_L2, /* suspend */
  146. LPM_L3, /* off */
  147. };
  148. /* device data structure */
  149. struct langwell_udc {
  150. /* each pci device provides one gadget, several endpoints */
  151. struct usb_gadget gadget;
  152. spinlock_t lock; /* device lock */
  153. struct langwell_ep *ep;
  154. struct usb_gadget_driver *driver;
  155. struct otg_transceiver *transceiver;
  156. u8 dev_addr;
  157. u32 usb_state;
  158. u32 resume_state;
  159. u32 bus_reset;
  160. enum lpm_state lpm_state;
  161. enum ep0_state ep0_state;
  162. u32 ep0_dir;
  163. u16 dciversion;
  164. unsigned ep_max;
  165. unsigned devcap:1,
  166. enabled:1,
  167. region:1,
  168. got_irq:1,
  169. powered:1,
  170. remote_wakeup:1,
  171. rate:1,
  172. is_reset:1,
  173. softconnected:1,
  174. vbus_active:1,
  175. suspended:1,
  176. stopped:1,
  177. lpm:1, /* LPM capability */
  178. has_sram:1, /* SRAM caching */
  179. got_sram:1;
  180. /* pci state used to access those endpoints */
  181. struct pci_dev *pdev;
  182. /* Langwell otg transceiver */
  183. struct langwell_otg *lotg;
  184. /* control registers */
  185. struct langwell_cap_regs __iomem *cap_regs;
  186. struct langwell_op_regs __iomem *op_regs;
  187. struct usb_ctrlrequest local_setup_buff;
  188. struct langwell_dqh *ep_dqh;
  189. size_t ep_dqh_size;
  190. dma_addr_t ep_dqh_dma;
  191. /* ep0 status request */
  192. struct langwell_request *status_req;
  193. /* dma pool */
  194. struct dma_pool *dtd_pool;
  195. /* make sure release() is done */
  196. struct completion *done;
  197. /* for private SRAM caching */
  198. unsigned int sram_addr;
  199. unsigned int sram_size;
  200. /* device status data for get_status request */
  201. u16 dev_status;
  202. };