ci13xxx_udc.c 70 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/interrupt.h>
  58. #include <linux/io.h>
  59. #include <linux/irq.h>
  60. #include <linux/kernel.h>
  61. #include <linux/slab.h>
  62. #include <linux/pm_runtime.h>
  63. #include <linux/usb/ch9.h>
  64. #include <linux/usb/gadget.h>
  65. #include <linux/usb/otg.h>
  66. #include "ci13xxx_udc.h"
  67. /******************************************************************************
  68. * DEFINE
  69. *****************************************************************************/
  70. /* ctrl register bank access */
  71. static DEFINE_SPINLOCK(udc_lock);
  72. /* control endpoint description */
  73. static const struct usb_endpoint_descriptor
  74. ctrl_endpt_out_desc = {
  75. .bLength = USB_DT_ENDPOINT_SIZE,
  76. .bDescriptorType = USB_DT_ENDPOINT,
  77. .bEndpointAddress = USB_DIR_OUT,
  78. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  79. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  80. };
  81. static const struct usb_endpoint_descriptor
  82. ctrl_endpt_in_desc = {
  83. .bLength = USB_DT_ENDPOINT_SIZE,
  84. .bDescriptorType = USB_DT_ENDPOINT,
  85. .bEndpointAddress = USB_DIR_IN,
  86. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  87. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  88. };
  89. /* UDC descriptor */
  90. static struct ci13xxx *_udc;
  91. /* Interrupt statistics */
  92. #define ISR_MASK 0x1F
  93. static struct {
  94. u32 test;
  95. u32 ui;
  96. u32 uei;
  97. u32 pci;
  98. u32 uri;
  99. u32 sli;
  100. u32 none;
  101. struct {
  102. u32 cnt;
  103. u32 buf[ISR_MASK+1];
  104. u32 idx;
  105. } hndl;
  106. } isr_statistics;
  107. /**
  108. * ffs_nr: find first (least significant) bit set
  109. * @x: the word to search
  110. *
  111. * This function returns bit number (instead of position)
  112. */
  113. static int ffs_nr(u32 x)
  114. {
  115. int n = ffs(x);
  116. return n ? n-1 : 32;
  117. }
  118. /******************************************************************************
  119. * HW block
  120. *****************************************************************************/
  121. /* register bank descriptor */
  122. static struct {
  123. unsigned lpm; /* is LPM? */
  124. void __iomem *abs; /* bus map offset */
  125. void __iomem *cap; /* bus map offset + CAP offset + CAP data */
  126. size_t size; /* bank size */
  127. } hw_bank;
  128. /* MSM specific */
  129. #define ABS_AHBBURST (0x0090UL)
  130. #define ABS_AHBMODE (0x0098UL)
  131. /* UDC register map */
  132. #define ABS_CAPLENGTH (0x100UL)
  133. #define ABS_HCCPARAMS (0x108UL)
  134. #define ABS_DCCPARAMS (0x124UL)
  135. #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
  136. /* offset to CAPLENTGH (addr + data) */
  137. #define CAP_USBCMD (0x000UL)
  138. #define CAP_USBSTS (0x004UL)
  139. #define CAP_USBINTR (0x008UL)
  140. #define CAP_DEVICEADDR (0x014UL)
  141. #define CAP_ENDPTLISTADDR (0x018UL)
  142. #define CAP_PORTSC (0x044UL)
  143. #define CAP_DEVLC (0x084UL)
  144. #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
  145. #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
  146. #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
  147. #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
  148. #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
  149. #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
  150. #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
  151. #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
  152. /* maximum number of enpoints: valid only after hw_device_reset() */
  153. static unsigned hw_ep_max;
  154. /**
  155. * hw_ep_bit: calculates the bit number
  156. * @num: endpoint number
  157. * @dir: endpoint direction
  158. *
  159. * This function returns bit number
  160. */
  161. static inline int hw_ep_bit(int num, int dir)
  162. {
  163. return num + (dir ? 16 : 0);
  164. }
  165. /**
  166. * hw_aread: reads from register bitfield
  167. * @addr: address relative to bus map
  168. * @mask: bitfield mask
  169. *
  170. * This function returns register bitfield data
  171. */
  172. static u32 hw_aread(u32 addr, u32 mask)
  173. {
  174. return ioread32(addr + hw_bank.abs) & mask;
  175. }
  176. /**
  177. * hw_awrite: writes to register bitfield
  178. * @addr: address relative to bus map
  179. * @mask: bitfield mask
  180. * @data: new data
  181. */
  182. static void hw_awrite(u32 addr, u32 mask, u32 data)
  183. {
  184. iowrite32(hw_aread(addr, ~mask) | (data & mask),
  185. addr + hw_bank.abs);
  186. }
  187. /**
  188. * hw_cread: reads from register bitfield
  189. * @addr: address relative to CAP offset plus content
  190. * @mask: bitfield mask
  191. *
  192. * This function returns register bitfield data
  193. */
  194. static u32 hw_cread(u32 addr, u32 mask)
  195. {
  196. return ioread32(addr + hw_bank.cap) & mask;
  197. }
  198. /**
  199. * hw_cwrite: writes to register bitfield
  200. * @addr: address relative to CAP offset plus content
  201. * @mask: bitfield mask
  202. * @data: new data
  203. */
  204. static void hw_cwrite(u32 addr, u32 mask, u32 data)
  205. {
  206. iowrite32(hw_cread(addr, ~mask) | (data & mask),
  207. addr + hw_bank.cap);
  208. }
  209. /**
  210. * hw_ctest_and_clear: tests & clears register bitfield
  211. * @addr: address relative to CAP offset plus content
  212. * @mask: bitfield mask
  213. *
  214. * This function returns register bitfield data
  215. */
  216. static u32 hw_ctest_and_clear(u32 addr, u32 mask)
  217. {
  218. u32 reg = hw_cread(addr, mask);
  219. iowrite32(reg, addr + hw_bank.cap);
  220. return reg;
  221. }
  222. /**
  223. * hw_ctest_and_write: tests & writes register bitfield
  224. * @addr: address relative to CAP offset plus content
  225. * @mask: bitfield mask
  226. * @data: new data
  227. *
  228. * This function returns register bitfield data
  229. */
  230. static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
  231. {
  232. u32 reg = hw_cread(addr, ~0);
  233. iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
  234. return (reg & mask) >> ffs_nr(mask);
  235. }
  236. static int hw_device_init(void __iomem *base)
  237. {
  238. u32 reg;
  239. /* bank is a module variable */
  240. hw_bank.abs = base;
  241. hw_bank.cap = hw_bank.abs;
  242. hw_bank.cap += ABS_CAPLENGTH;
  243. hw_bank.cap += ioread8(hw_bank.cap);
  244. reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
  245. hw_bank.lpm = reg;
  246. hw_bank.size = hw_bank.cap - hw_bank.abs;
  247. hw_bank.size += CAP_LAST;
  248. hw_bank.size /= sizeof(u32);
  249. reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
  250. hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  251. if (hw_ep_max == 0 || hw_ep_max > ENDPT_MAX)
  252. return -ENODEV;
  253. /* setup lock mode ? */
  254. /* ENDPTSETUPSTAT is '0' by default */
  255. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  256. return 0;
  257. }
  258. /**
  259. * hw_device_reset: resets chip (execute without interruption)
  260. * @base: register base address
  261. *
  262. * This function returns an error code
  263. */
  264. static int hw_device_reset(struct ci13xxx *udc)
  265. {
  266. /* should flush & stop before reset */
  267. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
  268. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  269. hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
  270. while (hw_cread(CAP_USBCMD, USBCMD_RST))
  271. udelay(10); /* not RTOS friendly */
  272. if (udc->udc_driver->notify_event)
  273. udc->udc_driver->notify_event(udc,
  274. CI13XXX_CONTROLLER_RESET_EVENT);
  275. if (udc->udc_driver->flags && CI13XXX_DISABLE_STREAMING)
  276. hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  277. /* USBMODE should be configured step by step */
  278. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  279. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  280. hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
  281. if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  282. pr_err("cannot enter in device mode");
  283. pr_err("lpm = %i", hw_bank.lpm);
  284. return -ENODEV;
  285. }
  286. return 0;
  287. }
  288. /**
  289. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  290. * without interruption)
  291. * @dma: 0 => disable, !0 => enable and set dma engine
  292. *
  293. * This function returns an error code
  294. */
  295. static int hw_device_state(u32 dma)
  296. {
  297. if (dma) {
  298. hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
  299. /* interrupt, error, port change, reset, sleep/suspend */
  300. hw_cwrite(CAP_USBINTR, ~0,
  301. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  302. hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
  303. } else {
  304. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  305. hw_cwrite(CAP_USBINTR, ~0, 0);
  306. }
  307. return 0;
  308. }
  309. /**
  310. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  311. * @num: endpoint number
  312. * @dir: endpoint direction
  313. *
  314. * This function returns an error code
  315. */
  316. static int hw_ep_flush(int num, int dir)
  317. {
  318. int n = hw_ep_bit(num, dir);
  319. do {
  320. /* flush any pending transfer */
  321. hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
  322. while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
  323. cpu_relax();
  324. } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
  325. return 0;
  326. }
  327. /**
  328. * hw_ep_disable: disables endpoint (execute without interruption)
  329. * @num: endpoint number
  330. * @dir: endpoint direction
  331. *
  332. * This function returns an error code
  333. */
  334. static int hw_ep_disable(int num, int dir)
  335. {
  336. hw_ep_flush(num, dir);
  337. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
  338. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  339. return 0;
  340. }
  341. /**
  342. * hw_ep_enable: enables endpoint (execute without interruption)
  343. * @num: endpoint number
  344. * @dir: endpoint direction
  345. * @type: endpoint type
  346. *
  347. * This function returns an error code
  348. */
  349. static int hw_ep_enable(int num, int dir, int type)
  350. {
  351. u32 mask, data;
  352. if (dir) {
  353. mask = ENDPTCTRL_TXT; /* type */
  354. data = type << ffs_nr(mask);
  355. mask |= ENDPTCTRL_TXS; /* unstall */
  356. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  357. data |= ENDPTCTRL_TXR;
  358. mask |= ENDPTCTRL_TXE; /* enable */
  359. data |= ENDPTCTRL_TXE;
  360. } else {
  361. mask = ENDPTCTRL_RXT; /* type */
  362. data = type << ffs_nr(mask);
  363. mask |= ENDPTCTRL_RXS; /* unstall */
  364. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  365. data |= ENDPTCTRL_RXR;
  366. mask |= ENDPTCTRL_RXE; /* enable */
  367. data |= ENDPTCTRL_RXE;
  368. }
  369. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
  370. return 0;
  371. }
  372. /**
  373. * hw_ep_get_halt: return endpoint halt status
  374. * @num: endpoint number
  375. * @dir: endpoint direction
  376. *
  377. * This function returns 1 if endpoint halted
  378. */
  379. static int hw_ep_get_halt(int num, int dir)
  380. {
  381. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  382. return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
  383. }
  384. /**
  385. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  386. * interruption)
  387. * @n: bit number (endpoint)
  388. *
  389. * This function returns setup status
  390. */
  391. static int hw_test_and_clear_setup_status(int n)
  392. {
  393. return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
  394. }
  395. /**
  396. * hw_ep_prime: primes endpoint (execute without interruption)
  397. * @num: endpoint number
  398. * @dir: endpoint direction
  399. * @is_ctrl: true if control endpoint
  400. *
  401. * This function returns an error code
  402. */
  403. static int hw_ep_prime(int num, int dir, int is_ctrl)
  404. {
  405. int n = hw_ep_bit(num, dir);
  406. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  407. return -EAGAIN;
  408. hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
  409. while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  410. cpu_relax();
  411. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  412. return -EAGAIN;
  413. /* status shoult be tested according with manual but it doesn't work */
  414. return 0;
  415. }
  416. /**
  417. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  418. * without interruption)
  419. * @num: endpoint number
  420. * @dir: endpoint direction
  421. * @value: true => stall, false => unstall
  422. *
  423. * This function returns an error code
  424. */
  425. static int hw_ep_set_halt(int num, int dir, int value)
  426. {
  427. if (value != 0 && value != 1)
  428. return -EINVAL;
  429. do {
  430. u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
  431. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  432. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  433. /* data toggle - reserved for EP0 but it's in ESS */
  434. hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
  435. } while (value != hw_ep_get_halt(num, dir));
  436. return 0;
  437. }
  438. /**
  439. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  440. * interruption)
  441. * @n: interrupt bit
  442. *
  443. * This function returns an error code
  444. */
  445. static int hw_intr_clear(int n)
  446. {
  447. if (n >= REG_BITS)
  448. return -EINVAL;
  449. hw_cwrite(CAP_USBINTR, BIT(n), 0);
  450. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  451. return 0;
  452. }
  453. /**
  454. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  455. * interruption)
  456. * @n: interrupt bit
  457. *
  458. * This function returns an error code
  459. */
  460. static int hw_intr_force(int n)
  461. {
  462. if (n >= REG_BITS)
  463. return -EINVAL;
  464. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  465. hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
  466. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  467. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
  468. return 0;
  469. }
  470. /**
  471. * hw_is_port_high_speed: test if port is high speed
  472. *
  473. * This function returns true if high speed port
  474. */
  475. static int hw_port_is_high_speed(void)
  476. {
  477. return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
  478. hw_cread(CAP_PORTSC, PORTSC_HSP);
  479. }
  480. /**
  481. * hw_port_test_get: reads port test mode value
  482. *
  483. * This function returns port test mode value
  484. */
  485. static u8 hw_port_test_get(void)
  486. {
  487. return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  488. }
  489. /**
  490. * hw_port_test_set: writes port test mode (execute without interruption)
  491. * @mode: new value
  492. *
  493. * This function returns an error code
  494. */
  495. static int hw_port_test_set(u8 mode)
  496. {
  497. const u8 TEST_MODE_MAX = 7;
  498. if (mode > TEST_MODE_MAX)
  499. return -EINVAL;
  500. hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  501. return 0;
  502. }
  503. /**
  504. * hw_read_intr_enable: returns interrupt enable register
  505. *
  506. * This function returns register data
  507. */
  508. static u32 hw_read_intr_enable(void)
  509. {
  510. return hw_cread(CAP_USBINTR, ~0);
  511. }
  512. /**
  513. * hw_read_intr_status: returns interrupt status register
  514. *
  515. * This function returns register data
  516. */
  517. static u32 hw_read_intr_status(void)
  518. {
  519. return hw_cread(CAP_USBSTS, ~0);
  520. }
  521. /**
  522. * hw_register_read: reads all device registers (execute without interruption)
  523. * @buf: destination buffer
  524. * @size: buffer size
  525. *
  526. * This function returns number of registers read
  527. */
  528. static size_t hw_register_read(u32 *buf, size_t size)
  529. {
  530. unsigned i;
  531. if (size > hw_bank.size)
  532. size = hw_bank.size;
  533. for (i = 0; i < size; i++)
  534. buf[i] = hw_aread(i * sizeof(u32), ~0);
  535. return size;
  536. }
  537. /**
  538. * hw_register_write: writes to register
  539. * @addr: register address
  540. * @data: register value
  541. *
  542. * This function returns an error code
  543. */
  544. static int hw_register_write(u16 addr, u32 data)
  545. {
  546. /* align */
  547. addr /= sizeof(u32);
  548. if (addr >= hw_bank.size)
  549. return -EINVAL;
  550. /* align */
  551. addr *= sizeof(u32);
  552. hw_awrite(addr, ~0, data);
  553. return 0;
  554. }
  555. /**
  556. * hw_test_and_clear_complete: test & clear complete status (execute without
  557. * interruption)
  558. * @n: bit number (endpoint)
  559. *
  560. * This function returns complete status
  561. */
  562. static int hw_test_and_clear_complete(int n)
  563. {
  564. return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
  565. }
  566. /**
  567. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  568. * without interruption)
  569. *
  570. * This function returns active interrutps
  571. */
  572. static u32 hw_test_and_clear_intr_active(void)
  573. {
  574. u32 reg = hw_read_intr_status() & hw_read_intr_enable();
  575. hw_cwrite(CAP_USBSTS, ~0, reg);
  576. return reg;
  577. }
  578. /**
  579. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  580. * interruption)
  581. *
  582. * This function returns guard value
  583. */
  584. static int hw_test_and_clear_setup_guard(void)
  585. {
  586. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
  587. }
  588. /**
  589. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  590. * interruption)
  591. *
  592. * This function returns guard value
  593. */
  594. static int hw_test_and_set_setup_guard(void)
  595. {
  596. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  597. }
  598. /**
  599. * hw_usb_set_address: configures USB address (execute without interruption)
  600. * @value: new USB address
  601. *
  602. * This function returns an error code
  603. */
  604. static int hw_usb_set_address(u8 value)
  605. {
  606. /* advance */
  607. hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  608. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  609. return 0;
  610. }
  611. /**
  612. * hw_usb_reset: restart device after a bus reset (execute without
  613. * interruption)
  614. *
  615. * This function returns an error code
  616. */
  617. static int hw_usb_reset(void)
  618. {
  619. hw_usb_set_address(0);
  620. /* ESS flushes only at end?!? */
  621. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
  622. /* clear setup token semaphores */
  623. hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
  624. /* clear complete status */
  625. hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
  626. /* wait until all bits cleared */
  627. while (hw_cread(CAP_ENDPTPRIME, ~0))
  628. udelay(10); /* not RTOS friendly */
  629. /* reset all endpoints ? */
  630. /* reset internal status and wait for further instructions
  631. no need to verify the port reset status (ESS does it) */
  632. return 0;
  633. }
  634. /******************************************************************************
  635. * DBG block
  636. *****************************************************************************/
  637. /**
  638. * show_device: prints information about device capabilities and status
  639. *
  640. * Check "device.h" for details
  641. */
  642. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  643. char *buf)
  644. {
  645. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  646. struct usb_gadget *gadget = &udc->gadget;
  647. int n = 0;
  648. dbg_trace("[%s] %p\n", __func__, buf);
  649. if (attr == NULL || buf == NULL) {
  650. dev_err(dev, "[%s] EINVAL\n", __func__);
  651. return 0;
  652. }
  653. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  654. gadget->speed);
  655. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  656. gadget->is_dualspeed);
  657. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  658. gadget->is_otg);
  659. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  660. gadget->is_a_peripheral);
  661. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  662. gadget->b_hnp_enable);
  663. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  664. gadget->a_hnp_support);
  665. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  666. gadget->a_alt_hnp_support);
  667. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  668. (gadget->name ? gadget->name : ""));
  669. return n;
  670. }
  671. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  672. /**
  673. * show_driver: prints information about attached gadget (if any)
  674. *
  675. * Check "device.h" for details
  676. */
  677. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  678. char *buf)
  679. {
  680. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  681. struct usb_gadget_driver *driver = udc->driver;
  682. int n = 0;
  683. dbg_trace("[%s] %p\n", __func__, buf);
  684. if (attr == NULL || buf == NULL) {
  685. dev_err(dev, "[%s] EINVAL\n", __func__);
  686. return 0;
  687. }
  688. if (driver == NULL)
  689. return scnprintf(buf, PAGE_SIZE,
  690. "There is no gadget attached!\n");
  691. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  692. (driver->function ? driver->function : ""));
  693. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  694. driver->speed);
  695. return n;
  696. }
  697. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  698. /* Maximum event message length */
  699. #define DBG_DATA_MSG 64UL
  700. /* Maximum event messages */
  701. #define DBG_DATA_MAX 128UL
  702. /* Event buffer descriptor */
  703. static struct {
  704. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  705. unsigned idx; /* index */
  706. unsigned tty; /* print to console? */
  707. rwlock_t lck; /* lock */
  708. } dbg_data = {
  709. .idx = 0,
  710. .tty = 0,
  711. .lck = __RW_LOCK_UNLOCKED(lck)
  712. };
  713. /**
  714. * dbg_dec: decrements debug event index
  715. * @idx: buffer index
  716. */
  717. static void dbg_dec(unsigned *idx)
  718. {
  719. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  720. }
  721. /**
  722. * dbg_inc: increments debug event index
  723. * @idx: buffer index
  724. */
  725. static void dbg_inc(unsigned *idx)
  726. {
  727. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  728. }
  729. /**
  730. * dbg_print: prints the common part of the event
  731. * @addr: endpoint address
  732. * @name: event name
  733. * @status: status
  734. * @extra: extra information
  735. */
  736. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  737. {
  738. struct timeval tval;
  739. unsigned int stamp;
  740. unsigned long flags;
  741. write_lock_irqsave(&dbg_data.lck, flags);
  742. do_gettimeofday(&tval);
  743. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  744. stamp = stamp * 1000000 + tval.tv_usec;
  745. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  746. "%04X\t» %02X %-7.7s %4i «\t%s\n",
  747. stamp, addr, name, status, extra);
  748. dbg_inc(&dbg_data.idx);
  749. write_unlock_irqrestore(&dbg_data.lck, flags);
  750. if (dbg_data.tty != 0)
  751. pr_notice("%04X\t» %02X %-7.7s %4i «\t%s\n",
  752. stamp, addr, name, status, extra);
  753. }
  754. /**
  755. * dbg_done: prints a DONE event
  756. * @addr: endpoint address
  757. * @td: transfer descriptor
  758. * @status: status
  759. */
  760. static void dbg_done(u8 addr, const u32 token, int status)
  761. {
  762. char msg[DBG_DATA_MSG];
  763. scnprintf(msg, sizeof(msg), "%d %02X",
  764. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  765. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  766. dbg_print(addr, "DONE", status, msg);
  767. }
  768. /**
  769. * dbg_event: prints a generic event
  770. * @addr: endpoint address
  771. * @name: event name
  772. * @status: status
  773. */
  774. static void dbg_event(u8 addr, const char *name, int status)
  775. {
  776. if (name != NULL)
  777. dbg_print(addr, name, status, "");
  778. }
  779. /*
  780. * dbg_queue: prints a QUEUE event
  781. * @addr: endpoint address
  782. * @req: USB request
  783. * @status: status
  784. */
  785. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  786. {
  787. char msg[DBG_DATA_MSG];
  788. if (req != NULL) {
  789. scnprintf(msg, sizeof(msg),
  790. "%d %d", !req->no_interrupt, req->length);
  791. dbg_print(addr, "QUEUE", status, msg);
  792. }
  793. }
  794. /**
  795. * dbg_setup: prints a SETUP event
  796. * @addr: endpoint address
  797. * @req: setup request
  798. */
  799. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  800. {
  801. char msg[DBG_DATA_MSG];
  802. if (req != NULL) {
  803. scnprintf(msg, sizeof(msg),
  804. "%02X %02X %04X %04X %d", req->bRequestType,
  805. req->bRequest, le16_to_cpu(req->wValue),
  806. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  807. dbg_print(addr, "SETUP", 0, msg);
  808. }
  809. }
  810. /**
  811. * show_events: displays the event buffer
  812. *
  813. * Check "device.h" for details
  814. */
  815. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  816. char *buf)
  817. {
  818. unsigned long flags;
  819. unsigned i, j, n = 0;
  820. dbg_trace("[%s] %p\n", __func__, buf);
  821. if (attr == NULL || buf == NULL) {
  822. dev_err(dev, "[%s] EINVAL\n", __func__);
  823. return 0;
  824. }
  825. read_lock_irqsave(&dbg_data.lck, flags);
  826. i = dbg_data.idx;
  827. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  828. n += strlen(dbg_data.buf[i]);
  829. if (n >= PAGE_SIZE) {
  830. n -= strlen(dbg_data.buf[i]);
  831. break;
  832. }
  833. }
  834. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  835. j += scnprintf(buf + j, PAGE_SIZE - j,
  836. "%s", dbg_data.buf[i]);
  837. read_unlock_irqrestore(&dbg_data.lck, flags);
  838. return n;
  839. }
  840. /**
  841. * store_events: configure if events are going to be also printed to console
  842. *
  843. * Check "device.h" for details
  844. */
  845. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  846. const char *buf, size_t count)
  847. {
  848. unsigned tty;
  849. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  850. if (attr == NULL || buf == NULL) {
  851. dev_err(dev, "[%s] EINVAL\n", __func__);
  852. goto done;
  853. }
  854. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  855. dev_err(dev, "<1|0>: enable|disable console log\n");
  856. goto done;
  857. }
  858. dbg_data.tty = tty;
  859. dev_info(dev, "tty = %u", dbg_data.tty);
  860. done:
  861. return count;
  862. }
  863. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  864. /**
  865. * show_inters: interrupt status, enable status and historic
  866. *
  867. * Check "device.h" for details
  868. */
  869. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  870. char *buf)
  871. {
  872. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  873. unsigned long flags;
  874. u32 intr;
  875. unsigned i, j, n = 0;
  876. dbg_trace("[%s] %p\n", __func__, buf);
  877. if (attr == NULL || buf == NULL) {
  878. dev_err(dev, "[%s] EINVAL\n", __func__);
  879. return 0;
  880. }
  881. spin_lock_irqsave(udc->lock, flags);
  882. n += scnprintf(buf + n, PAGE_SIZE - n,
  883. "status = %08x\n", hw_read_intr_status());
  884. n += scnprintf(buf + n, PAGE_SIZE - n,
  885. "enable = %08x\n", hw_read_intr_enable());
  886. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  887. isr_statistics.test);
  888. n += scnprintf(buf + n, PAGE_SIZE - n, "» ui = %d\n",
  889. isr_statistics.ui);
  890. n += scnprintf(buf + n, PAGE_SIZE - n, "» uei = %d\n",
  891. isr_statistics.uei);
  892. n += scnprintf(buf + n, PAGE_SIZE - n, "» pci = %d\n",
  893. isr_statistics.pci);
  894. n += scnprintf(buf + n, PAGE_SIZE - n, "» uri = %d\n",
  895. isr_statistics.uri);
  896. n += scnprintf(buf + n, PAGE_SIZE - n, "» sli = %d\n",
  897. isr_statistics.sli);
  898. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  899. isr_statistics.none);
  900. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  901. isr_statistics.hndl.cnt);
  902. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  903. i &= ISR_MASK;
  904. intr = isr_statistics.hndl.buf[i];
  905. if (USBi_UI & intr)
  906. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  907. intr &= ~USBi_UI;
  908. if (USBi_UEI & intr)
  909. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  910. intr &= ~USBi_UEI;
  911. if (USBi_PCI & intr)
  912. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  913. intr &= ~USBi_PCI;
  914. if (USBi_URI & intr)
  915. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  916. intr &= ~USBi_URI;
  917. if (USBi_SLI & intr)
  918. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  919. intr &= ~USBi_SLI;
  920. if (intr)
  921. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  922. if (isr_statistics.hndl.buf[i])
  923. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  924. }
  925. spin_unlock_irqrestore(udc->lock, flags);
  926. return n;
  927. }
  928. /**
  929. * store_inters: enable & force or disable an individual interrutps
  930. * (to be used for test purposes only)
  931. *
  932. * Check "device.h" for details
  933. */
  934. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  935. const char *buf, size_t count)
  936. {
  937. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  938. unsigned long flags;
  939. unsigned en, bit;
  940. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  941. if (attr == NULL || buf == NULL) {
  942. dev_err(dev, "[%s] EINVAL\n", __func__);
  943. goto done;
  944. }
  945. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  946. dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
  947. goto done;
  948. }
  949. spin_lock_irqsave(udc->lock, flags);
  950. if (en) {
  951. if (hw_intr_force(bit))
  952. dev_err(dev, "invalid bit number\n");
  953. else
  954. isr_statistics.test++;
  955. } else {
  956. if (hw_intr_clear(bit))
  957. dev_err(dev, "invalid bit number\n");
  958. }
  959. spin_unlock_irqrestore(udc->lock, flags);
  960. done:
  961. return count;
  962. }
  963. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  964. /**
  965. * show_port_test: reads port test mode
  966. *
  967. * Check "device.h" for details
  968. */
  969. static ssize_t show_port_test(struct device *dev,
  970. struct device_attribute *attr, char *buf)
  971. {
  972. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  973. unsigned long flags;
  974. unsigned mode;
  975. dbg_trace("[%s] %p\n", __func__, buf);
  976. if (attr == NULL || buf == NULL) {
  977. dev_err(dev, "[%s] EINVAL\n", __func__);
  978. return 0;
  979. }
  980. spin_lock_irqsave(udc->lock, flags);
  981. mode = hw_port_test_get();
  982. spin_unlock_irqrestore(udc->lock, flags);
  983. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  984. }
  985. /**
  986. * store_port_test: writes port test mode
  987. *
  988. * Check "device.h" for details
  989. */
  990. static ssize_t store_port_test(struct device *dev,
  991. struct device_attribute *attr,
  992. const char *buf, size_t count)
  993. {
  994. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  995. unsigned long flags;
  996. unsigned mode;
  997. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  998. if (attr == NULL || buf == NULL) {
  999. dev_err(dev, "[%s] EINVAL\n", __func__);
  1000. goto done;
  1001. }
  1002. if (sscanf(buf, "%u", &mode) != 1) {
  1003. dev_err(dev, "<mode>: set port test mode");
  1004. goto done;
  1005. }
  1006. spin_lock_irqsave(udc->lock, flags);
  1007. if (hw_port_test_set(mode))
  1008. dev_err(dev, "invalid mode\n");
  1009. spin_unlock_irqrestore(udc->lock, flags);
  1010. done:
  1011. return count;
  1012. }
  1013. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1014. show_port_test, store_port_test);
  1015. /**
  1016. * show_qheads: DMA contents of all queue heads
  1017. *
  1018. * Check "device.h" for details
  1019. */
  1020. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1021. char *buf)
  1022. {
  1023. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1024. unsigned long flags;
  1025. unsigned i, j, n = 0;
  1026. dbg_trace("[%s] %p\n", __func__, buf);
  1027. if (attr == NULL || buf == NULL) {
  1028. dev_err(dev, "[%s] EINVAL\n", __func__);
  1029. return 0;
  1030. }
  1031. spin_lock_irqsave(udc->lock, flags);
  1032. for (i = 0; i < hw_ep_max/2; i++) {
  1033. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1034. struct ci13xxx_ep *mEpTx = &udc->ci13xxx_ep[i + hw_ep_max/2];
  1035. n += scnprintf(buf + n, PAGE_SIZE - n,
  1036. "EP=%02i: RX=%08X TX=%08X\n",
  1037. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1038. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1039. n += scnprintf(buf + n, PAGE_SIZE - n,
  1040. " %04X: %08X %08X\n", j,
  1041. *((u32 *)mEpRx->qh.ptr + j),
  1042. *((u32 *)mEpTx->qh.ptr + j));
  1043. }
  1044. }
  1045. spin_unlock_irqrestore(udc->lock, flags);
  1046. return n;
  1047. }
  1048. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1049. /**
  1050. * show_registers: dumps all registers
  1051. *
  1052. * Check "device.h" for details
  1053. */
  1054. static ssize_t show_registers(struct device *dev,
  1055. struct device_attribute *attr, char *buf)
  1056. {
  1057. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1058. unsigned long flags;
  1059. u32 dump[512];
  1060. unsigned i, k, n = 0;
  1061. dbg_trace("[%s] %p\n", __func__, buf);
  1062. if (attr == NULL || buf == NULL) {
  1063. dev_err(dev, "[%s] EINVAL\n", __func__);
  1064. return 0;
  1065. }
  1066. spin_lock_irqsave(udc->lock, flags);
  1067. k = hw_register_read(dump, sizeof(dump)/sizeof(u32));
  1068. spin_unlock_irqrestore(udc->lock, flags);
  1069. for (i = 0; i < k; i++) {
  1070. n += scnprintf(buf + n, PAGE_SIZE - n,
  1071. "reg[0x%04X] = 0x%08X\n",
  1072. i * (unsigned)sizeof(u32), dump[i]);
  1073. }
  1074. return n;
  1075. }
  1076. /**
  1077. * store_registers: writes value to register address
  1078. *
  1079. * Check "device.h" for details
  1080. */
  1081. static ssize_t store_registers(struct device *dev,
  1082. struct device_attribute *attr,
  1083. const char *buf, size_t count)
  1084. {
  1085. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1086. unsigned long addr, data, flags;
  1087. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1088. if (attr == NULL || buf == NULL) {
  1089. dev_err(dev, "[%s] EINVAL\n", __func__);
  1090. goto done;
  1091. }
  1092. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1093. dev_err(dev, "<addr> <data>: write data to register address");
  1094. goto done;
  1095. }
  1096. spin_lock_irqsave(udc->lock, flags);
  1097. if (hw_register_write(addr, data))
  1098. dev_err(dev, "invalid address range\n");
  1099. spin_unlock_irqrestore(udc->lock, flags);
  1100. done:
  1101. return count;
  1102. }
  1103. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1104. show_registers, store_registers);
  1105. /**
  1106. * show_requests: DMA contents of all requests currently queued (all endpts)
  1107. *
  1108. * Check "device.h" for details
  1109. */
  1110. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1111. char *buf)
  1112. {
  1113. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1114. unsigned long flags;
  1115. struct list_head *ptr = NULL;
  1116. struct ci13xxx_req *req = NULL;
  1117. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1118. dbg_trace("[%s] %p\n", __func__, buf);
  1119. if (attr == NULL || buf == NULL) {
  1120. dev_err(dev, "[%s] EINVAL\n", __func__);
  1121. return 0;
  1122. }
  1123. spin_lock_irqsave(udc->lock, flags);
  1124. for (i = 0; i < hw_ep_max; i++)
  1125. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1126. {
  1127. req = list_entry(ptr, struct ci13xxx_req, queue);
  1128. n += scnprintf(buf + n, PAGE_SIZE - n,
  1129. "EP=%02i: TD=%08X %s\n",
  1130. i % hw_ep_max/2, (u32)req->dma,
  1131. ((i < hw_ep_max/2) ? "RX" : "TX"));
  1132. for (j = 0; j < qSize; j++)
  1133. n += scnprintf(buf + n, PAGE_SIZE - n,
  1134. " %04X: %08X\n", j,
  1135. *((u32 *)req->ptr + j));
  1136. }
  1137. spin_unlock_irqrestore(udc->lock, flags);
  1138. return n;
  1139. }
  1140. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1141. /**
  1142. * dbg_create_files: initializes the attribute interface
  1143. * @dev: device
  1144. *
  1145. * This function returns an error code
  1146. */
  1147. __maybe_unused static int dbg_create_files(struct device *dev)
  1148. {
  1149. int retval = 0;
  1150. if (dev == NULL)
  1151. return -EINVAL;
  1152. retval = device_create_file(dev, &dev_attr_device);
  1153. if (retval)
  1154. goto done;
  1155. retval = device_create_file(dev, &dev_attr_driver);
  1156. if (retval)
  1157. goto rm_device;
  1158. retval = device_create_file(dev, &dev_attr_events);
  1159. if (retval)
  1160. goto rm_driver;
  1161. retval = device_create_file(dev, &dev_attr_inters);
  1162. if (retval)
  1163. goto rm_events;
  1164. retval = device_create_file(dev, &dev_attr_port_test);
  1165. if (retval)
  1166. goto rm_inters;
  1167. retval = device_create_file(dev, &dev_attr_qheads);
  1168. if (retval)
  1169. goto rm_port_test;
  1170. retval = device_create_file(dev, &dev_attr_registers);
  1171. if (retval)
  1172. goto rm_qheads;
  1173. retval = device_create_file(dev, &dev_attr_requests);
  1174. if (retval)
  1175. goto rm_registers;
  1176. return 0;
  1177. rm_registers:
  1178. device_remove_file(dev, &dev_attr_registers);
  1179. rm_qheads:
  1180. device_remove_file(dev, &dev_attr_qheads);
  1181. rm_port_test:
  1182. device_remove_file(dev, &dev_attr_port_test);
  1183. rm_inters:
  1184. device_remove_file(dev, &dev_attr_inters);
  1185. rm_events:
  1186. device_remove_file(dev, &dev_attr_events);
  1187. rm_driver:
  1188. device_remove_file(dev, &dev_attr_driver);
  1189. rm_device:
  1190. device_remove_file(dev, &dev_attr_device);
  1191. done:
  1192. return retval;
  1193. }
  1194. /**
  1195. * dbg_remove_files: destroys the attribute interface
  1196. * @dev: device
  1197. *
  1198. * This function returns an error code
  1199. */
  1200. __maybe_unused static int dbg_remove_files(struct device *dev)
  1201. {
  1202. if (dev == NULL)
  1203. return -EINVAL;
  1204. device_remove_file(dev, &dev_attr_requests);
  1205. device_remove_file(dev, &dev_attr_registers);
  1206. device_remove_file(dev, &dev_attr_qheads);
  1207. device_remove_file(dev, &dev_attr_port_test);
  1208. device_remove_file(dev, &dev_attr_inters);
  1209. device_remove_file(dev, &dev_attr_events);
  1210. device_remove_file(dev, &dev_attr_driver);
  1211. device_remove_file(dev, &dev_attr_device);
  1212. return 0;
  1213. }
  1214. /******************************************************************************
  1215. * UTIL block
  1216. *****************************************************************************/
  1217. /**
  1218. * _usb_addr: calculates endpoint address from direction & number
  1219. * @ep: endpoint
  1220. */
  1221. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1222. {
  1223. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1224. }
  1225. /**
  1226. * _hardware_queue: configures a request at hardware level
  1227. * @gadget: gadget
  1228. * @mEp: endpoint
  1229. *
  1230. * This function returns an error code
  1231. */
  1232. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1233. {
  1234. unsigned i;
  1235. int ret = 0;
  1236. unsigned length = mReq->req.length;
  1237. trace("%p, %p", mEp, mReq);
  1238. /* don't queue twice */
  1239. if (mReq->req.status == -EALREADY)
  1240. return -EALREADY;
  1241. mReq->req.status = -EALREADY;
  1242. if (length && !mReq->req.dma) {
  1243. mReq->req.dma = \
  1244. dma_map_single(mEp->device, mReq->req.buf,
  1245. length, mEp->dir ? DMA_TO_DEVICE :
  1246. DMA_FROM_DEVICE);
  1247. if (mReq->req.dma == 0)
  1248. return -ENOMEM;
  1249. mReq->map = 1;
  1250. }
  1251. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1252. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1253. &mReq->zdma);
  1254. if (mReq->zptr == NULL) {
  1255. if (mReq->map) {
  1256. dma_unmap_single(mEp->device, mReq->req.dma,
  1257. length, mEp->dir ? DMA_TO_DEVICE :
  1258. DMA_FROM_DEVICE);
  1259. mReq->req.dma = 0;
  1260. mReq->map = 0;
  1261. }
  1262. return -ENOMEM;
  1263. }
  1264. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1265. mReq->zptr->next = TD_TERMINATE;
  1266. mReq->zptr->token = TD_STATUS_ACTIVE;
  1267. if (!mReq->req.no_interrupt)
  1268. mReq->zptr->token |= TD_IOC;
  1269. }
  1270. /*
  1271. * TD configuration
  1272. * TODO - handle requests which spawns into several TDs
  1273. */
  1274. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1275. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1276. mReq->ptr->token &= TD_TOTAL_BYTES;
  1277. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1278. if (mReq->zptr) {
  1279. mReq->ptr->next = mReq->zdma;
  1280. } else {
  1281. mReq->ptr->next = TD_TERMINATE;
  1282. if (!mReq->req.no_interrupt)
  1283. mReq->ptr->token |= TD_IOC;
  1284. }
  1285. mReq->ptr->page[0] = mReq->req.dma;
  1286. for (i = 1; i < 5; i++)
  1287. mReq->ptr->page[i] =
  1288. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1289. if (!list_empty(&mEp->qh.queue)) {
  1290. struct ci13xxx_req *mReqPrev;
  1291. int n = hw_ep_bit(mEp->num, mEp->dir);
  1292. int tmp_stat;
  1293. mReqPrev = list_entry(mEp->qh.queue.prev,
  1294. struct ci13xxx_req, queue);
  1295. if (mReqPrev->zptr)
  1296. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1297. else
  1298. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1299. wmb();
  1300. if (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  1301. goto done;
  1302. do {
  1303. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1304. tmp_stat = hw_cread(CAP_ENDPTSTAT, BIT(n));
  1305. } while (!hw_cread(CAP_USBCMD, USBCMD_ATDTW));
  1306. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, 0);
  1307. if (tmp_stat)
  1308. goto done;
  1309. }
  1310. /* QH configuration */
  1311. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1312. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1313. mEp->qh.ptr->cap |= QH_ZLT;
  1314. wmb(); /* synchronize before ep prime */
  1315. ret = hw_ep_prime(mEp->num, mEp->dir,
  1316. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1317. done:
  1318. return ret;
  1319. }
  1320. /**
  1321. * _hardware_dequeue: handles a request at hardware level
  1322. * @gadget: gadget
  1323. * @mEp: endpoint
  1324. *
  1325. * This function returns an error code
  1326. */
  1327. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1328. {
  1329. trace("%p, %p", mEp, mReq);
  1330. if (mReq->req.status != -EALREADY)
  1331. return -EINVAL;
  1332. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1333. return -EBUSY;
  1334. if (mReq->zptr) {
  1335. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1336. return -EBUSY;
  1337. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1338. mReq->zptr = NULL;
  1339. }
  1340. mReq->req.status = 0;
  1341. if (mReq->map) {
  1342. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1343. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1344. mReq->req.dma = 0;
  1345. mReq->map = 0;
  1346. }
  1347. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1348. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1349. mReq->req.status = -1;
  1350. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1351. mReq->req.status = -1;
  1352. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1353. mReq->req.status = -1;
  1354. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1355. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1356. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1357. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1358. return mReq->req.actual;
  1359. }
  1360. /**
  1361. * _ep_nuke: dequeues all endpoint requests
  1362. * @mEp: endpoint
  1363. *
  1364. * This function returns an error code
  1365. * Caller must hold lock
  1366. */
  1367. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1368. __releases(mEp->lock)
  1369. __acquires(mEp->lock)
  1370. {
  1371. trace("%p", mEp);
  1372. if (mEp == NULL)
  1373. return -EINVAL;
  1374. hw_ep_flush(mEp->num, mEp->dir);
  1375. while (!list_empty(&mEp->qh.queue)) {
  1376. /* pop oldest request */
  1377. struct ci13xxx_req *mReq = \
  1378. list_entry(mEp->qh.queue.next,
  1379. struct ci13xxx_req, queue);
  1380. list_del_init(&mReq->queue);
  1381. mReq->req.status = -ESHUTDOWN;
  1382. if (mReq->req.complete != NULL) {
  1383. spin_unlock(mEp->lock);
  1384. mReq->req.complete(&mEp->ep, &mReq->req);
  1385. spin_lock(mEp->lock);
  1386. }
  1387. }
  1388. return 0;
  1389. }
  1390. /**
  1391. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1392. * @gadget: gadget
  1393. *
  1394. * This function returns an error code
  1395. * Caller must hold lock
  1396. */
  1397. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1398. {
  1399. struct usb_ep *ep;
  1400. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1401. unsigned long flags;
  1402. trace("%p", gadget);
  1403. if (gadget == NULL)
  1404. return -EINVAL;
  1405. spin_lock_irqsave(udc->lock, flags);
  1406. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1407. udc->remote_wakeup = 0;
  1408. udc->suspended = 0;
  1409. spin_unlock_irqrestore(udc->lock, flags);
  1410. /* flush all endpoints */
  1411. gadget_for_each_ep(ep, gadget) {
  1412. usb_ep_fifo_flush(ep);
  1413. }
  1414. usb_ep_fifo_flush(&udc->ep0out.ep);
  1415. usb_ep_fifo_flush(&udc->ep0in.ep);
  1416. udc->driver->disconnect(gadget);
  1417. /* make sure to disable all endpoints */
  1418. gadget_for_each_ep(ep, gadget) {
  1419. usb_ep_disable(ep);
  1420. }
  1421. usb_ep_disable(&udc->ep0out.ep);
  1422. usb_ep_disable(&udc->ep0in.ep);
  1423. if (udc->status != NULL) {
  1424. usb_ep_free_request(&udc->ep0in.ep, udc->status);
  1425. udc->status = NULL;
  1426. }
  1427. return 0;
  1428. }
  1429. /******************************************************************************
  1430. * ISR block
  1431. *****************************************************************************/
  1432. /**
  1433. * isr_reset_handler: USB reset interrupt handler
  1434. * @udc: UDC device
  1435. *
  1436. * This function resets USB engine after a bus reset occurred
  1437. */
  1438. static void isr_reset_handler(struct ci13xxx *udc)
  1439. __releases(udc->lock)
  1440. __acquires(udc->lock)
  1441. {
  1442. int retval;
  1443. trace("%p", udc);
  1444. if (udc == NULL) {
  1445. err("EINVAL");
  1446. return;
  1447. }
  1448. dbg_event(0xFF, "BUS RST", 0);
  1449. spin_unlock(udc->lock);
  1450. retval = _gadget_stop_activity(&udc->gadget);
  1451. if (retval)
  1452. goto done;
  1453. retval = hw_usb_reset();
  1454. if (retval)
  1455. goto done;
  1456. retval = usb_ep_enable(&udc->ep0out.ep, &ctrl_endpt_out_desc);
  1457. if (retval)
  1458. goto done;
  1459. retval = usb_ep_enable(&udc->ep0in.ep, &ctrl_endpt_in_desc);
  1460. if (!retval) {
  1461. udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
  1462. if (udc->status == NULL) {
  1463. usb_ep_disable(&udc->ep0out.ep);
  1464. retval = -ENOMEM;
  1465. }
  1466. }
  1467. spin_lock(udc->lock);
  1468. done:
  1469. if (retval)
  1470. err("error: %i", retval);
  1471. }
  1472. /**
  1473. * isr_get_status_complete: get_status request complete function
  1474. * @ep: endpoint
  1475. * @req: request handled
  1476. *
  1477. * Caller must release lock
  1478. */
  1479. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1480. {
  1481. trace("%p, %p", ep, req);
  1482. if (ep == NULL || req == NULL) {
  1483. err("EINVAL");
  1484. return;
  1485. }
  1486. kfree(req->buf);
  1487. usb_ep_free_request(ep, req);
  1488. }
  1489. /**
  1490. * isr_get_status_response: get_status request response
  1491. * @udc: udc struct
  1492. * @setup: setup request packet
  1493. *
  1494. * This function returns an error code
  1495. */
  1496. static int isr_get_status_response(struct ci13xxx *udc,
  1497. struct usb_ctrlrequest *setup)
  1498. __releases(mEp->lock)
  1499. __acquires(mEp->lock)
  1500. {
  1501. struct ci13xxx_ep *mEp = &udc->ep0in;
  1502. struct usb_request *req = NULL;
  1503. gfp_t gfp_flags = GFP_ATOMIC;
  1504. int dir, num, retval;
  1505. trace("%p, %p", mEp, setup);
  1506. if (mEp == NULL || setup == NULL)
  1507. return -EINVAL;
  1508. spin_unlock(mEp->lock);
  1509. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1510. spin_lock(mEp->lock);
  1511. if (req == NULL)
  1512. return -ENOMEM;
  1513. req->complete = isr_get_status_complete;
  1514. req->length = 2;
  1515. req->buf = kzalloc(req->length, gfp_flags);
  1516. if (req->buf == NULL) {
  1517. retval = -ENOMEM;
  1518. goto err_free_req;
  1519. }
  1520. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1521. /* Assume that device is bus powered for now. */
  1522. *((u16 *)req->buf) = _udc->remote_wakeup << 1;
  1523. retval = 0;
  1524. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1525. == USB_RECIP_ENDPOINT) {
  1526. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1527. TX : RX;
  1528. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1529. *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
  1530. }
  1531. /* else do nothing; reserved for future use */
  1532. spin_unlock(mEp->lock);
  1533. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1534. spin_lock(mEp->lock);
  1535. if (retval)
  1536. goto err_free_buf;
  1537. return 0;
  1538. err_free_buf:
  1539. kfree(req->buf);
  1540. err_free_req:
  1541. spin_unlock(mEp->lock);
  1542. usb_ep_free_request(&mEp->ep, req);
  1543. spin_lock(mEp->lock);
  1544. return retval;
  1545. }
  1546. /**
  1547. * isr_setup_status_complete: setup_status request complete function
  1548. * @ep: endpoint
  1549. * @req: request handled
  1550. *
  1551. * Caller must release lock. Put the port in test mode if test mode
  1552. * feature is selected.
  1553. */
  1554. static void
  1555. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1556. {
  1557. struct ci13xxx *udc = req->context;
  1558. unsigned long flags;
  1559. trace("%p, %p", ep, req);
  1560. spin_lock_irqsave(udc->lock, flags);
  1561. if (udc->test_mode)
  1562. hw_port_test_set(udc->test_mode);
  1563. spin_unlock_irqrestore(udc->lock, flags);
  1564. }
  1565. /**
  1566. * isr_setup_status_phase: queues the status phase of a setup transation
  1567. * @udc: udc struct
  1568. *
  1569. * This function returns an error code
  1570. */
  1571. static int isr_setup_status_phase(struct ci13xxx *udc)
  1572. __releases(mEp->lock)
  1573. __acquires(mEp->lock)
  1574. {
  1575. int retval;
  1576. struct ci13xxx_ep *mEp;
  1577. trace("%p", udc);
  1578. mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
  1579. udc->status->context = udc;
  1580. udc->status->complete = isr_setup_status_complete;
  1581. spin_unlock(mEp->lock);
  1582. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1583. spin_lock(mEp->lock);
  1584. return retval;
  1585. }
  1586. /**
  1587. * isr_tr_complete_low: transaction complete low level handler
  1588. * @mEp: endpoint
  1589. *
  1590. * This function returns an error code
  1591. * Caller must hold lock
  1592. */
  1593. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1594. __releases(mEp->lock)
  1595. __acquires(mEp->lock)
  1596. {
  1597. struct ci13xxx_req *mReq, *mReqTemp;
  1598. int retval;
  1599. trace("%p", mEp);
  1600. if (list_empty(&mEp->qh.queue))
  1601. return -EINVAL;
  1602. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1603. queue) {
  1604. retval = _hardware_dequeue(mEp, mReq);
  1605. if (retval < 0)
  1606. break;
  1607. list_del_init(&mReq->queue);
  1608. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1609. if (mReq->req.complete != NULL) {
  1610. spin_unlock(mEp->lock);
  1611. mReq->req.complete(&mEp->ep, &mReq->req);
  1612. spin_lock(mEp->lock);
  1613. }
  1614. }
  1615. if (retval == EBUSY)
  1616. retval = 0;
  1617. if (retval < 0)
  1618. dbg_event(_usb_addr(mEp), "DONE", retval);
  1619. return retval;
  1620. }
  1621. /**
  1622. * isr_tr_complete_handler: transaction complete interrupt handler
  1623. * @udc: UDC descriptor
  1624. *
  1625. * This function handles traffic events
  1626. */
  1627. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1628. __releases(udc->lock)
  1629. __acquires(udc->lock)
  1630. {
  1631. unsigned i;
  1632. u8 tmode = 0;
  1633. trace("%p", udc);
  1634. if (udc == NULL) {
  1635. err("EINVAL");
  1636. return;
  1637. }
  1638. for (i = 0; i < hw_ep_max; i++) {
  1639. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1640. int type, num, err = -EINVAL;
  1641. struct usb_ctrlrequest req;
  1642. if (mEp->desc == NULL)
  1643. continue; /* not configured */
  1644. if (hw_test_and_clear_complete(i)) {
  1645. err = isr_tr_complete_low(mEp);
  1646. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1647. if (err > 0) /* needs status phase */
  1648. err = isr_setup_status_phase(udc);
  1649. if (err < 0) {
  1650. dbg_event(_usb_addr(mEp),
  1651. "ERROR", err);
  1652. spin_unlock(udc->lock);
  1653. if (usb_ep_set_halt(&mEp->ep))
  1654. err("error: ep_set_halt");
  1655. spin_lock(udc->lock);
  1656. }
  1657. }
  1658. }
  1659. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1660. !hw_test_and_clear_setup_status(i))
  1661. continue;
  1662. if (i != 0) {
  1663. warn("ctrl traffic received at endpoint");
  1664. continue;
  1665. }
  1666. /*
  1667. * Flush data and handshake transactions of previous
  1668. * setup packet.
  1669. */
  1670. _ep_nuke(&udc->ep0out);
  1671. _ep_nuke(&udc->ep0in);
  1672. /* read_setup_packet */
  1673. do {
  1674. hw_test_and_set_setup_guard();
  1675. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1676. } while (!hw_test_and_clear_setup_guard());
  1677. type = req.bRequestType;
  1678. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1679. dbg_setup(_usb_addr(mEp), &req);
  1680. switch (req.bRequest) {
  1681. case USB_REQ_CLEAR_FEATURE:
  1682. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1683. le16_to_cpu(req.wValue) ==
  1684. USB_ENDPOINT_HALT) {
  1685. if (req.wLength != 0)
  1686. break;
  1687. num = le16_to_cpu(req.wIndex);
  1688. num &= USB_ENDPOINT_NUMBER_MASK;
  1689. if (!udc->ci13xxx_ep[num].wedge) {
  1690. spin_unlock(udc->lock);
  1691. err = usb_ep_clear_halt(
  1692. &udc->ci13xxx_ep[num].ep);
  1693. spin_lock(udc->lock);
  1694. if (err)
  1695. break;
  1696. }
  1697. err = isr_setup_status_phase(udc);
  1698. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1699. le16_to_cpu(req.wValue) ==
  1700. USB_DEVICE_REMOTE_WAKEUP) {
  1701. if (req.wLength != 0)
  1702. break;
  1703. udc->remote_wakeup = 0;
  1704. err = isr_setup_status_phase(udc);
  1705. } else {
  1706. goto delegate;
  1707. }
  1708. break;
  1709. case USB_REQ_GET_STATUS:
  1710. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1711. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1712. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1713. goto delegate;
  1714. if (le16_to_cpu(req.wLength) != 2 ||
  1715. le16_to_cpu(req.wValue) != 0)
  1716. break;
  1717. err = isr_get_status_response(udc, &req);
  1718. break;
  1719. case USB_REQ_SET_ADDRESS:
  1720. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1721. goto delegate;
  1722. if (le16_to_cpu(req.wLength) != 0 ||
  1723. le16_to_cpu(req.wIndex) != 0)
  1724. break;
  1725. err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
  1726. if (err)
  1727. break;
  1728. err = isr_setup_status_phase(udc);
  1729. break;
  1730. case USB_REQ_SET_FEATURE:
  1731. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1732. le16_to_cpu(req.wValue) ==
  1733. USB_ENDPOINT_HALT) {
  1734. if (req.wLength != 0)
  1735. break;
  1736. num = le16_to_cpu(req.wIndex);
  1737. num &= USB_ENDPOINT_NUMBER_MASK;
  1738. spin_unlock(udc->lock);
  1739. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1740. spin_lock(udc->lock);
  1741. if (!err)
  1742. isr_setup_status_phase(udc);
  1743. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1744. if (req.wLength != 0)
  1745. break;
  1746. switch (le16_to_cpu(req.wValue)) {
  1747. case USB_DEVICE_REMOTE_WAKEUP:
  1748. udc->remote_wakeup = 1;
  1749. err = isr_setup_status_phase(udc);
  1750. break;
  1751. case USB_DEVICE_TEST_MODE:
  1752. tmode = le16_to_cpu(req.wIndex) >> 8;
  1753. switch (tmode) {
  1754. case TEST_J:
  1755. case TEST_K:
  1756. case TEST_SE0_NAK:
  1757. case TEST_PACKET:
  1758. case TEST_FORCE_EN:
  1759. udc->test_mode = tmode;
  1760. err = isr_setup_status_phase(
  1761. udc);
  1762. break;
  1763. default:
  1764. break;
  1765. }
  1766. default:
  1767. goto delegate;
  1768. }
  1769. } else {
  1770. goto delegate;
  1771. }
  1772. break;
  1773. default:
  1774. delegate:
  1775. if (req.wLength == 0) /* no data phase */
  1776. udc->ep0_dir = TX;
  1777. spin_unlock(udc->lock);
  1778. err = udc->driver->setup(&udc->gadget, &req);
  1779. spin_lock(udc->lock);
  1780. break;
  1781. }
  1782. if (err < 0) {
  1783. dbg_event(_usb_addr(mEp), "ERROR", err);
  1784. spin_unlock(udc->lock);
  1785. if (usb_ep_set_halt(&mEp->ep))
  1786. err("error: ep_set_halt");
  1787. spin_lock(udc->lock);
  1788. }
  1789. }
  1790. }
  1791. /******************************************************************************
  1792. * ENDPT block
  1793. *****************************************************************************/
  1794. /**
  1795. * ep_enable: configure endpoint, making it usable
  1796. *
  1797. * Check usb_ep_enable() at "usb_gadget.h" for details
  1798. */
  1799. static int ep_enable(struct usb_ep *ep,
  1800. const struct usb_endpoint_descriptor *desc)
  1801. {
  1802. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1803. int retval = 0;
  1804. unsigned long flags;
  1805. trace("%p, %p", ep, desc);
  1806. if (ep == NULL || desc == NULL)
  1807. return -EINVAL;
  1808. spin_lock_irqsave(mEp->lock, flags);
  1809. /* only internal SW should enable ctrl endpts */
  1810. mEp->desc = desc;
  1811. if (!list_empty(&mEp->qh.queue))
  1812. warn("enabling a non-empty endpoint!");
  1813. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1814. mEp->num = usb_endpoint_num(desc);
  1815. mEp->type = usb_endpoint_type(desc);
  1816. mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
  1817. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1818. mEp->qh.ptr->cap = 0;
  1819. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1820. mEp->qh.ptr->cap |= QH_IOS;
  1821. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1822. mEp->qh.ptr->cap &= ~QH_MULT;
  1823. else
  1824. mEp->qh.ptr->cap &= ~QH_ZLT;
  1825. mEp->qh.ptr->cap |=
  1826. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1827. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1828. retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
  1829. spin_unlock_irqrestore(mEp->lock, flags);
  1830. return retval;
  1831. }
  1832. /**
  1833. * ep_disable: endpoint is no longer usable
  1834. *
  1835. * Check usb_ep_disable() at "usb_gadget.h" for details
  1836. */
  1837. static int ep_disable(struct usb_ep *ep)
  1838. {
  1839. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1840. int direction, retval = 0;
  1841. unsigned long flags;
  1842. trace("%p", ep);
  1843. if (ep == NULL)
  1844. return -EINVAL;
  1845. else if (mEp->desc == NULL)
  1846. return -EBUSY;
  1847. spin_lock_irqsave(mEp->lock, flags);
  1848. /* only internal SW should disable ctrl endpts */
  1849. direction = mEp->dir;
  1850. do {
  1851. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1852. retval |= _ep_nuke(mEp);
  1853. retval |= hw_ep_disable(mEp->num, mEp->dir);
  1854. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1855. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1856. } while (mEp->dir != direction);
  1857. mEp->desc = NULL;
  1858. spin_unlock_irqrestore(mEp->lock, flags);
  1859. return retval;
  1860. }
  1861. /**
  1862. * ep_alloc_request: allocate a request object to use with this endpoint
  1863. *
  1864. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1865. */
  1866. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1867. {
  1868. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1869. struct ci13xxx_req *mReq = NULL;
  1870. trace("%p, %i", ep, gfp_flags);
  1871. if (ep == NULL) {
  1872. err("EINVAL");
  1873. return NULL;
  1874. }
  1875. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1876. if (mReq != NULL) {
  1877. INIT_LIST_HEAD(&mReq->queue);
  1878. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1879. &mReq->dma);
  1880. if (mReq->ptr == NULL) {
  1881. kfree(mReq);
  1882. mReq = NULL;
  1883. }
  1884. }
  1885. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1886. return (mReq == NULL) ? NULL : &mReq->req;
  1887. }
  1888. /**
  1889. * ep_free_request: frees a request object
  1890. *
  1891. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1892. */
  1893. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1894. {
  1895. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1896. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1897. unsigned long flags;
  1898. trace("%p, %p", ep, req);
  1899. if (ep == NULL || req == NULL) {
  1900. err("EINVAL");
  1901. return;
  1902. } else if (!list_empty(&mReq->queue)) {
  1903. err("EBUSY");
  1904. return;
  1905. }
  1906. spin_lock_irqsave(mEp->lock, flags);
  1907. if (mReq->ptr)
  1908. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1909. kfree(mReq);
  1910. dbg_event(_usb_addr(mEp), "FREE", 0);
  1911. spin_unlock_irqrestore(mEp->lock, flags);
  1912. }
  1913. /**
  1914. * ep_queue: queues (submits) an I/O request to an endpoint
  1915. *
  1916. * Check usb_ep_queue()* at usb_gadget.h" for details
  1917. */
  1918. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1919. gfp_t __maybe_unused gfp_flags)
  1920. {
  1921. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1922. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1923. int retval = 0;
  1924. unsigned long flags;
  1925. trace("%p, %p, %X", ep, req, gfp_flags);
  1926. if (ep == NULL || req == NULL || mEp->desc == NULL)
  1927. return -EINVAL;
  1928. spin_lock_irqsave(mEp->lock, flags);
  1929. if (mEp->type == USB_ENDPOINT_XFER_CONTROL &&
  1930. !list_empty(&mEp->qh.queue)) {
  1931. _ep_nuke(mEp);
  1932. retval = -EOVERFLOW;
  1933. warn("endpoint ctrl %X nuked", _usb_addr(mEp));
  1934. }
  1935. /* first nuke then test link, e.g. previous status has not sent */
  1936. if (!list_empty(&mReq->queue)) {
  1937. retval = -EBUSY;
  1938. err("request already in queue");
  1939. goto done;
  1940. }
  1941. if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
  1942. req->length = (4 * CI13XXX_PAGE_SIZE);
  1943. retval = -EMSGSIZE;
  1944. warn("request length truncated");
  1945. }
  1946. dbg_queue(_usb_addr(mEp), req, retval);
  1947. /* push request */
  1948. mReq->req.status = -EINPROGRESS;
  1949. mReq->req.actual = 0;
  1950. retval = _hardware_enqueue(mEp, mReq);
  1951. if (retval == -EALREADY) {
  1952. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1953. retval = 0;
  1954. }
  1955. if (!retval)
  1956. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1957. done:
  1958. spin_unlock_irqrestore(mEp->lock, flags);
  1959. return retval;
  1960. }
  1961. /**
  1962. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1963. *
  1964. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1965. */
  1966. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1967. {
  1968. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1969. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1970. unsigned long flags;
  1971. trace("%p, %p", ep, req);
  1972. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  1973. mEp->desc == NULL || list_empty(&mReq->queue) ||
  1974. list_empty(&mEp->qh.queue))
  1975. return -EINVAL;
  1976. spin_lock_irqsave(mEp->lock, flags);
  1977. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  1978. hw_ep_flush(mEp->num, mEp->dir);
  1979. /* pop request */
  1980. list_del_init(&mReq->queue);
  1981. if (mReq->map) {
  1982. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1983. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1984. mReq->req.dma = 0;
  1985. mReq->map = 0;
  1986. }
  1987. req->status = -ECONNRESET;
  1988. if (mReq->req.complete != NULL) {
  1989. spin_unlock(mEp->lock);
  1990. mReq->req.complete(&mEp->ep, &mReq->req);
  1991. spin_lock(mEp->lock);
  1992. }
  1993. spin_unlock_irqrestore(mEp->lock, flags);
  1994. return 0;
  1995. }
  1996. /**
  1997. * ep_set_halt: sets the endpoint halt feature
  1998. *
  1999. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2000. */
  2001. static int ep_set_halt(struct usb_ep *ep, int value)
  2002. {
  2003. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2004. int direction, retval = 0;
  2005. unsigned long flags;
  2006. trace("%p, %i", ep, value);
  2007. if (ep == NULL || mEp->desc == NULL)
  2008. return -EINVAL;
  2009. spin_lock_irqsave(mEp->lock, flags);
  2010. #ifndef STALL_IN
  2011. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2012. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2013. !list_empty(&mEp->qh.queue)) {
  2014. spin_unlock_irqrestore(mEp->lock, flags);
  2015. return -EAGAIN;
  2016. }
  2017. #endif
  2018. direction = mEp->dir;
  2019. do {
  2020. dbg_event(_usb_addr(mEp), "HALT", value);
  2021. retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
  2022. if (!value)
  2023. mEp->wedge = 0;
  2024. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2025. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2026. } while (mEp->dir != direction);
  2027. spin_unlock_irqrestore(mEp->lock, flags);
  2028. return retval;
  2029. }
  2030. /**
  2031. * ep_set_wedge: sets the halt feature and ignores clear requests
  2032. *
  2033. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2034. */
  2035. static int ep_set_wedge(struct usb_ep *ep)
  2036. {
  2037. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2038. unsigned long flags;
  2039. trace("%p", ep);
  2040. if (ep == NULL || mEp->desc == NULL)
  2041. return -EINVAL;
  2042. spin_lock_irqsave(mEp->lock, flags);
  2043. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2044. mEp->wedge = 1;
  2045. spin_unlock_irqrestore(mEp->lock, flags);
  2046. return usb_ep_set_halt(ep);
  2047. }
  2048. /**
  2049. * ep_fifo_flush: flushes contents of a fifo
  2050. *
  2051. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2052. */
  2053. static void ep_fifo_flush(struct usb_ep *ep)
  2054. {
  2055. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2056. unsigned long flags;
  2057. trace("%p", ep);
  2058. if (ep == NULL) {
  2059. err("%02X: -EINVAL", _usb_addr(mEp));
  2060. return;
  2061. }
  2062. spin_lock_irqsave(mEp->lock, flags);
  2063. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2064. hw_ep_flush(mEp->num, mEp->dir);
  2065. spin_unlock_irqrestore(mEp->lock, flags);
  2066. }
  2067. /**
  2068. * Endpoint-specific part of the API to the USB controller hardware
  2069. * Check "usb_gadget.h" for details
  2070. */
  2071. static const struct usb_ep_ops usb_ep_ops = {
  2072. .enable = ep_enable,
  2073. .disable = ep_disable,
  2074. .alloc_request = ep_alloc_request,
  2075. .free_request = ep_free_request,
  2076. .queue = ep_queue,
  2077. .dequeue = ep_dequeue,
  2078. .set_halt = ep_set_halt,
  2079. .set_wedge = ep_set_wedge,
  2080. .fifo_flush = ep_fifo_flush,
  2081. };
  2082. /******************************************************************************
  2083. * GADGET block
  2084. *****************************************************************************/
  2085. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2086. {
  2087. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2088. unsigned long flags;
  2089. int gadget_ready = 0;
  2090. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2091. return -EOPNOTSUPP;
  2092. spin_lock_irqsave(udc->lock, flags);
  2093. udc->vbus_active = is_active;
  2094. if (udc->driver)
  2095. gadget_ready = 1;
  2096. spin_unlock_irqrestore(udc->lock, flags);
  2097. if (gadget_ready) {
  2098. if (is_active) {
  2099. pm_runtime_get_sync(&_gadget->dev);
  2100. hw_device_reset(udc);
  2101. hw_device_state(udc->ep0out.qh.dma);
  2102. } else {
  2103. hw_device_state(0);
  2104. if (udc->udc_driver->notify_event)
  2105. udc->udc_driver->notify_event(udc,
  2106. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2107. _gadget_stop_activity(&udc->gadget);
  2108. pm_runtime_put_sync(&_gadget->dev);
  2109. }
  2110. }
  2111. return 0;
  2112. }
  2113. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2114. {
  2115. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2116. unsigned long flags;
  2117. int ret = 0;
  2118. trace();
  2119. spin_lock_irqsave(udc->lock, flags);
  2120. if (!udc->remote_wakeup) {
  2121. ret = -EOPNOTSUPP;
  2122. dbg_trace("remote wakeup feature is not enabled\n");
  2123. goto out;
  2124. }
  2125. if (!hw_cread(CAP_PORTSC, PORTSC_SUSP)) {
  2126. ret = -EINVAL;
  2127. dbg_trace("port is not suspended\n");
  2128. goto out;
  2129. }
  2130. hw_cwrite(CAP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2131. out:
  2132. spin_unlock_irqrestore(udc->lock, flags);
  2133. return ret;
  2134. }
  2135. /**
  2136. * Device operations part of the API to the USB controller hardware,
  2137. * which don't involve endpoints (or i/o)
  2138. * Check "usb_gadget.h" for details
  2139. */
  2140. static const struct usb_gadget_ops usb_gadget_ops = {
  2141. .vbus_session = ci13xxx_vbus_session,
  2142. .wakeup = ci13xxx_wakeup,
  2143. };
  2144. /**
  2145. * usb_gadget_probe_driver: register a gadget driver
  2146. * @driver: the driver being registered
  2147. * @bind: the driver's bind callback
  2148. *
  2149. * Check usb_gadget_probe_driver() at <linux/usb/gadget.h> for details.
  2150. * Interrupts are enabled here.
  2151. */
  2152. int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
  2153. int (*bind)(struct usb_gadget *))
  2154. {
  2155. struct ci13xxx *udc = _udc;
  2156. unsigned long flags;
  2157. int i, j;
  2158. int retval = -ENOMEM;
  2159. trace("%p", driver);
  2160. if (driver == NULL ||
  2161. bind == NULL ||
  2162. driver->setup == NULL ||
  2163. driver->disconnect == NULL ||
  2164. driver->suspend == NULL ||
  2165. driver->resume == NULL)
  2166. return -EINVAL;
  2167. else if (udc == NULL)
  2168. return -ENODEV;
  2169. else if (udc->driver != NULL)
  2170. return -EBUSY;
  2171. /* alloc resources */
  2172. udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
  2173. sizeof(struct ci13xxx_qh),
  2174. 64, CI13XXX_PAGE_SIZE);
  2175. if (udc->qh_pool == NULL)
  2176. return -ENOMEM;
  2177. udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
  2178. sizeof(struct ci13xxx_td),
  2179. 64, CI13XXX_PAGE_SIZE);
  2180. if (udc->td_pool == NULL) {
  2181. dma_pool_destroy(udc->qh_pool);
  2182. udc->qh_pool = NULL;
  2183. return -ENOMEM;
  2184. }
  2185. spin_lock_irqsave(udc->lock, flags);
  2186. info("hw_ep_max = %d", hw_ep_max);
  2187. udc->gadget.dev.driver = NULL;
  2188. retval = 0;
  2189. for (i = 0; i < hw_ep_max/2; i++) {
  2190. for (j = RX; j <= TX; j++) {
  2191. int k = i + j * hw_ep_max/2;
  2192. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2193. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2194. (j == TX) ? "in" : "out");
  2195. mEp->lock = udc->lock;
  2196. mEp->device = &udc->gadget.dev;
  2197. mEp->td_pool = udc->td_pool;
  2198. mEp->ep.name = mEp->name;
  2199. mEp->ep.ops = &usb_ep_ops;
  2200. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2201. INIT_LIST_HEAD(&mEp->qh.queue);
  2202. spin_unlock_irqrestore(udc->lock, flags);
  2203. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2204. &mEp->qh.dma);
  2205. spin_lock_irqsave(udc->lock, flags);
  2206. if (mEp->qh.ptr == NULL)
  2207. retval = -ENOMEM;
  2208. else
  2209. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2210. /* skip ep0 out and in endpoints */
  2211. if (i == 0)
  2212. continue;
  2213. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2214. }
  2215. }
  2216. if (retval)
  2217. goto done;
  2218. udc->gadget.ep0 = &udc->ep0in.ep;
  2219. /* bind gadget */
  2220. driver->driver.bus = NULL;
  2221. udc->gadget.dev.driver = &driver->driver;
  2222. spin_unlock_irqrestore(udc->lock, flags);
  2223. retval = bind(&udc->gadget); /* MAY SLEEP */
  2224. spin_lock_irqsave(udc->lock, flags);
  2225. if (retval) {
  2226. udc->gadget.dev.driver = NULL;
  2227. goto done;
  2228. }
  2229. udc->driver = driver;
  2230. pm_runtime_get_sync(&udc->gadget.dev);
  2231. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2232. if (udc->vbus_active) {
  2233. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2234. hw_device_reset(udc);
  2235. } else {
  2236. pm_runtime_put_sync(&udc->gadget.dev);
  2237. goto done;
  2238. }
  2239. }
  2240. retval = hw_device_state(udc->ep0out.qh.dma);
  2241. if (retval)
  2242. pm_runtime_put_sync(&udc->gadget.dev);
  2243. done:
  2244. spin_unlock_irqrestore(udc->lock, flags);
  2245. return retval;
  2246. }
  2247. EXPORT_SYMBOL(usb_gadget_probe_driver);
  2248. /**
  2249. * usb_gadget_unregister_driver: unregister a gadget driver
  2250. *
  2251. * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
  2252. */
  2253. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  2254. {
  2255. struct ci13xxx *udc = _udc;
  2256. unsigned long i, flags;
  2257. trace("%p", driver);
  2258. if (driver == NULL ||
  2259. driver->unbind == NULL ||
  2260. driver->setup == NULL ||
  2261. driver->disconnect == NULL ||
  2262. driver->suspend == NULL ||
  2263. driver->resume == NULL ||
  2264. driver != udc->driver)
  2265. return -EINVAL;
  2266. spin_lock_irqsave(udc->lock, flags);
  2267. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2268. udc->vbus_active) {
  2269. hw_device_state(0);
  2270. if (udc->udc_driver->notify_event)
  2271. udc->udc_driver->notify_event(udc,
  2272. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2273. _gadget_stop_activity(&udc->gadget);
  2274. pm_runtime_put(&udc->gadget.dev);
  2275. }
  2276. /* unbind gadget */
  2277. spin_unlock_irqrestore(udc->lock, flags);
  2278. driver->unbind(&udc->gadget); /* MAY SLEEP */
  2279. spin_lock_irqsave(udc->lock, flags);
  2280. udc->gadget.dev.driver = NULL;
  2281. /* free resources */
  2282. for (i = 0; i < hw_ep_max; i++) {
  2283. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2284. if (!list_empty(&mEp->ep.ep_list))
  2285. list_del_init(&mEp->ep.ep_list);
  2286. if (mEp->qh.ptr != NULL)
  2287. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2288. }
  2289. udc->gadget.ep0 = NULL;
  2290. udc->driver = NULL;
  2291. spin_unlock_irqrestore(udc->lock, flags);
  2292. if (udc->td_pool != NULL) {
  2293. dma_pool_destroy(udc->td_pool);
  2294. udc->td_pool = NULL;
  2295. }
  2296. if (udc->qh_pool != NULL) {
  2297. dma_pool_destroy(udc->qh_pool);
  2298. udc->qh_pool = NULL;
  2299. }
  2300. return 0;
  2301. }
  2302. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  2303. /******************************************************************************
  2304. * BUS block
  2305. *****************************************************************************/
  2306. /**
  2307. * udc_irq: global interrupt handler
  2308. *
  2309. * This function returns IRQ_HANDLED if the IRQ has been handled
  2310. * It locks access to registers
  2311. */
  2312. static irqreturn_t udc_irq(void)
  2313. {
  2314. struct ci13xxx *udc = _udc;
  2315. irqreturn_t retval;
  2316. u32 intr;
  2317. trace();
  2318. if (udc == NULL) {
  2319. err("ENODEV");
  2320. return IRQ_HANDLED;
  2321. }
  2322. spin_lock(udc->lock);
  2323. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2324. if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
  2325. USBMODE_CM_DEVICE) {
  2326. spin_unlock(udc->lock);
  2327. return IRQ_NONE;
  2328. }
  2329. }
  2330. intr = hw_test_and_clear_intr_active();
  2331. if (intr) {
  2332. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2333. isr_statistics.hndl.idx &= ISR_MASK;
  2334. isr_statistics.hndl.cnt++;
  2335. /* order defines priority - do NOT change it */
  2336. if (USBi_URI & intr) {
  2337. isr_statistics.uri++;
  2338. isr_reset_handler(udc);
  2339. }
  2340. if (USBi_PCI & intr) {
  2341. isr_statistics.pci++;
  2342. udc->gadget.speed = hw_port_is_high_speed() ?
  2343. USB_SPEED_HIGH : USB_SPEED_FULL;
  2344. if (udc->suspended) {
  2345. spin_unlock(udc->lock);
  2346. udc->driver->resume(&udc->gadget);
  2347. spin_lock(udc->lock);
  2348. udc->suspended = 0;
  2349. }
  2350. }
  2351. if (USBi_UEI & intr)
  2352. isr_statistics.uei++;
  2353. if (USBi_UI & intr) {
  2354. isr_statistics.ui++;
  2355. isr_tr_complete_handler(udc);
  2356. }
  2357. if (USBi_SLI & intr) {
  2358. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  2359. udc->suspended = 1;
  2360. spin_unlock(udc->lock);
  2361. udc->driver->suspend(&udc->gadget);
  2362. spin_lock(udc->lock);
  2363. }
  2364. isr_statistics.sli++;
  2365. }
  2366. retval = IRQ_HANDLED;
  2367. } else {
  2368. isr_statistics.none++;
  2369. retval = IRQ_NONE;
  2370. }
  2371. spin_unlock(udc->lock);
  2372. return retval;
  2373. }
  2374. /**
  2375. * udc_release: driver release function
  2376. * @dev: device
  2377. *
  2378. * Currently does nothing
  2379. */
  2380. static void udc_release(struct device *dev)
  2381. {
  2382. trace("%p", dev);
  2383. if (dev == NULL)
  2384. err("EINVAL");
  2385. }
  2386. /**
  2387. * udc_probe: parent probe must call this to initialize UDC
  2388. * @dev: parent device
  2389. * @regs: registers base address
  2390. * @name: driver name
  2391. *
  2392. * This function returns an error code
  2393. * No interrupts active, the IRQ has not been requested yet
  2394. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2395. */
  2396. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2397. void __iomem *regs)
  2398. {
  2399. struct ci13xxx *udc;
  2400. int retval = 0;
  2401. trace("%p, %p, %p", dev, regs, name);
  2402. if (dev == NULL || regs == NULL || driver == NULL ||
  2403. driver->name == NULL)
  2404. return -EINVAL;
  2405. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2406. if (udc == NULL)
  2407. return -ENOMEM;
  2408. udc->lock = &udc_lock;
  2409. udc->regs = regs;
  2410. udc->udc_driver = driver;
  2411. udc->gadget.ops = &usb_gadget_ops;
  2412. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2413. udc->gadget.is_dualspeed = 1;
  2414. udc->gadget.is_otg = 0;
  2415. udc->gadget.name = driver->name;
  2416. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2417. udc->gadget.ep0 = NULL;
  2418. dev_set_name(&udc->gadget.dev, "gadget");
  2419. udc->gadget.dev.dma_mask = dev->dma_mask;
  2420. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2421. udc->gadget.dev.parent = dev;
  2422. udc->gadget.dev.release = udc_release;
  2423. retval = hw_device_init(regs);
  2424. if (retval < 0)
  2425. goto free_udc;
  2426. udc->transceiver = otg_get_transceiver();
  2427. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2428. if (udc->transceiver == NULL) {
  2429. retval = -ENODEV;
  2430. goto free_udc;
  2431. }
  2432. }
  2433. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2434. retval = hw_device_reset(udc);
  2435. if (retval)
  2436. goto put_transceiver;
  2437. }
  2438. retval = device_register(&udc->gadget.dev);
  2439. if (retval) {
  2440. put_device(&udc->gadget.dev);
  2441. goto put_transceiver;
  2442. }
  2443. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2444. retval = dbg_create_files(&udc->gadget.dev);
  2445. #endif
  2446. if (retval)
  2447. goto unreg_device;
  2448. if (udc->transceiver) {
  2449. retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
  2450. if (retval)
  2451. goto remove_dbg;
  2452. }
  2453. pm_runtime_no_callbacks(&udc->gadget.dev);
  2454. pm_runtime_enable(&udc->gadget.dev);
  2455. _udc = udc;
  2456. return retval;
  2457. err("error = %i", retval);
  2458. remove_dbg:
  2459. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2460. dbg_remove_files(&udc->gadget.dev);
  2461. #endif
  2462. unreg_device:
  2463. device_unregister(&udc->gadget.dev);
  2464. put_transceiver:
  2465. if (udc->transceiver)
  2466. otg_put_transceiver(udc->transceiver);
  2467. free_udc:
  2468. kfree(udc);
  2469. _udc = NULL;
  2470. return retval;
  2471. }
  2472. /**
  2473. * udc_remove: parent remove must call this to remove UDC
  2474. *
  2475. * No interrupts active, the IRQ has been released
  2476. */
  2477. static void udc_remove(void)
  2478. {
  2479. struct ci13xxx *udc = _udc;
  2480. if (udc == NULL) {
  2481. err("EINVAL");
  2482. return;
  2483. }
  2484. if (udc->transceiver) {
  2485. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2486. otg_put_transceiver(udc->transceiver);
  2487. }
  2488. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2489. dbg_remove_files(&udc->gadget.dev);
  2490. #endif
  2491. device_unregister(&udc->gadget.dev);
  2492. kfree(udc);
  2493. _udc = NULL;
  2494. }