bfin_sport_uart.c 23 KB

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  1. /*
  2. * Blackfin On-Chip Sport Emulated UART Driver
  3. *
  4. * Copyright 2006-2009 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. /*
  11. * This driver and the hardware supported are in term of EE-191 of ADI.
  12. * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
  13. * This application note describe how to implement a UART on a Sharc DSP,
  14. * but this driver is implemented on Blackfin Processor.
  15. * Transmit Frame Sync is not used by this driver to transfer data out.
  16. */
  17. /* #define DEBUG */
  18. #define DRV_NAME "bfin-sport-uart"
  19. #define DEVICE_NAME "ttySS"
  20. #define pr_fmt(fmt) DRV_NAME ": " fmt
  21. #include <linux/module.h>
  22. #include <linux/ioport.h>
  23. #include <linux/io.h>
  24. #include <linux/init.h>
  25. #include <linux/console.h>
  26. #include <linux/sysrq.h>
  27. #include <linux/slab.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/tty.h>
  30. #include <linux/tty_flip.h>
  31. #include <linux/serial_core.h>
  32. #include <asm/bfin_sport.h>
  33. #include <asm/delay.h>
  34. #include <asm/portmux.h>
  35. #include "bfin_sport_uart.h"
  36. struct sport_uart_port {
  37. struct uart_port port;
  38. int err_irq;
  39. unsigned short csize;
  40. unsigned short rxmask;
  41. unsigned short txmask1;
  42. unsigned short txmask2;
  43. unsigned char stopb;
  44. /* unsigned char parib; */
  45. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  46. int cts_pin;
  47. int rts_pin;
  48. #endif
  49. };
  50. static int sport_uart_tx_chars(struct sport_uart_port *up);
  51. static void sport_stop_tx(struct uart_port *port);
  52. static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
  53. {
  54. pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
  55. up->txmask1, up->txmask2);
  56. /* Place Start and Stop bits */
  57. __asm__ __volatile__ (
  58. "%[val] <<= 1;"
  59. "%[val] = %[val] & %[mask1];"
  60. "%[val] = %[val] | %[mask2];"
  61. : [val]"+d"(value)
  62. : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
  63. : "ASTAT"
  64. );
  65. pr_debug("%s value:%x\n", __func__, value);
  66. SPORT_PUT_TX(up, value);
  67. }
  68. static inline unsigned char rx_one_byte(struct sport_uart_port *up)
  69. {
  70. unsigned int value;
  71. unsigned char extract;
  72. u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
  73. if ((up->csize + up->stopb) > 7)
  74. value = SPORT_GET_RX32(up);
  75. else
  76. value = SPORT_GET_RX(up);
  77. pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
  78. up->csize, up->rxmask);
  79. /* Extract data */
  80. __asm__ __volatile__ (
  81. "%[extr] = 0;"
  82. "%[mask1] = %[rxmask];"
  83. "%[mask2] = 0x0200(Z);"
  84. "%[shift] = 0;"
  85. "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
  86. ".Lloop_s:"
  87. "%[tmp] = extract(%[val], %[mask1].L)(Z);"
  88. "%[tmp] <<= %[shift];"
  89. "%[extr] = %[extr] | %[tmp];"
  90. "%[mask1] = %[mask1] - %[mask2];"
  91. ".Lloop_e:"
  92. "%[shift] += 1;"
  93. : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
  94. [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
  95. : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
  96. : "ASTAT", "LB0", "LC0", "LT0"
  97. );
  98. pr_debug(" extract:%x\n", extract);
  99. return extract;
  100. }
  101. static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
  102. {
  103. int tclkdiv, rclkdiv;
  104. unsigned int sclk = get_sclk();
  105. /* Set TCR1 and TCR2, TFSR is not enabled for uart */
  106. SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
  107. SPORT_PUT_TCR2(up, size + 1);
  108. pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
  109. /* Set RCR1 and RCR2 */
  110. SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
  111. SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
  112. pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
  113. tclkdiv = sclk / (2 * baud_rate) - 1;
  114. /* The actual uart baud rate of devices vary between +/-2%. The sport
  115. * RX sample rate should be faster than the double of the worst case,
  116. * otherwise, wrong data are received. So, set sport RX clock to be
  117. * 3% faster.
  118. */
  119. rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
  120. SPORT_PUT_TCLKDIV(up, tclkdiv);
  121. SPORT_PUT_RCLKDIV(up, rclkdiv);
  122. SSYNC();
  123. pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
  124. __func__, sclk, baud_rate, tclkdiv, rclkdiv);
  125. return 0;
  126. }
  127. static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
  128. {
  129. struct sport_uart_port *up = dev_id;
  130. struct tty_struct *tty = up->port.state->port.tty;
  131. unsigned int ch;
  132. spin_lock(&up->port.lock);
  133. while (SPORT_GET_STAT(up) & RXNE) {
  134. ch = rx_one_byte(up);
  135. up->port.icount.rx++;
  136. if (!uart_handle_sysrq_char(&up->port, ch))
  137. tty_insert_flip_char(tty, ch, TTY_NORMAL);
  138. }
  139. tty_flip_buffer_push(tty);
  140. spin_unlock(&up->port.lock);
  141. return IRQ_HANDLED;
  142. }
  143. static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
  144. {
  145. struct sport_uart_port *up = dev_id;
  146. spin_lock(&up->port.lock);
  147. sport_uart_tx_chars(up);
  148. spin_unlock(&up->port.lock);
  149. return IRQ_HANDLED;
  150. }
  151. static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
  152. {
  153. struct sport_uart_port *up = dev_id;
  154. struct tty_struct *tty = up->port.state->port.tty;
  155. unsigned int stat = SPORT_GET_STAT(up);
  156. spin_lock(&up->port.lock);
  157. /* Overflow in RX FIFO */
  158. if (stat & ROVF) {
  159. up->port.icount.overrun++;
  160. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  161. SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
  162. }
  163. /* These should not happen */
  164. if (stat & (TOVF | TUVF | RUVF)) {
  165. pr_err("SPORT Error:%s %s %s\n",
  166. (stat & TOVF) ? "TX overflow" : "",
  167. (stat & TUVF) ? "TX underflow" : "",
  168. (stat & RUVF) ? "RX underflow" : "");
  169. SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
  170. SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
  171. }
  172. SSYNC();
  173. spin_unlock(&up->port.lock);
  174. return IRQ_HANDLED;
  175. }
  176. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  177. static unsigned int sport_get_mctrl(struct uart_port *port)
  178. {
  179. struct sport_uart_port *up = (struct sport_uart_port *)port;
  180. if (up->cts_pin < 0)
  181. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  182. /* CTS PIN is negative assertive. */
  183. if (SPORT_UART_GET_CTS(up))
  184. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  185. else
  186. return TIOCM_DSR | TIOCM_CAR;
  187. }
  188. static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
  189. {
  190. struct sport_uart_port *up = (struct sport_uart_port *)port;
  191. if (up->rts_pin < 0)
  192. return;
  193. /* RTS PIN is negative assertive. */
  194. if (mctrl & TIOCM_RTS)
  195. SPORT_UART_ENABLE_RTS(up);
  196. else
  197. SPORT_UART_DISABLE_RTS(up);
  198. }
  199. /*
  200. * Handle any change of modem status signal.
  201. */
  202. static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
  203. {
  204. struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
  205. unsigned int status;
  206. status = sport_get_mctrl(&up->port);
  207. uart_handle_cts_change(&up->port, status & TIOCM_CTS);
  208. return IRQ_HANDLED;
  209. }
  210. #else
  211. static unsigned int sport_get_mctrl(struct uart_port *port)
  212. {
  213. pr_debug("%s enter\n", __func__);
  214. return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
  215. }
  216. static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
  217. {
  218. pr_debug("%s enter\n", __func__);
  219. }
  220. #endif
  221. /* Reqeust IRQ, Setup clock */
  222. static int sport_startup(struct uart_port *port)
  223. {
  224. struct sport_uart_port *up = (struct sport_uart_port *)port;
  225. int ret;
  226. pr_debug("%s enter\n", __func__);
  227. ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
  228. "SPORT_UART_RX", up);
  229. if (ret) {
  230. dev_err(port->dev, "unable to request SPORT RX interrupt\n");
  231. return ret;
  232. }
  233. ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
  234. "SPORT_UART_TX", up);
  235. if (ret) {
  236. dev_err(port->dev, "unable to request SPORT TX interrupt\n");
  237. goto fail1;
  238. }
  239. ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
  240. "SPORT_UART_STATUS", up);
  241. if (ret) {
  242. dev_err(port->dev, "unable to request SPORT status interrupt\n");
  243. goto fail2;
  244. }
  245. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  246. if (up->cts_pin >= 0) {
  247. if (request_irq(gpio_to_irq(up->cts_pin),
  248. sport_mctrl_cts_int,
  249. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
  250. IRQF_DISABLED, "BFIN_SPORT_UART_CTS", up)) {
  251. up->cts_pin = -1;
  252. dev_info(port->dev, "Unable to attach BlackFin UART \
  253. over SPORT CTS interrupt. So, disable it.\n");
  254. }
  255. }
  256. if (up->rts_pin >= 0)
  257. gpio_direction_output(up->rts_pin, 0);
  258. #endif
  259. return 0;
  260. fail2:
  261. free_irq(up->port.irq+1, up);
  262. fail1:
  263. free_irq(up->port.irq, up);
  264. return ret;
  265. }
  266. /*
  267. * sport_uart_tx_chars
  268. *
  269. * ret 1 means need to enable sport.
  270. * ret 0 means do nothing.
  271. */
  272. static int sport_uart_tx_chars(struct sport_uart_port *up)
  273. {
  274. struct circ_buf *xmit = &up->port.state->xmit;
  275. if (SPORT_GET_STAT(up) & TXF)
  276. return 0;
  277. if (up->port.x_char) {
  278. tx_one_byte(up, up->port.x_char);
  279. up->port.icount.tx++;
  280. up->port.x_char = 0;
  281. return 1;
  282. }
  283. if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
  284. /* The waiting loop to stop SPORT TX from TX interrupt is
  285. * too long. This may block SPORT RX interrupts and cause
  286. * RX FIFO overflow. So, do stop sport TX only after the last
  287. * char in TX FIFO is moved into the shift register.
  288. */
  289. if (SPORT_GET_STAT(up) & TXHRE)
  290. sport_stop_tx(&up->port);
  291. return 0;
  292. }
  293. while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
  294. tx_one_byte(up, xmit->buf[xmit->tail]);
  295. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
  296. up->port.icount.tx++;
  297. }
  298. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  299. uart_write_wakeup(&up->port);
  300. return 1;
  301. }
  302. static unsigned int sport_tx_empty(struct uart_port *port)
  303. {
  304. struct sport_uart_port *up = (struct sport_uart_port *)port;
  305. unsigned int stat;
  306. stat = SPORT_GET_STAT(up);
  307. pr_debug("%s stat:%04x\n", __func__, stat);
  308. if (stat & TXHRE) {
  309. return TIOCSER_TEMT;
  310. } else
  311. return 0;
  312. }
  313. static void sport_stop_tx(struct uart_port *port)
  314. {
  315. struct sport_uart_port *up = (struct sport_uart_port *)port;
  316. pr_debug("%s enter\n", __func__);
  317. if (!(SPORT_GET_TCR1(up) & TSPEN))
  318. return;
  319. /* Although the hold register is empty, last byte is still in shift
  320. * register and not sent out yet. So, put a dummy data into TX FIFO.
  321. * Then, sport tx stops when last byte is shift out and the dummy
  322. * data is moved into the shift register.
  323. */
  324. SPORT_PUT_TX(up, 0xffff);
  325. while (!(SPORT_GET_STAT(up) & TXHRE))
  326. cpu_relax();
  327. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
  328. SSYNC();
  329. return;
  330. }
  331. static void sport_start_tx(struct uart_port *port)
  332. {
  333. struct sport_uart_port *up = (struct sport_uart_port *)port;
  334. pr_debug("%s enter\n", __func__);
  335. /* Write data into SPORT FIFO before enable SPROT to transmit */
  336. if (sport_uart_tx_chars(up)) {
  337. /* Enable transmit, then an interrupt will generated */
  338. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
  339. SSYNC();
  340. }
  341. pr_debug("%s exit\n", __func__);
  342. }
  343. static void sport_stop_rx(struct uart_port *port)
  344. {
  345. struct sport_uart_port *up = (struct sport_uart_port *)port;
  346. pr_debug("%s enter\n", __func__);
  347. /* Disable sport to stop rx */
  348. SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
  349. SSYNC();
  350. }
  351. static void sport_enable_ms(struct uart_port *port)
  352. {
  353. pr_debug("%s enter\n", __func__);
  354. }
  355. static void sport_break_ctl(struct uart_port *port, int break_state)
  356. {
  357. pr_debug("%s enter\n", __func__);
  358. }
  359. static void sport_shutdown(struct uart_port *port)
  360. {
  361. struct sport_uart_port *up = (struct sport_uart_port *)port;
  362. dev_dbg(port->dev, "%s enter\n", __func__);
  363. /* Disable sport */
  364. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
  365. SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
  366. SSYNC();
  367. free_irq(up->port.irq, up);
  368. free_irq(up->port.irq+1, up);
  369. free_irq(up->err_irq, up);
  370. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  371. if (up->cts_pin >= 0)
  372. free_irq(gpio_to_irq(up->cts_pin), up);
  373. #endif
  374. }
  375. static const char *sport_type(struct uart_port *port)
  376. {
  377. struct sport_uart_port *up = (struct sport_uart_port *)port;
  378. pr_debug("%s enter\n", __func__);
  379. return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
  380. }
  381. static void sport_release_port(struct uart_port *port)
  382. {
  383. pr_debug("%s enter\n", __func__);
  384. }
  385. static int sport_request_port(struct uart_port *port)
  386. {
  387. pr_debug("%s enter\n", __func__);
  388. return 0;
  389. }
  390. static void sport_config_port(struct uart_port *port, int flags)
  391. {
  392. struct sport_uart_port *up = (struct sport_uart_port *)port;
  393. pr_debug("%s enter\n", __func__);
  394. up->port.type = PORT_BFIN_SPORT;
  395. }
  396. static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
  397. {
  398. pr_debug("%s enter\n", __func__);
  399. return 0;
  400. }
  401. static void sport_set_termios(struct uart_port *port,
  402. struct ktermios *termios, struct ktermios *old)
  403. {
  404. struct sport_uart_port *up = (struct sport_uart_port *)port;
  405. unsigned long flags;
  406. int i;
  407. pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
  408. switch (termios->c_cflag & CSIZE) {
  409. case CS8:
  410. up->csize = 8;
  411. break;
  412. case CS7:
  413. up->csize = 7;
  414. break;
  415. case CS6:
  416. up->csize = 6;
  417. break;
  418. case CS5:
  419. up->csize = 5;
  420. break;
  421. default:
  422. pr_warning("requested word length not supported\n");
  423. }
  424. if (termios->c_cflag & CSTOPB) {
  425. up->stopb = 1;
  426. }
  427. if (termios->c_cflag & PARENB) {
  428. pr_warning("PAREN bits is not supported yet\n");
  429. /* up->parib = 1; */
  430. }
  431. spin_lock_irqsave(&up->port.lock, flags);
  432. port->read_status_mask = 0;
  433. /*
  434. * Characters to ignore
  435. */
  436. port->ignore_status_mask = 0;
  437. /* RX extract mask */
  438. up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
  439. /* TX masks, 8 bit data and 1 bit stop for example:
  440. * mask1 = b#0111111110
  441. * mask2 = b#1000000000
  442. */
  443. for (i = 0, up->txmask1 = 0; i < up->csize; i++)
  444. up->txmask1 |= (1<<i);
  445. up->txmask2 = (1<<i);
  446. if (up->stopb) {
  447. ++i;
  448. up->txmask2 |= (1<<i);
  449. }
  450. up->txmask1 <<= 1;
  451. up->txmask2 <<= 1;
  452. /* uart baud rate */
  453. port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
  454. /* Disable UART */
  455. SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
  456. SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
  457. sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
  458. /* driver TX line high after config, one dummy data is
  459. * necessary to stop sport after shift one byte
  460. */
  461. SPORT_PUT_TX(up, 0xffff);
  462. SPORT_PUT_TX(up, 0xffff);
  463. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
  464. SSYNC();
  465. while (!(SPORT_GET_STAT(up) & TXHRE))
  466. cpu_relax();
  467. SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
  468. SSYNC();
  469. /* Port speed changed, update the per-port timeout. */
  470. uart_update_timeout(port, termios->c_cflag, port->uartclk);
  471. /* Enable sport rx */
  472. SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
  473. SSYNC();
  474. spin_unlock_irqrestore(&up->port.lock, flags);
  475. }
  476. struct uart_ops sport_uart_ops = {
  477. .tx_empty = sport_tx_empty,
  478. .set_mctrl = sport_set_mctrl,
  479. .get_mctrl = sport_get_mctrl,
  480. .stop_tx = sport_stop_tx,
  481. .start_tx = sport_start_tx,
  482. .stop_rx = sport_stop_rx,
  483. .enable_ms = sport_enable_ms,
  484. .break_ctl = sport_break_ctl,
  485. .startup = sport_startup,
  486. .shutdown = sport_shutdown,
  487. .set_termios = sport_set_termios,
  488. .type = sport_type,
  489. .release_port = sport_release_port,
  490. .request_port = sport_request_port,
  491. .config_port = sport_config_port,
  492. .verify_port = sport_verify_port,
  493. };
  494. #define BFIN_SPORT_UART_MAX_PORTS 4
  495. static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
  496. #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
  497. #define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
  498. static int __init
  499. sport_uart_console_setup(struct console *co, char *options)
  500. {
  501. struct sport_uart_port *up;
  502. int baud = 57600;
  503. int bits = 8;
  504. int parity = 'n';
  505. # ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  506. int flow = 'r';
  507. # else
  508. int flow = 'n';
  509. # endif
  510. /* Check whether an invalid uart number has been specified */
  511. if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
  512. return -ENODEV;
  513. up = bfin_sport_uart_ports[co->index];
  514. if (!up)
  515. return -ENODEV;
  516. if (options)
  517. uart_parse_options(options, &baud, &parity, &bits, &flow);
  518. return uart_set_options(&up->port, co, baud, parity, bits, flow);
  519. }
  520. static void sport_uart_console_putchar(struct uart_port *port, int ch)
  521. {
  522. struct sport_uart_port *up = (struct sport_uart_port *)port;
  523. while (SPORT_GET_STAT(up) & TXF)
  524. barrier();
  525. tx_one_byte(up, ch);
  526. }
  527. /*
  528. * Interrupts are disabled on entering
  529. */
  530. static void
  531. sport_uart_console_write(struct console *co, const char *s, unsigned int count)
  532. {
  533. struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
  534. unsigned long flags;
  535. spin_lock_irqsave(&up->port.lock, flags);
  536. if (SPORT_GET_TCR1(up) & TSPEN)
  537. uart_console_write(&up->port, s, count, sport_uart_console_putchar);
  538. else {
  539. /* dummy data to start sport */
  540. while (SPORT_GET_STAT(up) & TXF)
  541. barrier();
  542. SPORT_PUT_TX(up, 0xffff);
  543. /* Enable transmit, then an interrupt will generated */
  544. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
  545. SSYNC();
  546. uart_console_write(&up->port, s, count, sport_uart_console_putchar);
  547. /* Although the hold register is empty, last byte is still in shift
  548. * register and not sent out yet. So, put a dummy data into TX FIFO.
  549. * Then, sport tx stops when last byte is shift out and the dummy
  550. * data is moved into the shift register.
  551. */
  552. while (SPORT_GET_STAT(up) & TXF)
  553. barrier();
  554. SPORT_PUT_TX(up, 0xffff);
  555. while (!(SPORT_GET_STAT(up) & TXHRE))
  556. barrier();
  557. /* Stop sport tx transfer */
  558. SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
  559. SSYNC();
  560. }
  561. spin_unlock_irqrestore(&up->port.lock, flags);
  562. }
  563. static struct uart_driver sport_uart_reg;
  564. static struct console sport_uart_console = {
  565. .name = DEVICE_NAME,
  566. .write = sport_uart_console_write,
  567. .device = uart_console_device,
  568. .setup = sport_uart_console_setup,
  569. .flags = CON_PRINTBUFFER,
  570. .index = -1,
  571. .data = &sport_uart_reg,
  572. };
  573. #define SPORT_UART_CONSOLE (&sport_uart_console)
  574. #else
  575. #define SPORT_UART_CONSOLE NULL
  576. #endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
  577. static struct uart_driver sport_uart_reg = {
  578. .owner = THIS_MODULE,
  579. .driver_name = DRV_NAME,
  580. .dev_name = DEVICE_NAME,
  581. .major = 204,
  582. .minor = 84,
  583. .nr = BFIN_SPORT_UART_MAX_PORTS,
  584. .cons = SPORT_UART_CONSOLE,
  585. };
  586. #ifdef CONFIG_PM
  587. static int sport_uart_suspend(struct device *dev)
  588. {
  589. struct sport_uart_port *sport = dev_get_drvdata(dev);
  590. dev_dbg(dev, "%s enter\n", __func__);
  591. if (sport)
  592. uart_suspend_port(&sport_uart_reg, &sport->port);
  593. return 0;
  594. }
  595. static int sport_uart_resume(struct device *dev)
  596. {
  597. struct sport_uart_port *sport = dev_get_drvdata(dev);
  598. dev_dbg(dev, "%s enter\n", __func__);
  599. if (sport)
  600. uart_resume_port(&sport_uart_reg, &sport->port);
  601. return 0;
  602. }
  603. static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
  604. .suspend = sport_uart_suspend,
  605. .resume = sport_uart_resume,
  606. };
  607. #endif
  608. static int __devinit sport_uart_probe(struct platform_device *pdev)
  609. {
  610. struct resource *res;
  611. struct sport_uart_port *sport;
  612. int ret = 0;
  613. dev_dbg(&pdev->dev, "%s enter\n", __func__);
  614. if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
  615. dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
  616. return -ENOENT;
  617. }
  618. if (bfin_sport_uart_ports[pdev->id] == NULL) {
  619. bfin_sport_uart_ports[pdev->id] =
  620. kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
  621. sport = bfin_sport_uart_ports[pdev->id];
  622. if (!sport) {
  623. dev_err(&pdev->dev,
  624. "Fail to malloc sport_uart_port\n");
  625. return -ENOMEM;
  626. }
  627. ret = peripheral_request_list(
  628. (unsigned short *)pdev->dev.platform_data, DRV_NAME);
  629. if (ret) {
  630. dev_err(&pdev->dev,
  631. "Fail to request SPORT peripherals\n");
  632. goto out_error_free_mem;
  633. }
  634. spin_lock_init(&sport->port.lock);
  635. sport->port.fifosize = SPORT_TX_FIFO_SIZE,
  636. sport->port.ops = &sport_uart_ops;
  637. sport->port.line = pdev->id;
  638. sport->port.iotype = UPIO_MEM;
  639. sport->port.flags = UPF_BOOT_AUTOCONF;
  640. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  641. if (res == NULL) {
  642. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  643. ret = -ENOENT;
  644. goto out_error_free_peripherals;
  645. }
  646. sport->port.membase = ioremap(res->start, resource_size(res));
  647. if (!sport->port.membase) {
  648. dev_err(&pdev->dev, "Cannot map sport IO\n");
  649. ret = -ENXIO;
  650. goto out_error_free_peripherals;
  651. }
  652. sport->port.mapbase = res->start;
  653. sport->port.irq = platform_get_irq(pdev, 0);
  654. if ((int)sport->port.irq < 0) {
  655. dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
  656. ret = -ENOENT;
  657. goto out_error_unmap;
  658. }
  659. sport->err_irq = platform_get_irq(pdev, 1);
  660. if (sport->err_irq < 0) {
  661. dev_err(&pdev->dev, "No sport status IRQ specified\n");
  662. ret = -ENOENT;
  663. goto out_error_unmap;
  664. }
  665. #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
  666. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  667. if (res == NULL)
  668. sport->cts_pin = -1;
  669. else
  670. sport->cts_pin = res->start;
  671. res = platform_get_resource(pdev, IORESOURCE_IO, 1);
  672. if (res == NULL)
  673. sport->rts_pin = -1;
  674. else
  675. sport->rts_pin = res->start;
  676. if (sport->rts_pin >= 0)
  677. gpio_request(sport->rts_pin, DRV_NAME);
  678. #endif
  679. }
  680. #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
  681. if (!is_early_platform_device(pdev)) {
  682. #endif
  683. sport = bfin_sport_uart_ports[pdev->id];
  684. sport->port.dev = &pdev->dev;
  685. dev_set_drvdata(&pdev->dev, sport);
  686. ret = uart_add_one_port(&sport_uart_reg, &sport->port);
  687. #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
  688. }
  689. #endif
  690. if (!ret)
  691. return 0;
  692. if (sport) {
  693. out_error_unmap:
  694. iounmap(sport->port.membase);
  695. out_error_free_peripherals:
  696. peripheral_free_list(
  697. (unsigned short *)pdev->dev.platform_data);
  698. out_error_free_mem:
  699. kfree(sport);
  700. bfin_sport_uart_ports[pdev->id] = NULL;
  701. }
  702. return ret;
  703. }
  704. static int __devexit sport_uart_remove(struct platform_device *pdev)
  705. {
  706. struct sport_uart_port *sport = platform_get_drvdata(pdev);
  707. dev_dbg(&pdev->dev, "%s enter\n", __func__);
  708. dev_set_drvdata(&pdev->dev, NULL);
  709. if (sport) {
  710. uart_remove_one_port(&sport_uart_reg, &sport->port);
  711. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  712. if (sport->rts_pin >= 0)
  713. gpio_free(sport->rts_pin);
  714. #endif
  715. iounmap(sport->port.membase);
  716. peripheral_free_list(
  717. (unsigned short *)pdev->dev.platform_data);
  718. kfree(sport);
  719. bfin_sport_uart_ports[pdev->id] = NULL;
  720. }
  721. return 0;
  722. }
  723. static struct platform_driver sport_uart_driver = {
  724. .probe = sport_uart_probe,
  725. .remove = __devexit_p(sport_uart_remove),
  726. .driver = {
  727. .name = DRV_NAME,
  728. #ifdef CONFIG_PM
  729. .pm = &bfin_sport_uart_dev_pm_ops,
  730. #endif
  731. },
  732. };
  733. #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
  734. static __initdata struct early_platform_driver early_sport_uart_driver = {
  735. .class_str = CLASS_BFIN_SPORT_CONSOLE,
  736. .pdrv = &sport_uart_driver,
  737. .requested_id = EARLY_PLATFORM_ID_UNSET,
  738. };
  739. static int __init sport_uart_rs_console_init(void)
  740. {
  741. early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
  742. early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
  743. BFIN_SPORT_UART_MAX_PORTS, 0);
  744. register_console(&sport_uart_console);
  745. return 0;
  746. }
  747. console_initcall(sport_uart_rs_console_init);
  748. #endif
  749. static int __init sport_uart_init(void)
  750. {
  751. int ret;
  752. pr_info("Blackfin uart over sport driver\n");
  753. ret = uart_register_driver(&sport_uart_reg);
  754. if (ret) {
  755. pr_err("failed to register %s:%d\n",
  756. sport_uart_reg.driver_name, ret);
  757. return ret;
  758. }
  759. ret = platform_driver_register(&sport_uart_driver);
  760. if (ret) {
  761. pr_err("failed to register sport uart driver:%d\n", ret);
  762. uart_unregister_driver(&sport_uart_reg);
  763. }
  764. return ret;
  765. }
  766. module_init(sport_uart_init);
  767. static void __exit sport_uart_exit(void)
  768. {
  769. platform_driver_unregister(&sport_uart_driver);
  770. uart_unregister_driver(&sport_uart_reg);
  771. }
  772. module_exit(sport_uart_exit);
  773. MODULE_AUTHOR("Sonic Zhang, Roy Huang");
  774. MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
  775. MODULE_LICENSE("GPL");