qla_os.c 109 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. /*
  20. * Driver version
  21. */
  22. char qla2x00_version_str[40];
  23. static int apidev_major;
  24. /*
  25. * SRB allocation cache
  26. */
  27. static struct kmem_cache *srb_cachep;
  28. /*
  29. * CT6 CTX allocation cache
  30. */
  31. static struct kmem_cache *ctx_cachep;
  32. int ql2xlogintimeout = 20;
  33. module_param(ql2xlogintimeout, int, S_IRUGO);
  34. MODULE_PARM_DESC(ql2xlogintimeout,
  35. "Login timeout value in seconds.");
  36. int qlport_down_retry;
  37. module_param(qlport_down_retry, int, S_IRUGO);
  38. MODULE_PARM_DESC(qlport_down_retry,
  39. "Maximum number of command retries to a port that returns "
  40. "a PORT-DOWN status.");
  41. int ql2xplogiabsentdevice;
  42. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  43. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  44. "Option to enable PLOGI to devices that are not present after "
  45. "a Fabric scan. This is needed for several broken switches. "
  46. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  47. int ql2xloginretrycount = 0;
  48. module_param(ql2xloginretrycount, int, S_IRUGO);
  49. MODULE_PARM_DESC(ql2xloginretrycount,
  50. "Specify an alternate value for the NVRAM login retry count.");
  51. int ql2xallocfwdump = 1;
  52. module_param(ql2xallocfwdump, int, S_IRUGO);
  53. MODULE_PARM_DESC(ql2xallocfwdump,
  54. "Option to enable allocation of memory for a firmware dump "
  55. "during HBA initialization. Memory allocation requirements "
  56. "vary by ISP type. Default is 1 - allocate memory.");
  57. int ql2xextended_error_logging;
  58. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  59. MODULE_PARM_DESC(ql2xextended_error_logging,
  60. "Option to enable extended error logging, "
  61. "Default is 0 - no logging. 1 - log errors.");
  62. int ql2xshiftctondsd = 6;
  63. module_param(ql2xshiftctondsd, int, S_IRUGO);
  64. MODULE_PARM_DESC(ql2xshiftctondsd,
  65. "Set to control shifting of command type processing "
  66. "based on total number of SG elements.");
  67. static void qla2x00_free_device(scsi_qla_host_t *);
  68. int ql2xfdmienable=1;
  69. module_param(ql2xfdmienable, int, S_IRUGO);
  70. MODULE_PARM_DESC(ql2xfdmienable,
  71. "Enables FDMI registrations. "
  72. "0 - no FDMI. Default is 1 - perform FDMI.");
  73. #define MAX_Q_DEPTH 32
  74. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  75. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(ql2xmaxqdepth,
  77. "Maximum queue depth to report for target devices.");
  78. /* Do not change the value of this after module load */
  79. int ql2xenabledif = 1;
  80. module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(ql2xenabledif,
  82. " Enable T10-CRC-DIF "
  83. " Default is 0 - No DIF Support. 1 - Enable it");
  84. int ql2xenablehba_err_chk;
  85. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  86. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  87. " Enable T10-CRC-DIF Error isolation by HBA"
  88. " Default is 0 - Error isolation disabled, 1 - Enable it");
  89. int ql2xiidmaenable=1;
  90. module_param(ql2xiidmaenable, int, S_IRUGO);
  91. MODULE_PARM_DESC(ql2xiidmaenable,
  92. "Enables iIDMA settings "
  93. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  94. int ql2xmaxqueues = 1;
  95. module_param(ql2xmaxqueues, int, S_IRUGO);
  96. MODULE_PARM_DESC(ql2xmaxqueues,
  97. "Enables MQ settings "
  98. "Default is 1 for single queue. Set it to number "
  99. "of queues in MQ mode.");
  100. int ql2xmultique_tag;
  101. module_param(ql2xmultique_tag, int, S_IRUGO);
  102. MODULE_PARM_DESC(ql2xmultique_tag,
  103. "Enables CPU affinity settings for the driver "
  104. "Default is 0 for no affinity of request and response IO. "
  105. "Set it to 1 to turn on the cpu affinity.");
  106. int ql2xfwloadbin;
  107. module_param(ql2xfwloadbin, int, S_IRUGO);
  108. MODULE_PARM_DESC(ql2xfwloadbin,
  109. "Option to specify location from which to load ISP firmware:\n"
  110. " 2 -- load firmware via the request_firmware() (hotplug)\n"
  111. " interface.\n"
  112. " 1 -- load firmware from flash.\n"
  113. " 0 -- use default semantics.\n");
  114. int ql2xetsenable;
  115. module_param(ql2xetsenable, int, S_IRUGO);
  116. MODULE_PARM_DESC(ql2xetsenable,
  117. "Enables firmware ETS burst."
  118. "Default is 0 - skip ETS enablement.");
  119. int ql2xdbwr = 1;
  120. module_param(ql2xdbwr, int, S_IRUGO);
  121. MODULE_PARM_DESC(ql2xdbwr,
  122. "Option to specify scheme for request queue posting\n"
  123. " 0 -- Regular doorbell.\n"
  124. " 1 -- CAMRAM doorbell (faster).\n");
  125. int ql2xtargetreset = 1;
  126. module_param(ql2xtargetreset, int, S_IRUGO);
  127. MODULE_PARM_DESC(ql2xtargetreset,
  128. "Enable target reset."
  129. "Default is 1 - use hw defaults.");
  130. int ql2xgffidenable;
  131. module_param(ql2xgffidenable, int, S_IRUGO);
  132. MODULE_PARM_DESC(ql2xgffidenable,
  133. "Enables GFF_ID checks of port type. "
  134. "Default is 0 - Do not use GFF_ID information.");
  135. int ql2xasynctmfenable;
  136. module_param(ql2xasynctmfenable, int, S_IRUGO);
  137. MODULE_PARM_DESC(ql2xasynctmfenable,
  138. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  139. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  140. /*
  141. * SCSI host template entry points
  142. */
  143. static int qla2xxx_slave_configure(struct scsi_device * device);
  144. static int qla2xxx_slave_alloc(struct scsi_device *);
  145. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  146. static void qla2xxx_scan_start(struct Scsi_Host *);
  147. static void qla2xxx_slave_destroy(struct scsi_device *);
  148. static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  149. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  150. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  151. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  152. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  153. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  154. static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
  155. static int qla2x00_change_queue_type(struct scsi_device *, int);
  156. struct scsi_host_template qla2xxx_driver_template = {
  157. .module = THIS_MODULE,
  158. .name = QLA2XXX_DRIVER_NAME,
  159. .queuecommand = qla2xxx_queuecommand,
  160. .eh_abort_handler = qla2xxx_eh_abort,
  161. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  162. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  163. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  164. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  165. .slave_configure = qla2xxx_slave_configure,
  166. .slave_alloc = qla2xxx_slave_alloc,
  167. .slave_destroy = qla2xxx_slave_destroy,
  168. .scan_finished = qla2xxx_scan_finished,
  169. .scan_start = qla2xxx_scan_start,
  170. .change_queue_depth = qla2x00_change_queue_depth,
  171. .change_queue_type = qla2x00_change_queue_type,
  172. .this_id = -1,
  173. .cmd_per_lun = 3,
  174. .use_clustering = ENABLE_CLUSTERING,
  175. .sg_tablesize = SG_ALL,
  176. .max_sectors = 0xFFFF,
  177. .shost_attrs = qla2x00_host_attrs,
  178. };
  179. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  180. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  181. /* TODO Convert to inlines
  182. *
  183. * Timer routines
  184. */
  185. __inline__ void
  186. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  187. {
  188. init_timer(&vha->timer);
  189. vha->timer.expires = jiffies + interval * HZ;
  190. vha->timer.data = (unsigned long)vha;
  191. vha->timer.function = (void (*)(unsigned long))func;
  192. add_timer(&vha->timer);
  193. vha->timer_active = 1;
  194. }
  195. static inline void
  196. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  197. {
  198. /* Currently used for 82XX only. */
  199. if (vha->device_flags & DFLG_DEV_FAILED)
  200. return;
  201. mod_timer(&vha->timer, jiffies + interval * HZ);
  202. }
  203. static __inline__ void
  204. qla2x00_stop_timer(scsi_qla_host_t *vha)
  205. {
  206. del_timer_sync(&vha->timer);
  207. vha->timer_active = 0;
  208. }
  209. static int qla2x00_do_dpc(void *data);
  210. static void qla2x00_rst_aen(scsi_qla_host_t *);
  211. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  212. struct req_que **, struct rsp_que **);
  213. static void qla2x00_free_fw_dump(struct qla_hw_data *);
  214. static void qla2x00_mem_free(struct qla_hw_data *);
  215. static void qla2x00_sp_free_dma(srb_t *);
  216. /* -------------------------------------------------------------------------- */
  217. static int qla2x00_alloc_queues(struct qla_hw_data *ha)
  218. {
  219. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  220. GFP_KERNEL);
  221. if (!ha->req_q_map) {
  222. qla_printk(KERN_WARNING, ha,
  223. "Unable to allocate memory for request queue ptrs\n");
  224. goto fail_req_map;
  225. }
  226. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  227. GFP_KERNEL);
  228. if (!ha->rsp_q_map) {
  229. qla_printk(KERN_WARNING, ha,
  230. "Unable to allocate memory for response queue ptrs\n");
  231. goto fail_rsp_map;
  232. }
  233. set_bit(0, ha->rsp_qid_map);
  234. set_bit(0, ha->req_qid_map);
  235. return 1;
  236. fail_rsp_map:
  237. kfree(ha->req_q_map);
  238. ha->req_q_map = NULL;
  239. fail_req_map:
  240. return -ENOMEM;
  241. }
  242. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  243. {
  244. if (req && req->ring)
  245. dma_free_coherent(&ha->pdev->dev,
  246. (req->length + 1) * sizeof(request_t),
  247. req->ring, req->dma);
  248. kfree(req);
  249. req = NULL;
  250. }
  251. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  252. {
  253. if (rsp && rsp->ring)
  254. dma_free_coherent(&ha->pdev->dev,
  255. (rsp->length + 1) * sizeof(response_t),
  256. rsp->ring, rsp->dma);
  257. kfree(rsp);
  258. rsp = NULL;
  259. }
  260. static void qla2x00_free_queues(struct qla_hw_data *ha)
  261. {
  262. struct req_que *req;
  263. struct rsp_que *rsp;
  264. int cnt;
  265. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  266. req = ha->req_q_map[cnt];
  267. qla2x00_free_req_que(ha, req);
  268. }
  269. kfree(ha->req_q_map);
  270. ha->req_q_map = NULL;
  271. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  272. rsp = ha->rsp_q_map[cnt];
  273. qla2x00_free_rsp_que(ha, rsp);
  274. }
  275. kfree(ha->rsp_q_map);
  276. ha->rsp_q_map = NULL;
  277. }
  278. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  279. {
  280. uint16_t options = 0;
  281. int ques, req, ret;
  282. struct qla_hw_data *ha = vha->hw;
  283. if (!(ha->fw_attributes & BIT_6)) {
  284. qla_printk(KERN_INFO, ha,
  285. "Firmware is not multi-queue capable\n");
  286. goto fail;
  287. }
  288. if (ql2xmultique_tag) {
  289. /* create a request queue for IO */
  290. options |= BIT_7;
  291. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  292. QLA_DEFAULT_QUE_QOS);
  293. if (!req) {
  294. qla_printk(KERN_WARNING, ha,
  295. "Can't create request queue\n");
  296. goto fail;
  297. }
  298. ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
  299. vha->req = ha->req_q_map[req];
  300. options |= BIT_1;
  301. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  302. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  303. if (!ret) {
  304. qla_printk(KERN_WARNING, ha,
  305. "Response Queue create failed\n");
  306. goto fail2;
  307. }
  308. }
  309. ha->flags.cpu_affinity_enabled = 1;
  310. DEBUG2(qla_printk(KERN_INFO, ha,
  311. "CPU affinity mode enabled, no. of response"
  312. " queues:%d, no. of request queues:%d\n",
  313. ha->max_rsp_queues, ha->max_req_queues));
  314. }
  315. return 0;
  316. fail2:
  317. qla25xx_delete_queues(vha);
  318. destroy_workqueue(ha->wq);
  319. ha->wq = NULL;
  320. fail:
  321. ha->mqenable = 0;
  322. kfree(ha->req_q_map);
  323. kfree(ha->rsp_q_map);
  324. ha->max_req_queues = ha->max_rsp_queues = 1;
  325. return 1;
  326. }
  327. static char *
  328. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  329. {
  330. struct qla_hw_data *ha = vha->hw;
  331. static char *pci_bus_modes[] = {
  332. "33", "66", "100", "133",
  333. };
  334. uint16_t pci_bus;
  335. strcpy(str, "PCI");
  336. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  337. if (pci_bus) {
  338. strcat(str, "-X (");
  339. strcat(str, pci_bus_modes[pci_bus]);
  340. } else {
  341. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  342. strcat(str, " (");
  343. strcat(str, pci_bus_modes[pci_bus]);
  344. }
  345. strcat(str, " MHz)");
  346. return (str);
  347. }
  348. static char *
  349. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  350. {
  351. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  352. struct qla_hw_data *ha = vha->hw;
  353. uint32_t pci_bus;
  354. int pcie_reg;
  355. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  356. if (pcie_reg) {
  357. char lwstr[6];
  358. uint16_t pcie_lstat, lspeed, lwidth;
  359. pcie_reg += 0x12;
  360. pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
  361. lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
  362. lwidth = (pcie_lstat &
  363. (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
  364. strcpy(str, "PCIe (");
  365. if (lspeed == 1)
  366. strcat(str, "2.5GT/s ");
  367. else if (lspeed == 2)
  368. strcat(str, "5.0GT/s ");
  369. else
  370. strcat(str, "<unknown> ");
  371. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  372. strcat(str, lwstr);
  373. return str;
  374. }
  375. strcpy(str, "PCI");
  376. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  377. if (pci_bus == 0 || pci_bus == 8) {
  378. strcat(str, " (");
  379. strcat(str, pci_bus_modes[pci_bus >> 3]);
  380. } else {
  381. strcat(str, "-X ");
  382. if (pci_bus & BIT_2)
  383. strcat(str, "Mode 2");
  384. else
  385. strcat(str, "Mode 1");
  386. strcat(str, " (");
  387. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  388. }
  389. strcat(str, " MHz)");
  390. return str;
  391. }
  392. static char *
  393. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
  394. {
  395. char un_str[10];
  396. struct qla_hw_data *ha = vha->hw;
  397. sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
  398. ha->fw_minor_version,
  399. ha->fw_subminor_version);
  400. if (ha->fw_attributes & BIT_9) {
  401. strcat(str, "FLX");
  402. return (str);
  403. }
  404. switch (ha->fw_attributes & 0xFF) {
  405. case 0x7:
  406. strcat(str, "EF");
  407. break;
  408. case 0x17:
  409. strcat(str, "TP");
  410. break;
  411. case 0x37:
  412. strcat(str, "IP");
  413. break;
  414. case 0x77:
  415. strcat(str, "VI");
  416. break;
  417. default:
  418. sprintf(un_str, "(%x)", ha->fw_attributes);
  419. strcat(str, un_str);
  420. break;
  421. }
  422. if (ha->fw_attributes & 0x100)
  423. strcat(str, "X");
  424. return (str);
  425. }
  426. static char *
  427. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
  428. {
  429. struct qla_hw_data *ha = vha->hw;
  430. sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
  431. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  432. return str;
  433. }
  434. static inline srb_t *
  435. qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
  436. struct scsi_cmnd *cmd)
  437. {
  438. srb_t *sp;
  439. struct qla_hw_data *ha = vha->hw;
  440. sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
  441. if (!sp)
  442. return sp;
  443. atomic_set(&sp->ref_count, 1);
  444. sp->fcport = fcport;
  445. sp->cmd = cmd;
  446. sp->flags = 0;
  447. CMD_SP(cmd) = (void *)sp;
  448. sp->ctx = NULL;
  449. return sp;
  450. }
  451. static int
  452. qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  453. {
  454. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  455. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  456. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  457. struct qla_hw_data *ha = vha->hw;
  458. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  459. srb_t *sp;
  460. int rval;
  461. if (ha->flags.eeh_busy) {
  462. if (ha->flags.pci_channel_io_perm_failure)
  463. cmd->result = DID_NO_CONNECT << 16;
  464. else
  465. cmd->result = DID_REQUEUE << 16;
  466. goto qc24_fail_command;
  467. }
  468. rval = fc_remote_port_chkready(rport);
  469. if (rval) {
  470. cmd->result = rval;
  471. goto qc24_fail_command;
  472. }
  473. if (!vha->flags.difdix_supported &&
  474. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  475. DEBUG2(qla_printk(KERN_ERR, ha,
  476. "DIF Cap Not Reg, fail DIF capable cmd's:%x\n",
  477. cmd->cmnd[0]));
  478. cmd->result = DID_NO_CONNECT << 16;
  479. goto qc24_fail_command;
  480. }
  481. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  482. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  483. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  484. cmd->result = DID_NO_CONNECT << 16;
  485. goto qc24_fail_command;
  486. }
  487. goto qc24_target_busy;
  488. }
  489. sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
  490. if (!sp)
  491. goto qc24_host_busy;
  492. rval = ha->isp_ops->start_scsi(sp);
  493. if (rval != QLA_SUCCESS)
  494. goto qc24_host_busy_free_sp;
  495. return 0;
  496. qc24_host_busy_free_sp:
  497. qla2x00_sp_free_dma(sp);
  498. mempool_free(sp, ha->srb_mempool);
  499. qc24_host_busy:
  500. return SCSI_MLQUEUE_HOST_BUSY;
  501. qc24_target_busy:
  502. return SCSI_MLQUEUE_TARGET_BUSY;
  503. qc24_fail_command:
  504. cmd->scsi_done(cmd);
  505. return 0;
  506. }
  507. /*
  508. * qla2x00_eh_wait_on_command
  509. * Waits for the command to be returned by the Firmware for some
  510. * max time.
  511. *
  512. * Input:
  513. * cmd = Scsi Command to wait on.
  514. *
  515. * Return:
  516. * Not Found : 0
  517. * Found : 1
  518. */
  519. static int
  520. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  521. {
  522. #define ABORT_POLLING_PERIOD 1000
  523. #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
  524. unsigned long wait_iter = ABORT_WAIT_ITER;
  525. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  526. struct qla_hw_data *ha = vha->hw;
  527. int ret = QLA_SUCCESS;
  528. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  529. DEBUG17(qla_printk(KERN_WARNING, ha, "return:eh_wait\n"));
  530. return ret;
  531. }
  532. while (CMD_SP(cmd) && wait_iter--) {
  533. msleep(ABORT_POLLING_PERIOD);
  534. }
  535. if (CMD_SP(cmd))
  536. ret = QLA_FUNCTION_FAILED;
  537. return ret;
  538. }
  539. /*
  540. * qla2x00_wait_for_hba_online
  541. * Wait till the HBA is online after going through
  542. * <= MAX_RETRIES_OF_ISP_ABORT or
  543. * finally HBA is disabled ie marked offline
  544. *
  545. * Input:
  546. * ha - pointer to host adapter structure
  547. *
  548. * Note:
  549. * Does context switching-Release SPIN_LOCK
  550. * (if any) before calling this routine.
  551. *
  552. * Return:
  553. * Success (Adapter is online) : 0
  554. * Failed (Adapter is offline/disabled) : 1
  555. */
  556. int
  557. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  558. {
  559. int return_status;
  560. unsigned long wait_online;
  561. struct qla_hw_data *ha = vha->hw;
  562. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  563. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  564. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  565. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  566. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  567. ha->dpc_active) && time_before(jiffies, wait_online)) {
  568. msleep(1000);
  569. }
  570. if (base_vha->flags.online)
  571. return_status = QLA_SUCCESS;
  572. else
  573. return_status = QLA_FUNCTION_FAILED;
  574. return (return_status);
  575. }
  576. /*
  577. * qla2x00_wait_for_reset_ready
  578. * Wait till the HBA is online after going through
  579. * <= MAX_RETRIES_OF_ISP_ABORT or
  580. * finally HBA is disabled ie marked offline or flash
  581. * operations are in progress.
  582. *
  583. * Input:
  584. * ha - pointer to host adapter structure
  585. *
  586. * Note:
  587. * Does context switching-Release SPIN_LOCK
  588. * (if any) before calling this routine.
  589. *
  590. * Return:
  591. * Success (Adapter is online/no flash ops) : 0
  592. * Failed (Adapter is offline/disabled/flash ops in progress) : 1
  593. */
  594. static int
  595. qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
  596. {
  597. int return_status;
  598. unsigned long wait_online;
  599. struct qla_hw_data *ha = vha->hw;
  600. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  601. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  602. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  603. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  604. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  605. ha->optrom_state != QLA_SWAITING ||
  606. ha->dpc_active) && time_before(jiffies, wait_online))
  607. msleep(1000);
  608. if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
  609. return_status = QLA_SUCCESS;
  610. else
  611. return_status = QLA_FUNCTION_FAILED;
  612. DEBUG2(printk("%s return_status=%d\n", __func__, return_status));
  613. return return_status;
  614. }
  615. int
  616. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  617. {
  618. int return_status;
  619. unsigned long wait_reset;
  620. struct qla_hw_data *ha = vha->hw;
  621. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  622. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  623. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  624. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  625. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  626. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  627. msleep(1000);
  628. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  629. ha->flags.chip_reset_done)
  630. break;
  631. }
  632. if (ha->flags.chip_reset_done)
  633. return_status = QLA_SUCCESS;
  634. else
  635. return_status = QLA_FUNCTION_FAILED;
  636. return return_status;
  637. }
  638. /*
  639. * qla2x00_wait_for_loop_ready
  640. * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
  641. * to be in LOOP_READY state.
  642. * Input:
  643. * ha - pointer to host adapter structure
  644. *
  645. * Note:
  646. * Does context switching-Release SPIN_LOCK
  647. * (if any) before calling this routine.
  648. *
  649. *
  650. * Return:
  651. * Success (LOOP_READY) : 0
  652. * Failed (LOOP_NOT_READY) : 1
  653. */
  654. static inline int
  655. qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
  656. {
  657. int return_status = QLA_SUCCESS;
  658. unsigned long loop_timeout ;
  659. struct qla_hw_data *ha = vha->hw;
  660. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  661. /* wait for 5 min at the max for loop to be ready */
  662. loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  663. while ((!atomic_read(&base_vha->loop_down_timer) &&
  664. atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
  665. atomic_read(&base_vha->loop_state) != LOOP_READY) {
  666. if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  667. return_status = QLA_FUNCTION_FAILED;
  668. break;
  669. }
  670. msleep(1000);
  671. if (time_after_eq(jiffies, loop_timeout)) {
  672. return_status = QLA_FUNCTION_FAILED;
  673. break;
  674. }
  675. }
  676. return (return_status);
  677. }
  678. static void
  679. sp_get(struct srb *sp)
  680. {
  681. atomic_inc(&sp->ref_count);
  682. }
  683. /**************************************************************************
  684. * qla2xxx_eh_abort
  685. *
  686. * Description:
  687. * The abort function will abort the specified command.
  688. *
  689. * Input:
  690. * cmd = Linux SCSI command packet to be aborted.
  691. *
  692. * Returns:
  693. * Either SUCCESS or FAILED.
  694. *
  695. * Note:
  696. * Only return FAILED if command not returned by firmware.
  697. **************************************************************************/
  698. static int
  699. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  700. {
  701. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  702. srb_t *sp;
  703. int ret;
  704. unsigned int id, lun;
  705. unsigned long flags;
  706. int wait = 0;
  707. struct qla_hw_data *ha = vha->hw;
  708. if (!CMD_SP(cmd))
  709. return SUCCESS;
  710. ret = fc_block_scsi_eh(cmd);
  711. if (ret != 0)
  712. return ret;
  713. ret = SUCCESS;
  714. id = cmd->device->id;
  715. lun = cmd->device->lun;
  716. spin_lock_irqsave(&ha->hardware_lock, flags);
  717. sp = (srb_t *) CMD_SP(cmd);
  718. if (!sp) {
  719. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  720. return SUCCESS;
  721. }
  722. DEBUG2(printk("%s(%ld): aborting sp %p from RISC.",
  723. __func__, vha->host_no, sp));
  724. /* Get a reference to the sp and drop the lock.*/
  725. sp_get(sp);
  726. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  727. if (ha->isp_ops->abort_command(sp)) {
  728. DEBUG2(printk("%s(%ld): abort_command "
  729. "mbx failed.\n", __func__, vha->host_no));
  730. ret = FAILED;
  731. } else {
  732. DEBUG3(printk("%s(%ld): abort_command "
  733. "mbx success.\n", __func__, vha->host_no));
  734. wait = 1;
  735. }
  736. qla2x00_sp_compl(ha, sp);
  737. /* Wait for the command to be returned. */
  738. if (wait) {
  739. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  740. qla_printk(KERN_ERR, ha,
  741. "scsi(%ld:%d:%d): Abort handler timed out -- %x.\n",
  742. vha->host_no, id, lun, ret);
  743. ret = FAILED;
  744. }
  745. }
  746. qla_printk(KERN_INFO, ha,
  747. "scsi(%ld:%d:%d): Abort command issued -- %d %x.\n",
  748. vha->host_no, id, lun, wait, ret);
  749. return ret;
  750. }
  751. int
  752. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  753. unsigned int l, enum nexus_wait_type type)
  754. {
  755. int cnt, match, status;
  756. unsigned long flags;
  757. struct qla_hw_data *ha = vha->hw;
  758. struct req_que *req;
  759. srb_t *sp;
  760. status = QLA_SUCCESS;
  761. spin_lock_irqsave(&ha->hardware_lock, flags);
  762. req = vha->req;
  763. for (cnt = 1; status == QLA_SUCCESS &&
  764. cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  765. sp = req->outstanding_cmds[cnt];
  766. if (!sp)
  767. continue;
  768. if ((sp->ctx) && !IS_PROT_IO(sp))
  769. continue;
  770. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  771. continue;
  772. match = 0;
  773. switch (type) {
  774. case WAIT_HOST:
  775. match = 1;
  776. break;
  777. case WAIT_TARGET:
  778. match = sp->cmd->device->id == t;
  779. break;
  780. case WAIT_LUN:
  781. match = (sp->cmd->device->id == t &&
  782. sp->cmd->device->lun == l);
  783. break;
  784. }
  785. if (!match)
  786. continue;
  787. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  788. status = qla2x00_eh_wait_on_command(sp->cmd);
  789. spin_lock_irqsave(&ha->hardware_lock, flags);
  790. }
  791. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  792. return status;
  793. }
  794. static char *reset_errors[] = {
  795. "HBA not online",
  796. "HBA not ready",
  797. "Task management failed",
  798. "Waiting for command completions",
  799. };
  800. static int
  801. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  802. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
  803. {
  804. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  805. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  806. int err;
  807. if (!fcport)
  808. return FAILED;
  809. err = fc_block_scsi_eh(cmd);
  810. if (err != 0)
  811. return err;
  812. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET ISSUED.\n",
  813. vha->host_no, cmd->device->id, cmd->device->lun, name);
  814. err = 0;
  815. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  816. goto eh_reset_failed;
  817. err = 1;
  818. if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS)
  819. goto eh_reset_failed;
  820. err = 2;
  821. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  822. != QLA_SUCCESS)
  823. goto eh_reset_failed;
  824. err = 3;
  825. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  826. cmd->device->lun, type) != QLA_SUCCESS)
  827. goto eh_reset_failed;
  828. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET SUCCEEDED.\n",
  829. vha->host_no, cmd->device->id, cmd->device->lun, name);
  830. return SUCCESS;
  831. eh_reset_failed:
  832. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET FAILED: %s.\n"
  833. , vha->host_no, cmd->device->id, cmd->device->lun, name,
  834. reset_errors[err]);
  835. return FAILED;
  836. }
  837. static int
  838. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  839. {
  840. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  841. struct qla_hw_data *ha = vha->hw;
  842. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  843. ha->isp_ops->lun_reset);
  844. }
  845. static int
  846. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  847. {
  848. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  849. struct qla_hw_data *ha = vha->hw;
  850. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  851. ha->isp_ops->target_reset);
  852. }
  853. /**************************************************************************
  854. * qla2xxx_eh_bus_reset
  855. *
  856. * Description:
  857. * The bus reset function will reset the bus and abort any executing
  858. * commands.
  859. *
  860. * Input:
  861. * cmd = Linux SCSI command packet of the command that cause the
  862. * bus reset.
  863. *
  864. * Returns:
  865. * SUCCESS/FAILURE (defined as macro in scsi.h).
  866. *
  867. **************************************************************************/
  868. static int
  869. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  870. {
  871. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  872. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  873. int ret = FAILED;
  874. unsigned int id, lun;
  875. id = cmd->device->id;
  876. lun = cmd->device->lun;
  877. if (!fcport)
  878. return ret;
  879. ret = fc_block_scsi_eh(cmd);
  880. if (ret != 0)
  881. return ret;
  882. ret = FAILED;
  883. qla_printk(KERN_INFO, vha->hw,
  884. "scsi(%ld:%d:%d): BUS RESET ISSUED.\n", vha->host_no, id, lun);
  885. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  886. DEBUG2(printk("%s failed:board disabled\n",__func__));
  887. goto eh_bus_reset_done;
  888. }
  889. if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
  890. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  891. ret = SUCCESS;
  892. }
  893. if (ret == FAILED)
  894. goto eh_bus_reset_done;
  895. /* Flush outstanding commands. */
  896. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  897. QLA_SUCCESS)
  898. ret = FAILED;
  899. eh_bus_reset_done:
  900. qla_printk(KERN_INFO, vha->hw, "%s: reset %s\n", __func__,
  901. (ret == FAILED) ? "failed" : "succeded");
  902. return ret;
  903. }
  904. /**************************************************************************
  905. * qla2xxx_eh_host_reset
  906. *
  907. * Description:
  908. * The reset function will reset the Adapter.
  909. *
  910. * Input:
  911. * cmd = Linux SCSI command packet of the command that cause the
  912. * adapter reset.
  913. *
  914. * Returns:
  915. * Either SUCCESS or FAILED.
  916. *
  917. * Note:
  918. **************************************************************************/
  919. static int
  920. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  921. {
  922. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  923. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  924. struct qla_hw_data *ha = vha->hw;
  925. int ret = FAILED;
  926. unsigned int id, lun;
  927. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  928. id = cmd->device->id;
  929. lun = cmd->device->lun;
  930. if (!fcport)
  931. return ret;
  932. ret = fc_block_scsi_eh(cmd);
  933. if (ret != 0)
  934. return ret;
  935. ret = FAILED;
  936. qla_printk(KERN_INFO, ha,
  937. "scsi(%ld:%d:%d): ADAPTER RESET ISSUED.\n", vha->host_no, id, lun);
  938. if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
  939. goto eh_host_reset_lock;
  940. /*
  941. * Fixme-may be dpc thread is active and processing
  942. * loop_resync,so wait a while for it to
  943. * be completed and then issue big hammer.Otherwise
  944. * it may cause I/O failure as big hammer marks the
  945. * devices as lost kicking of the port_down_timer
  946. * while dpc is stuck for the mailbox to complete.
  947. */
  948. qla2x00_wait_for_loop_ready(vha);
  949. if (vha != base_vha) {
  950. if (qla2x00_vp_abort_isp(vha))
  951. goto eh_host_reset_lock;
  952. } else {
  953. if (IS_QLA82XX(vha->hw)) {
  954. if (!qla82xx_fcoe_ctx_reset(vha)) {
  955. /* Ctx reset success */
  956. ret = SUCCESS;
  957. goto eh_host_reset_lock;
  958. }
  959. /* fall thru if ctx reset failed */
  960. }
  961. if (ha->wq)
  962. flush_workqueue(ha->wq);
  963. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  964. if (ha->isp_ops->abort_isp(base_vha)) {
  965. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  966. /* failed. schedule dpc to try */
  967. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  968. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  969. goto eh_host_reset_lock;
  970. }
  971. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  972. }
  973. /* Waiting for command to be returned to OS.*/
  974. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  975. QLA_SUCCESS)
  976. ret = SUCCESS;
  977. eh_host_reset_lock:
  978. qla_printk(KERN_INFO, ha, "%s: reset %s\n", __func__,
  979. (ret == FAILED) ? "failed" : "succeded");
  980. return ret;
  981. }
  982. /*
  983. * qla2x00_loop_reset
  984. * Issue loop reset.
  985. *
  986. * Input:
  987. * ha = adapter block pointer.
  988. *
  989. * Returns:
  990. * 0 = success
  991. */
  992. int
  993. qla2x00_loop_reset(scsi_qla_host_t *vha)
  994. {
  995. int ret;
  996. struct fc_port *fcport;
  997. struct qla_hw_data *ha = vha->hw;
  998. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  999. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1000. if (fcport->port_type != FCT_TARGET)
  1001. continue;
  1002. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  1003. if (ret != QLA_SUCCESS) {
  1004. DEBUG2_3(printk("%s(%ld): bus_reset failed: "
  1005. "target_reset=%d d_id=%x.\n", __func__,
  1006. vha->host_no, ret, fcport->d_id.b24));
  1007. }
  1008. }
  1009. }
  1010. if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
  1011. ret = qla2x00_full_login_lip(vha);
  1012. if (ret != QLA_SUCCESS) {
  1013. DEBUG2_3(printk("%s(%ld): failed: "
  1014. "full_login_lip=%d.\n", __func__, vha->host_no,
  1015. ret));
  1016. }
  1017. atomic_set(&vha->loop_state, LOOP_DOWN);
  1018. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1019. qla2x00_mark_all_devices_lost(vha, 0);
  1020. qla2x00_wait_for_loop_ready(vha);
  1021. }
  1022. if (ha->flags.enable_lip_reset) {
  1023. ret = qla2x00_lip_reset(vha);
  1024. if (ret != QLA_SUCCESS) {
  1025. DEBUG2_3(printk("%s(%ld): failed: "
  1026. "lip_reset=%d.\n", __func__, vha->host_no, ret));
  1027. } else
  1028. qla2x00_wait_for_loop_ready(vha);
  1029. }
  1030. /* Issue marker command only when we are going to start the I/O */
  1031. vha->marker_needed = 1;
  1032. return QLA_SUCCESS;
  1033. }
  1034. void
  1035. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1036. {
  1037. int que, cnt;
  1038. unsigned long flags;
  1039. srb_t *sp;
  1040. struct srb_ctx *ctx;
  1041. struct qla_hw_data *ha = vha->hw;
  1042. struct req_que *req;
  1043. spin_lock_irqsave(&ha->hardware_lock, flags);
  1044. for (que = 0; que < ha->max_req_queues; que++) {
  1045. req = ha->req_q_map[que];
  1046. if (!req)
  1047. continue;
  1048. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  1049. sp = req->outstanding_cmds[cnt];
  1050. if (sp) {
  1051. req->outstanding_cmds[cnt] = NULL;
  1052. if (!sp->ctx ||
  1053. (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
  1054. IS_PROT_IO(sp)) {
  1055. sp->cmd->result = res;
  1056. qla2x00_sp_compl(ha, sp);
  1057. } else {
  1058. ctx = sp->ctx;
  1059. if (ctx->type == SRB_LOGIN_CMD ||
  1060. ctx->type == SRB_LOGOUT_CMD) {
  1061. ctx->u.iocb_cmd->free(sp);
  1062. } else {
  1063. struct fc_bsg_job *bsg_job =
  1064. ctx->u.bsg_job;
  1065. if (bsg_job->request->msgcode
  1066. == FC_BSG_HST_CT)
  1067. kfree(sp->fcport);
  1068. bsg_job->req->errors = 0;
  1069. bsg_job->reply->result = res;
  1070. bsg_job->job_done(bsg_job);
  1071. kfree(sp->ctx);
  1072. mempool_free(sp,
  1073. ha->srb_mempool);
  1074. }
  1075. }
  1076. }
  1077. }
  1078. }
  1079. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1080. }
  1081. static int
  1082. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1083. {
  1084. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1085. if (!rport || fc_remote_port_chkready(rport))
  1086. return -ENXIO;
  1087. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1088. return 0;
  1089. }
  1090. static int
  1091. qla2xxx_slave_configure(struct scsi_device *sdev)
  1092. {
  1093. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1094. struct req_que *req = vha->req;
  1095. if (sdev->tagged_supported)
  1096. scsi_activate_tcq(sdev, req->max_q_depth);
  1097. else
  1098. scsi_deactivate_tcq(sdev, req->max_q_depth);
  1099. return 0;
  1100. }
  1101. static void
  1102. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1103. {
  1104. sdev->hostdata = NULL;
  1105. }
  1106. static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
  1107. {
  1108. fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
  1109. if (!scsi_track_queue_full(sdev, qdepth))
  1110. return;
  1111. DEBUG2(qla_printk(KERN_INFO, fcport->vha->hw,
  1112. "scsi(%ld:%d:%d:%d): Queue depth adjusted-down to %d.\n",
  1113. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1114. sdev->queue_depth));
  1115. }
  1116. static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
  1117. {
  1118. fc_port_t *fcport = sdev->hostdata;
  1119. struct scsi_qla_host *vha = fcport->vha;
  1120. struct qla_hw_data *ha = vha->hw;
  1121. struct req_que *req = NULL;
  1122. req = vha->req;
  1123. if (!req)
  1124. return;
  1125. if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
  1126. return;
  1127. if (sdev->ordered_tags)
  1128. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
  1129. else
  1130. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
  1131. DEBUG2(qla_printk(KERN_INFO, ha,
  1132. "scsi(%ld:%d:%d:%d): Queue depth adjusted-up to %d.\n",
  1133. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1134. sdev->queue_depth));
  1135. }
  1136. static int
  1137. qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
  1138. {
  1139. switch (reason) {
  1140. case SCSI_QDEPTH_DEFAULT:
  1141. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1142. break;
  1143. case SCSI_QDEPTH_QFULL:
  1144. qla2x00_handle_queue_full(sdev, qdepth);
  1145. break;
  1146. case SCSI_QDEPTH_RAMP_UP:
  1147. qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
  1148. break;
  1149. default:
  1150. return -EOPNOTSUPP;
  1151. }
  1152. return sdev->queue_depth;
  1153. }
  1154. static int
  1155. qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
  1156. {
  1157. if (sdev->tagged_supported) {
  1158. scsi_set_tag_type(sdev, tag_type);
  1159. if (tag_type)
  1160. scsi_activate_tcq(sdev, sdev->queue_depth);
  1161. else
  1162. scsi_deactivate_tcq(sdev, sdev->queue_depth);
  1163. } else
  1164. tag_type = 0;
  1165. return tag_type;
  1166. }
  1167. /**
  1168. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1169. * @ha: HA context
  1170. *
  1171. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1172. * supported addressing method.
  1173. */
  1174. static void
  1175. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1176. {
  1177. /* Assume a 32bit DMA mask. */
  1178. ha->flags.enable_64bit_addressing = 0;
  1179. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1180. /* Any upper-dword bits set? */
  1181. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1182. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1183. /* Ok, a 64bit DMA mask is applicable. */
  1184. ha->flags.enable_64bit_addressing = 1;
  1185. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1186. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1187. return;
  1188. }
  1189. }
  1190. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1191. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1192. }
  1193. static void
  1194. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1195. {
  1196. unsigned long flags = 0;
  1197. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1198. spin_lock_irqsave(&ha->hardware_lock, flags);
  1199. ha->interrupts_on = 1;
  1200. /* enable risc and host interrupts */
  1201. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1202. RD_REG_WORD(&reg->ictrl);
  1203. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1204. }
  1205. static void
  1206. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1207. {
  1208. unsigned long flags = 0;
  1209. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1210. spin_lock_irqsave(&ha->hardware_lock, flags);
  1211. ha->interrupts_on = 0;
  1212. /* disable risc and host interrupts */
  1213. WRT_REG_WORD(&reg->ictrl, 0);
  1214. RD_REG_WORD(&reg->ictrl);
  1215. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1216. }
  1217. static void
  1218. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1219. {
  1220. unsigned long flags = 0;
  1221. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1222. spin_lock_irqsave(&ha->hardware_lock, flags);
  1223. ha->interrupts_on = 1;
  1224. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1225. RD_REG_DWORD(&reg->ictrl);
  1226. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1227. }
  1228. static void
  1229. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1230. {
  1231. unsigned long flags = 0;
  1232. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1233. if (IS_NOPOLLING_TYPE(ha))
  1234. return;
  1235. spin_lock_irqsave(&ha->hardware_lock, flags);
  1236. ha->interrupts_on = 0;
  1237. WRT_REG_DWORD(&reg->ictrl, 0);
  1238. RD_REG_DWORD(&reg->ictrl);
  1239. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1240. }
  1241. static struct isp_operations qla2100_isp_ops = {
  1242. .pci_config = qla2100_pci_config,
  1243. .reset_chip = qla2x00_reset_chip,
  1244. .chip_diag = qla2x00_chip_diag,
  1245. .config_rings = qla2x00_config_rings,
  1246. .reset_adapter = qla2x00_reset_adapter,
  1247. .nvram_config = qla2x00_nvram_config,
  1248. .update_fw_options = qla2x00_update_fw_options,
  1249. .load_risc = qla2x00_load_risc,
  1250. .pci_info_str = qla2x00_pci_info_str,
  1251. .fw_version_str = qla2x00_fw_version_str,
  1252. .intr_handler = qla2100_intr_handler,
  1253. .enable_intrs = qla2x00_enable_intrs,
  1254. .disable_intrs = qla2x00_disable_intrs,
  1255. .abort_command = qla2x00_abort_command,
  1256. .target_reset = qla2x00_abort_target,
  1257. .lun_reset = qla2x00_lun_reset,
  1258. .fabric_login = qla2x00_login_fabric,
  1259. .fabric_logout = qla2x00_fabric_logout,
  1260. .calc_req_entries = qla2x00_calc_iocbs_32,
  1261. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1262. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1263. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1264. .read_nvram = qla2x00_read_nvram_data,
  1265. .write_nvram = qla2x00_write_nvram_data,
  1266. .fw_dump = qla2100_fw_dump,
  1267. .beacon_on = NULL,
  1268. .beacon_off = NULL,
  1269. .beacon_blink = NULL,
  1270. .read_optrom = qla2x00_read_optrom_data,
  1271. .write_optrom = qla2x00_write_optrom_data,
  1272. .get_flash_version = qla2x00_get_flash_version,
  1273. .start_scsi = qla2x00_start_scsi,
  1274. .abort_isp = qla2x00_abort_isp,
  1275. };
  1276. static struct isp_operations qla2300_isp_ops = {
  1277. .pci_config = qla2300_pci_config,
  1278. .reset_chip = qla2x00_reset_chip,
  1279. .chip_diag = qla2x00_chip_diag,
  1280. .config_rings = qla2x00_config_rings,
  1281. .reset_adapter = qla2x00_reset_adapter,
  1282. .nvram_config = qla2x00_nvram_config,
  1283. .update_fw_options = qla2x00_update_fw_options,
  1284. .load_risc = qla2x00_load_risc,
  1285. .pci_info_str = qla2x00_pci_info_str,
  1286. .fw_version_str = qla2x00_fw_version_str,
  1287. .intr_handler = qla2300_intr_handler,
  1288. .enable_intrs = qla2x00_enable_intrs,
  1289. .disable_intrs = qla2x00_disable_intrs,
  1290. .abort_command = qla2x00_abort_command,
  1291. .target_reset = qla2x00_abort_target,
  1292. .lun_reset = qla2x00_lun_reset,
  1293. .fabric_login = qla2x00_login_fabric,
  1294. .fabric_logout = qla2x00_fabric_logout,
  1295. .calc_req_entries = qla2x00_calc_iocbs_32,
  1296. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1297. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1298. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1299. .read_nvram = qla2x00_read_nvram_data,
  1300. .write_nvram = qla2x00_write_nvram_data,
  1301. .fw_dump = qla2300_fw_dump,
  1302. .beacon_on = qla2x00_beacon_on,
  1303. .beacon_off = qla2x00_beacon_off,
  1304. .beacon_blink = qla2x00_beacon_blink,
  1305. .read_optrom = qla2x00_read_optrom_data,
  1306. .write_optrom = qla2x00_write_optrom_data,
  1307. .get_flash_version = qla2x00_get_flash_version,
  1308. .start_scsi = qla2x00_start_scsi,
  1309. .abort_isp = qla2x00_abort_isp,
  1310. };
  1311. static struct isp_operations qla24xx_isp_ops = {
  1312. .pci_config = qla24xx_pci_config,
  1313. .reset_chip = qla24xx_reset_chip,
  1314. .chip_diag = qla24xx_chip_diag,
  1315. .config_rings = qla24xx_config_rings,
  1316. .reset_adapter = qla24xx_reset_adapter,
  1317. .nvram_config = qla24xx_nvram_config,
  1318. .update_fw_options = qla24xx_update_fw_options,
  1319. .load_risc = qla24xx_load_risc,
  1320. .pci_info_str = qla24xx_pci_info_str,
  1321. .fw_version_str = qla24xx_fw_version_str,
  1322. .intr_handler = qla24xx_intr_handler,
  1323. .enable_intrs = qla24xx_enable_intrs,
  1324. .disable_intrs = qla24xx_disable_intrs,
  1325. .abort_command = qla24xx_abort_command,
  1326. .target_reset = qla24xx_abort_target,
  1327. .lun_reset = qla24xx_lun_reset,
  1328. .fabric_login = qla24xx_login_fabric,
  1329. .fabric_logout = qla24xx_fabric_logout,
  1330. .calc_req_entries = NULL,
  1331. .build_iocbs = NULL,
  1332. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1333. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1334. .read_nvram = qla24xx_read_nvram_data,
  1335. .write_nvram = qla24xx_write_nvram_data,
  1336. .fw_dump = qla24xx_fw_dump,
  1337. .beacon_on = qla24xx_beacon_on,
  1338. .beacon_off = qla24xx_beacon_off,
  1339. .beacon_blink = qla24xx_beacon_blink,
  1340. .read_optrom = qla24xx_read_optrom_data,
  1341. .write_optrom = qla24xx_write_optrom_data,
  1342. .get_flash_version = qla24xx_get_flash_version,
  1343. .start_scsi = qla24xx_start_scsi,
  1344. .abort_isp = qla2x00_abort_isp,
  1345. };
  1346. static struct isp_operations qla25xx_isp_ops = {
  1347. .pci_config = qla25xx_pci_config,
  1348. .reset_chip = qla24xx_reset_chip,
  1349. .chip_diag = qla24xx_chip_diag,
  1350. .config_rings = qla24xx_config_rings,
  1351. .reset_adapter = qla24xx_reset_adapter,
  1352. .nvram_config = qla24xx_nvram_config,
  1353. .update_fw_options = qla24xx_update_fw_options,
  1354. .load_risc = qla24xx_load_risc,
  1355. .pci_info_str = qla24xx_pci_info_str,
  1356. .fw_version_str = qla24xx_fw_version_str,
  1357. .intr_handler = qla24xx_intr_handler,
  1358. .enable_intrs = qla24xx_enable_intrs,
  1359. .disable_intrs = qla24xx_disable_intrs,
  1360. .abort_command = qla24xx_abort_command,
  1361. .target_reset = qla24xx_abort_target,
  1362. .lun_reset = qla24xx_lun_reset,
  1363. .fabric_login = qla24xx_login_fabric,
  1364. .fabric_logout = qla24xx_fabric_logout,
  1365. .calc_req_entries = NULL,
  1366. .build_iocbs = NULL,
  1367. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1368. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1369. .read_nvram = qla25xx_read_nvram_data,
  1370. .write_nvram = qla25xx_write_nvram_data,
  1371. .fw_dump = qla25xx_fw_dump,
  1372. .beacon_on = qla24xx_beacon_on,
  1373. .beacon_off = qla24xx_beacon_off,
  1374. .beacon_blink = qla24xx_beacon_blink,
  1375. .read_optrom = qla25xx_read_optrom_data,
  1376. .write_optrom = qla24xx_write_optrom_data,
  1377. .get_flash_version = qla24xx_get_flash_version,
  1378. .start_scsi = qla24xx_dif_start_scsi,
  1379. .abort_isp = qla2x00_abort_isp,
  1380. };
  1381. static struct isp_operations qla81xx_isp_ops = {
  1382. .pci_config = qla25xx_pci_config,
  1383. .reset_chip = qla24xx_reset_chip,
  1384. .chip_diag = qla24xx_chip_diag,
  1385. .config_rings = qla24xx_config_rings,
  1386. .reset_adapter = qla24xx_reset_adapter,
  1387. .nvram_config = qla81xx_nvram_config,
  1388. .update_fw_options = qla81xx_update_fw_options,
  1389. .load_risc = qla81xx_load_risc,
  1390. .pci_info_str = qla24xx_pci_info_str,
  1391. .fw_version_str = qla24xx_fw_version_str,
  1392. .intr_handler = qla24xx_intr_handler,
  1393. .enable_intrs = qla24xx_enable_intrs,
  1394. .disable_intrs = qla24xx_disable_intrs,
  1395. .abort_command = qla24xx_abort_command,
  1396. .target_reset = qla24xx_abort_target,
  1397. .lun_reset = qla24xx_lun_reset,
  1398. .fabric_login = qla24xx_login_fabric,
  1399. .fabric_logout = qla24xx_fabric_logout,
  1400. .calc_req_entries = NULL,
  1401. .build_iocbs = NULL,
  1402. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1403. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1404. .read_nvram = NULL,
  1405. .write_nvram = NULL,
  1406. .fw_dump = qla81xx_fw_dump,
  1407. .beacon_on = qla24xx_beacon_on,
  1408. .beacon_off = qla24xx_beacon_off,
  1409. .beacon_blink = qla24xx_beacon_blink,
  1410. .read_optrom = qla25xx_read_optrom_data,
  1411. .write_optrom = qla24xx_write_optrom_data,
  1412. .get_flash_version = qla24xx_get_flash_version,
  1413. .start_scsi = qla24xx_dif_start_scsi,
  1414. .abort_isp = qla2x00_abort_isp,
  1415. };
  1416. static struct isp_operations qla82xx_isp_ops = {
  1417. .pci_config = qla82xx_pci_config,
  1418. .reset_chip = qla82xx_reset_chip,
  1419. .chip_diag = qla24xx_chip_diag,
  1420. .config_rings = qla82xx_config_rings,
  1421. .reset_adapter = qla24xx_reset_adapter,
  1422. .nvram_config = qla81xx_nvram_config,
  1423. .update_fw_options = qla24xx_update_fw_options,
  1424. .load_risc = qla82xx_load_risc,
  1425. .pci_info_str = qla82xx_pci_info_str,
  1426. .fw_version_str = qla24xx_fw_version_str,
  1427. .intr_handler = qla82xx_intr_handler,
  1428. .enable_intrs = qla82xx_enable_intrs,
  1429. .disable_intrs = qla82xx_disable_intrs,
  1430. .abort_command = qla24xx_abort_command,
  1431. .target_reset = qla24xx_abort_target,
  1432. .lun_reset = qla24xx_lun_reset,
  1433. .fabric_login = qla24xx_login_fabric,
  1434. .fabric_logout = qla24xx_fabric_logout,
  1435. .calc_req_entries = NULL,
  1436. .build_iocbs = NULL,
  1437. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1438. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1439. .read_nvram = qla24xx_read_nvram_data,
  1440. .write_nvram = qla24xx_write_nvram_data,
  1441. .fw_dump = qla24xx_fw_dump,
  1442. .beacon_on = qla24xx_beacon_on,
  1443. .beacon_off = qla24xx_beacon_off,
  1444. .beacon_blink = qla24xx_beacon_blink,
  1445. .read_optrom = qla82xx_read_optrom_data,
  1446. .write_optrom = qla82xx_write_optrom_data,
  1447. .get_flash_version = qla24xx_get_flash_version,
  1448. .start_scsi = qla82xx_start_scsi,
  1449. .abort_isp = qla82xx_abort_isp,
  1450. };
  1451. static inline void
  1452. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1453. {
  1454. ha->device_type = DT_EXTENDED_IDS;
  1455. switch (ha->pdev->device) {
  1456. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1457. ha->device_type |= DT_ISP2100;
  1458. ha->device_type &= ~DT_EXTENDED_IDS;
  1459. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1460. break;
  1461. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1462. ha->device_type |= DT_ISP2200;
  1463. ha->device_type &= ~DT_EXTENDED_IDS;
  1464. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1465. break;
  1466. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1467. ha->device_type |= DT_ISP2300;
  1468. ha->device_type |= DT_ZIO_SUPPORTED;
  1469. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1470. break;
  1471. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1472. ha->device_type |= DT_ISP2312;
  1473. ha->device_type |= DT_ZIO_SUPPORTED;
  1474. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1475. break;
  1476. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1477. ha->device_type |= DT_ISP2322;
  1478. ha->device_type |= DT_ZIO_SUPPORTED;
  1479. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1480. ha->pdev->subsystem_device == 0x0170)
  1481. ha->device_type |= DT_OEM_001;
  1482. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1483. break;
  1484. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1485. ha->device_type |= DT_ISP6312;
  1486. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1487. break;
  1488. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1489. ha->device_type |= DT_ISP6322;
  1490. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1491. break;
  1492. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1493. ha->device_type |= DT_ISP2422;
  1494. ha->device_type |= DT_ZIO_SUPPORTED;
  1495. ha->device_type |= DT_FWI2;
  1496. ha->device_type |= DT_IIDMA;
  1497. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1498. break;
  1499. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1500. ha->device_type |= DT_ISP2432;
  1501. ha->device_type |= DT_ZIO_SUPPORTED;
  1502. ha->device_type |= DT_FWI2;
  1503. ha->device_type |= DT_IIDMA;
  1504. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1505. break;
  1506. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1507. ha->device_type |= DT_ISP8432;
  1508. ha->device_type |= DT_ZIO_SUPPORTED;
  1509. ha->device_type |= DT_FWI2;
  1510. ha->device_type |= DT_IIDMA;
  1511. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1512. break;
  1513. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  1514. ha->device_type |= DT_ISP5422;
  1515. ha->device_type |= DT_FWI2;
  1516. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1517. break;
  1518. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  1519. ha->device_type |= DT_ISP5432;
  1520. ha->device_type |= DT_FWI2;
  1521. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1522. break;
  1523. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  1524. ha->device_type |= DT_ISP2532;
  1525. ha->device_type |= DT_ZIO_SUPPORTED;
  1526. ha->device_type |= DT_FWI2;
  1527. ha->device_type |= DT_IIDMA;
  1528. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1529. break;
  1530. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  1531. ha->device_type |= DT_ISP8001;
  1532. ha->device_type |= DT_ZIO_SUPPORTED;
  1533. ha->device_type |= DT_FWI2;
  1534. ha->device_type |= DT_IIDMA;
  1535. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1536. break;
  1537. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  1538. ha->device_type |= DT_ISP8021;
  1539. ha->device_type |= DT_ZIO_SUPPORTED;
  1540. ha->device_type |= DT_FWI2;
  1541. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1542. /* Initialize 82XX ISP flags */
  1543. qla82xx_init_flags(ha);
  1544. break;
  1545. }
  1546. if (IS_QLA82XX(ha))
  1547. ha->port_no = !(ha->portnum & 1);
  1548. else
  1549. /* Get adapter physical port no from interrupt pin register. */
  1550. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  1551. if (ha->port_no & 1)
  1552. ha->flags.port0 = 1;
  1553. else
  1554. ha->flags.port0 = 0;
  1555. }
  1556. static int
  1557. qla2x00_iospace_config(struct qla_hw_data *ha)
  1558. {
  1559. resource_size_t pio;
  1560. uint16_t msix;
  1561. int cpus;
  1562. if (IS_QLA82XX(ha))
  1563. return qla82xx_iospace_config(ha);
  1564. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1565. QLA2XXX_DRIVER_NAME)) {
  1566. qla_printk(KERN_WARNING, ha,
  1567. "Failed to reserve PIO/MMIO regions (%s)\n",
  1568. pci_name(ha->pdev));
  1569. goto iospace_error_exit;
  1570. }
  1571. if (!(ha->bars & 1))
  1572. goto skip_pio;
  1573. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1574. pio = pci_resource_start(ha->pdev, 0);
  1575. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1576. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1577. qla_printk(KERN_WARNING, ha,
  1578. "Invalid PCI I/O region size (%s)...\n",
  1579. pci_name(ha->pdev));
  1580. pio = 0;
  1581. }
  1582. } else {
  1583. qla_printk(KERN_WARNING, ha,
  1584. "region #0 not a PIO resource (%s)...\n",
  1585. pci_name(ha->pdev));
  1586. pio = 0;
  1587. }
  1588. ha->pio_address = pio;
  1589. skip_pio:
  1590. /* Use MMIO operations for all accesses. */
  1591. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1592. qla_printk(KERN_ERR, ha,
  1593. "region #1 not an MMIO resource (%s), aborting\n",
  1594. pci_name(ha->pdev));
  1595. goto iospace_error_exit;
  1596. }
  1597. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1598. qla_printk(KERN_ERR, ha,
  1599. "Invalid PCI mem region size (%s), aborting\n",
  1600. pci_name(ha->pdev));
  1601. goto iospace_error_exit;
  1602. }
  1603. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1604. if (!ha->iobase) {
  1605. qla_printk(KERN_ERR, ha,
  1606. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  1607. goto iospace_error_exit;
  1608. }
  1609. /* Determine queue resources */
  1610. ha->max_req_queues = ha->max_rsp_queues = 1;
  1611. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1612. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1613. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1614. goto mqiobase_exit;
  1615. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1616. pci_resource_len(ha->pdev, 3));
  1617. if (ha->mqiobase) {
  1618. /* Read MSIX vector size of the board */
  1619. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1620. ha->msix_count = msix;
  1621. /* Max queues are bounded by available msix vectors */
  1622. /* queue 0 uses two msix vectors */
  1623. if (ql2xmultique_tag) {
  1624. cpus = num_online_cpus();
  1625. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1626. (cpus + 1) : (ha->msix_count - 1);
  1627. ha->max_req_queues = 2;
  1628. } else if (ql2xmaxqueues > 1) {
  1629. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1630. QLA_MQ_SIZE : ql2xmaxqueues;
  1631. DEBUG2(qla_printk(KERN_INFO, ha, "QoS mode set, max no"
  1632. " of request queues:%d\n", ha->max_req_queues));
  1633. }
  1634. qla_printk(KERN_INFO, ha,
  1635. "MSI-X vector count: %d\n", msix);
  1636. } else
  1637. qla_printk(KERN_INFO, ha, "BAR 3 not enabled\n");
  1638. mqiobase_exit:
  1639. ha->msix_count = ha->max_rsp_queues + 1;
  1640. return (0);
  1641. iospace_error_exit:
  1642. return (-ENOMEM);
  1643. }
  1644. static void
  1645. qla2xxx_scan_start(struct Scsi_Host *shost)
  1646. {
  1647. scsi_qla_host_t *vha = shost_priv(shost);
  1648. if (vha->hw->flags.running_gold_fw)
  1649. return;
  1650. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1651. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1652. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  1653. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  1654. }
  1655. static int
  1656. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  1657. {
  1658. scsi_qla_host_t *vha = shost_priv(shost);
  1659. if (!vha->host)
  1660. return 1;
  1661. if (time > vha->hw->loop_reset_delay * HZ)
  1662. return 1;
  1663. return atomic_read(&vha->loop_state) == LOOP_READY;
  1664. }
  1665. /*
  1666. * PCI driver interface
  1667. */
  1668. static int __devinit
  1669. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1670. {
  1671. int ret = -ENODEV;
  1672. struct Scsi_Host *host;
  1673. scsi_qla_host_t *base_vha = NULL;
  1674. struct qla_hw_data *ha;
  1675. char pci_info[30];
  1676. char fw_str[30];
  1677. struct scsi_host_template *sht;
  1678. int bars, max_id, mem_only = 0;
  1679. uint16_t req_length = 0, rsp_length = 0;
  1680. struct req_que *req = NULL;
  1681. struct rsp_que *rsp = NULL;
  1682. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  1683. sht = &qla2xxx_driver_template;
  1684. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  1685. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  1686. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  1687. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  1688. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  1689. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  1690. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  1691. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
  1692. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1693. mem_only = 1;
  1694. }
  1695. if (mem_only) {
  1696. if (pci_enable_device_mem(pdev))
  1697. goto probe_out;
  1698. } else {
  1699. if (pci_enable_device(pdev))
  1700. goto probe_out;
  1701. }
  1702. /* This may fail but that's ok */
  1703. pci_enable_pcie_error_reporting(pdev);
  1704. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  1705. if (!ha) {
  1706. DEBUG(printk("Unable to allocate memory for ha\n"));
  1707. goto probe_out;
  1708. }
  1709. ha->pdev = pdev;
  1710. /* Clear our data area */
  1711. ha->bars = bars;
  1712. ha->mem_only = mem_only;
  1713. spin_lock_init(&ha->hardware_lock);
  1714. spin_lock_init(&ha->vport_slock);
  1715. /* Set ISP-type information. */
  1716. qla2x00_set_isp_flags(ha);
  1717. /* Set EEH reset type to fundamental if required by hba */
  1718. if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
  1719. pdev->needs_freset = 1;
  1720. }
  1721. /* Configure PCI I/O space */
  1722. ret = qla2x00_iospace_config(ha);
  1723. if (ret)
  1724. goto probe_hw_failed;
  1725. qla_printk(KERN_INFO, ha,
  1726. "Found an ISP%04X, irq %d, iobase 0x%p\n", pdev->device, pdev->irq,
  1727. ha->iobase);
  1728. ha->prev_topology = 0;
  1729. ha->init_cb_size = sizeof(init_cb_t);
  1730. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  1731. ha->optrom_size = OPTROM_SIZE_2300;
  1732. /* Assign ISP specific operations. */
  1733. max_id = MAX_TARGETS_2200;
  1734. if (IS_QLA2100(ha)) {
  1735. max_id = MAX_TARGETS_2100;
  1736. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  1737. req_length = REQUEST_ENTRY_CNT_2100;
  1738. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1739. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1740. ha->gid_list_info_size = 4;
  1741. ha->flash_conf_off = ~0;
  1742. ha->flash_data_off = ~0;
  1743. ha->nvram_conf_off = ~0;
  1744. ha->nvram_data_off = ~0;
  1745. ha->isp_ops = &qla2100_isp_ops;
  1746. } else if (IS_QLA2200(ha)) {
  1747. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1748. req_length = REQUEST_ENTRY_CNT_2200;
  1749. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1750. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1751. ha->gid_list_info_size = 4;
  1752. ha->flash_conf_off = ~0;
  1753. ha->flash_data_off = ~0;
  1754. ha->nvram_conf_off = ~0;
  1755. ha->nvram_data_off = ~0;
  1756. ha->isp_ops = &qla2100_isp_ops;
  1757. } else if (IS_QLA23XX(ha)) {
  1758. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1759. req_length = REQUEST_ENTRY_CNT_2200;
  1760. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1761. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1762. ha->gid_list_info_size = 6;
  1763. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1764. ha->optrom_size = OPTROM_SIZE_2322;
  1765. ha->flash_conf_off = ~0;
  1766. ha->flash_data_off = ~0;
  1767. ha->nvram_conf_off = ~0;
  1768. ha->nvram_data_off = ~0;
  1769. ha->isp_ops = &qla2300_isp_ops;
  1770. } else if (IS_QLA24XX_TYPE(ha)) {
  1771. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1772. req_length = REQUEST_ENTRY_CNT_24XX;
  1773. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1774. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1775. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1776. ha->gid_list_info_size = 8;
  1777. ha->optrom_size = OPTROM_SIZE_24XX;
  1778. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  1779. ha->isp_ops = &qla24xx_isp_ops;
  1780. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1781. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1782. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1783. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1784. } else if (IS_QLA25XX(ha)) {
  1785. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1786. req_length = REQUEST_ENTRY_CNT_24XX;
  1787. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1788. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1789. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1790. ha->gid_list_info_size = 8;
  1791. ha->optrom_size = OPTROM_SIZE_25XX;
  1792. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1793. ha->isp_ops = &qla25xx_isp_ops;
  1794. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1795. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1796. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1797. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1798. } else if (IS_QLA81XX(ha)) {
  1799. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1800. req_length = REQUEST_ENTRY_CNT_24XX;
  1801. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1802. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1803. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1804. ha->gid_list_info_size = 8;
  1805. ha->optrom_size = OPTROM_SIZE_81XX;
  1806. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1807. ha->isp_ops = &qla81xx_isp_ops;
  1808. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  1809. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  1810. ha->nvram_conf_off = ~0;
  1811. ha->nvram_data_off = ~0;
  1812. } else if (IS_QLA82XX(ha)) {
  1813. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1814. req_length = REQUEST_ENTRY_CNT_82XX;
  1815. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  1816. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1817. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1818. ha->gid_list_info_size = 8;
  1819. ha->optrom_size = OPTROM_SIZE_82XX;
  1820. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1821. ha->isp_ops = &qla82xx_isp_ops;
  1822. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1823. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1824. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1825. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1826. }
  1827. mutex_init(&ha->vport_lock);
  1828. init_completion(&ha->mbx_cmd_comp);
  1829. complete(&ha->mbx_cmd_comp);
  1830. init_completion(&ha->mbx_intr_comp);
  1831. init_completion(&ha->dcbx_comp);
  1832. set_bit(0, (unsigned long *) ha->vp_idx_map);
  1833. qla2x00_config_dma_addressing(ha);
  1834. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  1835. if (!ret) {
  1836. qla_printk(KERN_WARNING, ha,
  1837. "[ERROR] Failed to allocate memory for adapter\n");
  1838. goto probe_hw_failed;
  1839. }
  1840. req->max_q_depth = MAX_Q_DEPTH;
  1841. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  1842. req->max_q_depth = ql2xmaxqdepth;
  1843. base_vha = qla2x00_create_host(sht, ha);
  1844. if (!base_vha) {
  1845. qla_printk(KERN_WARNING, ha,
  1846. "[ERROR] Failed to allocate memory for scsi_host\n");
  1847. ret = -ENOMEM;
  1848. qla2x00_mem_free(ha);
  1849. qla2x00_free_req_que(ha, req);
  1850. qla2x00_free_rsp_que(ha, rsp);
  1851. goto probe_hw_failed;
  1852. }
  1853. pci_set_drvdata(pdev, base_vha);
  1854. host = base_vha->host;
  1855. base_vha->req = req;
  1856. host->can_queue = req->length + 128;
  1857. if (IS_QLA2XXX_MIDTYPE(ha))
  1858. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  1859. else
  1860. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  1861. base_vha->vp_idx;
  1862. /* Set the SG table size based on ISP type */
  1863. if (!IS_FWI2_CAPABLE(ha)) {
  1864. if (IS_QLA2100(ha))
  1865. host->sg_tablesize = 32;
  1866. } else {
  1867. if (!IS_QLA82XX(ha))
  1868. host->sg_tablesize = QLA_SG_ALL;
  1869. }
  1870. host->max_id = max_id;
  1871. host->this_id = 255;
  1872. host->cmd_per_lun = 3;
  1873. host->unique_id = host->host_no;
  1874. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
  1875. host->max_cmd_len = 32;
  1876. else
  1877. host->max_cmd_len = MAX_CMDSZ;
  1878. host->max_channel = MAX_BUSES - 1;
  1879. host->max_lun = MAX_LUNS;
  1880. host->transportt = qla2xxx_transport_template;
  1881. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  1882. /* Set up the irqs */
  1883. ret = qla2x00_request_irqs(ha, rsp);
  1884. if (ret)
  1885. goto probe_init_failed;
  1886. pci_save_state(pdev);
  1887. /* Alloc arrays of request and response ring ptrs */
  1888. que_init:
  1889. if (!qla2x00_alloc_queues(ha)) {
  1890. qla_printk(KERN_WARNING, ha,
  1891. "[ERROR] Failed to allocate memory for queue"
  1892. " pointers\n");
  1893. goto probe_init_failed;
  1894. }
  1895. ha->rsp_q_map[0] = rsp;
  1896. ha->req_q_map[0] = req;
  1897. rsp->req = req;
  1898. req->rsp = rsp;
  1899. set_bit(0, ha->req_qid_map);
  1900. set_bit(0, ha->rsp_qid_map);
  1901. /* FWI2-capable only. */
  1902. req->req_q_in = &ha->iobase->isp24.req_q_in;
  1903. req->req_q_out = &ha->iobase->isp24.req_q_out;
  1904. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  1905. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  1906. if (ha->mqenable) {
  1907. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  1908. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  1909. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  1910. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  1911. }
  1912. if (IS_QLA82XX(ha)) {
  1913. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  1914. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  1915. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  1916. }
  1917. if (qla2x00_initialize_adapter(base_vha)) {
  1918. qla_printk(KERN_WARNING, ha,
  1919. "Failed to initialize adapter\n");
  1920. DEBUG2(printk("scsi(%ld): Failed to initialize adapter - "
  1921. "Adapter flags %x.\n",
  1922. base_vha->host_no, base_vha->device_flags));
  1923. if (IS_QLA82XX(ha)) {
  1924. qla82xx_idc_lock(ha);
  1925. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  1926. QLA82XX_DEV_FAILED);
  1927. qla82xx_idc_unlock(ha);
  1928. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  1929. }
  1930. ret = -ENODEV;
  1931. goto probe_failed;
  1932. }
  1933. if (ha->mqenable) {
  1934. if (qla25xx_setup_mode(base_vha)) {
  1935. qla_printk(KERN_WARNING, ha,
  1936. "Can't create queues, falling back to single"
  1937. " queue mode\n");
  1938. goto que_init;
  1939. }
  1940. }
  1941. if (ha->flags.running_gold_fw)
  1942. goto skip_dpc;
  1943. /*
  1944. * Startup the kernel thread for this host adapter
  1945. */
  1946. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  1947. "%s_dpc", base_vha->host_str);
  1948. if (IS_ERR(ha->dpc_thread)) {
  1949. qla_printk(KERN_WARNING, ha,
  1950. "Unable to start DPC thread!\n");
  1951. ret = PTR_ERR(ha->dpc_thread);
  1952. goto probe_failed;
  1953. }
  1954. skip_dpc:
  1955. list_add_tail(&base_vha->list, &ha->vp_list);
  1956. base_vha->host->irq = ha->pdev->irq;
  1957. /* Initialized the timer */
  1958. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  1959. DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
  1960. base_vha->host_no, ha));
  1961. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
  1962. if (ha->fw_attributes & BIT_4) {
  1963. base_vha->flags.difdix_supported = 1;
  1964. DEBUG18(qla_printk(KERN_INFO, ha,
  1965. "Registering for DIF/DIX type 1 and 3"
  1966. " protection.\n"));
  1967. scsi_host_set_prot(host,
  1968. SHOST_DIF_TYPE1_PROTECTION
  1969. | SHOST_DIF_TYPE2_PROTECTION
  1970. | SHOST_DIF_TYPE3_PROTECTION
  1971. | SHOST_DIX_TYPE1_PROTECTION
  1972. | SHOST_DIX_TYPE2_PROTECTION
  1973. | SHOST_DIX_TYPE3_PROTECTION);
  1974. scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
  1975. } else
  1976. base_vha->flags.difdix_supported = 0;
  1977. }
  1978. ha->isp_ops->enable_intrs(ha);
  1979. ret = scsi_add_host(host, &pdev->dev);
  1980. if (ret)
  1981. goto probe_failed;
  1982. base_vha->flags.init_done = 1;
  1983. base_vha->flags.online = 1;
  1984. scsi_scan_host(host);
  1985. qla2x00_alloc_sysfs_attr(base_vha);
  1986. qla2x00_init_host_attr(base_vha);
  1987. qla2x00_dfs_setup(base_vha);
  1988. qla_printk(KERN_INFO, ha, "\n"
  1989. " QLogic Fibre Channel HBA Driver: %s\n"
  1990. " QLogic %s - %s\n"
  1991. " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n",
  1992. qla2x00_version_str, ha->model_number,
  1993. ha->model_desc ? ha->model_desc : "", pdev->device,
  1994. ha->isp_ops->pci_info_str(base_vha, pci_info), pci_name(pdev),
  1995. ha->flags.enable_64bit_addressing ? '+' : '-', base_vha->host_no,
  1996. ha->isp_ops->fw_version_str(base_vha, fw_str));
  1997. return 0;
  1998. probe_init_failed:
  1999. qla2x00_free_req_que(ha, req);
  2000. qla2x00_free_rsp_que(ha, rsp);
  2001. ha->max_req_queues = ha->max_rsp_queues = 0;
  2002. probe_failed:
  2003. if (base_vha->timer_active)
  2004. qla2x00_stop_timer(base_vha);
  2005. base_vha->flags.online = 0;
  2006. if (ha->dpc_thread) {
  2007. struct task_struct *t = ha->dpc_thread;
  2008. ha->dpc_thread = NULL;
  2009. kthread_stop(t);
  2010. }
  2011. qla2x00_free_device(base_vha);
  2012. scsi_host_put(base_vha->host);
  2013. probe_hw_failed:
  2014. if (IS_QLA82XX(ha)) {
  2015. qla82xx_idc_lock(ha);
  2016. qla82xx_clear_drv_active(ha);
  2017. qla82xx_idc_unlock(ha);
  2018. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2019. if (!ql2xdbwr)
  2020. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2021. } else {
  2022. if (ha->iobase)
  2023. iounmap(ha->iobase);
  2024. }
  2025. pci_release_selected_regions(ha->pdev, ha->bars);
  2026. kfree(ha);
  2027. ha = NULL;
  2028. probe_out:
  2029. pci_disable_device(pdev);
  2030. return ret;
  2031. }
  2032. static void
  2033. qla2x00_shutdown(struct pci_dev *pdev)
  2034. {
  2035. scsi_qla_host_t *vha;
  2036. struct qla_hw_data *ha;
  2037. vha = pci_get_drvdata(pdev);
  2038. ha = vha->hw;
  2039. /* Turn-off FCE trace */
  2040. if (ha->flags.fce_enabled) {
  2041. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2042. ha->flags.fce_enabled = 0;
  2043. }
  2044. /* Turn-off EFT trace */
  2045. if (ha->eft)
  2046. qla2x00_disable_eft_trace(vha);
  2047. /* Stop currently executing firmware. */
  2048. qla2x00_try_to_stop_firmware(vha);
  2049. /* Turn adapter off line */
  2050. vha->flags.online = 0;
  2051. /* turn-off interrupts on the card */
  2052. if (ha->interrupts_on) {
  2053. vha->flags.init_done = 0;
  2054. ha->isp_ops->disable_intrs(ha);
  2055. }
  2056. qla2x00_free_irqs(vha);
  2057. qla2x00_free_fw_dump(ha);
  2058. }
  2059. static void
  2060. qla2x00_remove_one(struct pci_dev *pdev)
  2061. {
  2062. scsi_qla_host_t *base_vha, *vha;
  2063. struct qla_hw_data *ha;
  2064. unsigned long flags;
  2065. base_vha = pci_get_drvdata(pdev);
  2066. ha = base_vha->hw;
  2067. spin_lock_irqsave(&ha->vport_slock, flags);
  2068. list_for_each_entry(vha, &ha->vp_list, list) {
  2069. atomic_inc(&vha->vref_count);
  2070. if (vha->fc_vport) {
  2071. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2072. fc_vport_terminate(vha->fc_vport);
  2073. spin_lock_irqsave(&ha->vport_slock, flags);
  2074. }
  2075. atomic_dec(&vha->vref_count);
  2076. }
  2077. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2078. set_bit(UNLOADING, &base_vha->dpc_flags);
  2079. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2080. qla2x00_dfs_remove(base_vha);
  2081. qla84xx_put_chip(base_vha);
  2082. /* Disable timer */
  2083. if (base_vha->timer_active)
  2084. qla2x00_stop_timer(base_vha);
  2085. base_vha->flags.online = 0;
  2086. /* Flush the work queue and remove it */
  2087. if (ha->wq) {
  2088. flush_workqueue(ha->wq);
  2089. destroy_workqueue(ha->wq);
  2090. ha->wq = NULL;
  2091. }
  2092. /* Kill the kernel thread for this host */
  2093. if (ha->dpc_thread) {
  2094. struct task_struct *t = ha->dpc_thread;
  2095. /*
  2096. * qla2xxx_wake_dpc checks for ->dpc_thread
  2097. * so we need to zero it out.
  2098. */
  2099. ha->dpc_thread = NULL;
  2100. kthread_stop(t);
  2101. }
  2102. qla2x00_free_sysfs_attr(base_vha);
  2103. fc_remove_host(base_vha->host);
  2104. scsi_remove_host(base_vha->host);
  2105. qla2x00_free_device(base_vha);
  2106. scsi_host_put(base_vha->host);
  2107. if (IS_QLA82XX(ha)) {
  2108. qla82xx_idc_lock(ha);
  2109. qla82xx_clear_drv_active(ha);
  2110. qla82xx_idc_unlock(ha);
  2111. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2112. if (!ql2xdbwr)
  2113. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2114. } else {
  2115. if (ha->iobase)
  2116. iounmap(ha->iobase);
  2117. if (ha->mqiobase)
  2118. iounmap(ha->mqiobase);
  2119. }
  2120. pci_release_selected_regions(ha->pdev, ha->bars);
  2121. kfree(ha);
  2122. ha = NULL;
  2123. pci_disable_pcie_error_reporting(pdev);
  2124. pci_disable_device(pdev);
  2125. pci_set_drvdata(pdev, NULL);
  2126. }
  2127. static void
  2128. qla2x00_free_device(scsi_qla_host_t *vha)
  2129. {
  2130. struct qla_hw_data *ha = vha->hw;
  2131. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2132. /* Disable timer */
  2133. if (vha->timer_active)
  2134. qla2x00_stop_timer(vha);
  2135. /* Kill the kernel thread for this host */
  2136. if (ha->dpc_thread) {
  2137. struct task_struct *t = ha->dpc_thread;
  2138. /*
  2139. * qla2xxx_wake_dpc checks for ->dpc_thread
  2140. * so we need to zero it out.
  2141. */
  2142. ha->dpc_thread = NULL;
  2143. kthread_stop(t);
  2144. }
  2145. qla25xx_delete_queues(vha);
  2146. if (ha->flags.fce_enabled)
  2147. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2148. if (ha->eft)
  2149. qla2x00_disable_eft_trace(vha);
  2150. /* Stop currently executing firmware. */
  2151. qla2x00_try_to_stop_firmware(vha);
  2152. vha->flags.online = 0;
  2153. /* turn-off interrupts on the card */
  2154. if (ha->interrupts_on) {
  2155. vha->flags.init_done = 0;
  2156. ha->isp_ops->disable_intrs(ha);
  2157. }
  2158. qla2x00_free_irqs(vha);
  2159. qla2x00_free_fcports(vha);
  2160. qla2x00_mem_free(ha);
  2161. qla2x00_free_queues(ha);
  2162. }
  2163. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2164. {
  2165. fc_port_t *fcport, *tfcport;
  2166. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2167. list_del(&fcport->list);
  2168. kfree(fcport);
  2169. fcport = NULL;
  2170. }
  2171. }
  2172. static inline void
  2173. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2174. int defer)
  2175. {
  2176. struct fc_rport *rport;
  2177. scsi_qla_host_t *base_vha;
  2178. unsigned long flags;
  2179. if (!fcport->rport)
  2180. return;
  2181. rport = fcport->rport;
  2182. if (defer) {
  2183. base_vha = pci_get_drvdata(vha->hw->pdev);
  2184. spin_lock_irqsave(vha->host->host_lock, flags);
  2185. fcport->drport = rport;
  2186. spin_unlock_irqrestore(vha->host->host_lock, flags);
  2187. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2188. qla2xxx_wake_dpc(base_vha);
  2189. } else
  2190. fc_remote_port_delete(rport);
  2191. }
  2192. /*
  2193. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2194. *
  2195. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2196. *
  2197. * Return: None.
  2198. *
  2199. * Context:
  2200. */
  2201. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2202. int do_login, int defer)
  2203. {
  2204. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2205. vha->vp_idx == fcport->vp_idx) {
  2206. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2207. qla2x00_schedule_rport_del(vha, fcport, defer);
  2208. }
  2209. /*
  2210. * We may need to retry the login, so don't change the state of the
  2211. * port but do the retries.
  2212. */
  2213. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2214. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2215. if (!do_login)
  2216. return;
  2217. if (fcport->login_retry == 0) {
  2218. fcport->login_retry = vha->hw->login_retry_count;
  2219. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2220. DEBUG(printk("scsi(%ld): Port login retry: "
  2221. "%02x%02x%02x%02x%02x%02x%02x%02x, "
  2222. "id = 0x%04x retry cnt=%d\n",
  2223. vha->host_no,
  2224. fcport->port_name[0],
  2225. fcport->port_name[1],
  2226. fcport->port_name[2],
  2227. fcport->port_name[3],
  2228. fcport->port_name[4],
  2229. fcport->port_name[5],
  2230. fcport->port_name[6],
  2231. fcport->port_name[7],
  2232. fcport->loop_id,
  2233. fcport->login_retry));
  2234. }
  2235. }
  2236. /*
  2237. * qla2x00_mark_all_devices_lost
  2238. * Updates fcport state when device goes offline.
  2239. *
  2240. * Input:
  2241. * ha = adapter block pointer.
  2242. * fcport = port structure pointer.
  2243. *
  2244. * Return:
  2245. * None.
  2246. *
  2247. * Context:
  2248. */
  2249. void
  2250. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  2251. {
  2252. fc_port_t *fcport;
  2253. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2254. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
  2255. continue;
  2256. /*
  2257. * No point in marking the device as lost, if the device is
  2258. * already DEAD.
  2259. */
  2260. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  2261. continue;
  2262. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2263. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2264. if (defer)
  2265. qla2x00_schedule_rport_del(vha, fcport, defer);
  2266. else if (vha->vp_idx == fcport->vp_idx)
  2267. qla2x00_schedule_rport_del(vha, fcport, defer);
  2268. }
  2269. }
  2270. }
  2271. /*
  2272. * qla2x00_mem_alloc
  2273. * Allocates adapter memory.
  2274. *
  2275. * Returns:
  2276. * 0 = success.
  2277. * !0 = failure.
  2278. */
  2279. static int
  2280. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  2281. struct req_que **req, struct rsp_que **rsp)
  2282. {
  2283. char name[16];
  2284. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  2285. &ha->init_cb_dma, GFP_KERNEL);
  2286. if (!ha->init_cb)
  2287. goto fail;
  2288. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
  2289. &ha->gid_list_dma, GFP_KERNEL);
  2290. if (!ha->gid_list)
  2291. goto fail_free_init_cb;
  2292. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  2293. if (!ha->srb_mempool)
  2294. goto fail_free_gid_list;
  2295. if (IS_QLA82XX(ha)) {
  2296. /* Allocate cache for CT6 Ctx. */
  2297. if (!ctx_cachep) {
  2298. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  2299. sizeof(struct ct6_dsd), 0,
  2300. SLAB_HWCACHE_ALIGN, NULL);
  2301. if (!ctx_cachep)
  2302. goto fail_free_gid_list;
  2303. }
  2304. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  2305. ctx_cachep);
  2306. if (!ha->ctx_mempool)
  2307. goto fail_free_srb_mempool;
  2308. }
  2309. /* Get memory for cached NVRAM */
  2310. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  2311. if (!ha->nvram)
  2312. goto fail_free_ctx_mempool;
  2313. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  2314. ha->pdev->device);
  2315. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2316. DMA_POOL_SIZE, 8, 0);
  2317. if (!ha->s_dma_pool)
  2318. goto fail_free_nvram;
  2319. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2320. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2321. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  2322. if (!ha->dl_dma_pool) {
  2323. qla_printk(KERN_WARNING, ha,
  2324. "Memory Allocation failed - dl_dma_pool\n");
  2325. goto fail_s_dma_pool;
  2326. }
  2327. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2328. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  2329. if (!ha->fcp_cmnd_dma_pool) {
  2330. qla_printk(KERN_WARNING, ha,
  2331. "Memory Allocation failed - fcp_cmnd_dma_pool\n");
  2332. goto fail_dl_dma_pool;
  2333. }
  2334. }
  2335. /* Allocate memory for SNS commands */
  2336. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2337. /* Get consistent memory allocated for SNS commands */
  2338. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  2339. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  2340. if (!ha->sns_cmd)
  2341. goto fail_dma_pool;
  2342. } else {
  2343. /* Get consistent memory allocated for MS IOCB */
  2344. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2345. &ha->ms_iocb_dma);
  2346. if (!ha->ms_iocb)
  2347. goto fail_dma_pool;
  2348. /* Get consistent memory allocated for CT SNS commands */
  2349. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  2350. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  2351. if (!ha->ct_sns)
  2352. goto fail_free_ms_iocb;
  2353. }
  2354. /* Allocate memory for request ring */
  2355. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  2356. if (!*req) {
  2357. DEBUG(printk("Unable to allocate memory for req\n"));
  2358. goto fail_req;
  2359. }
  2360. (*req)->length = req_len;
  2361. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2362. ((*req)->length + 1) * sizeof(request_t),
  2363. &(*req)->dma, GFP_KERNEL);
  2364. if (!(*req)->ring) {
  2365. DEBUG(printk("Unable to allocate memory for req_ring\n"));
  2366. goto fail_req_ring;
  2367. }
  2368. /* Allocate memory for response ring */
  2369. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  2370. if (!*rsp) {
  2371. qla_printk(KERN_WARNING, ha,
  2372. "Unable to allocate memory for rsp\n");
  2373. goto fail_rsp;
  2374. }
  2375. (*rsp)->hw = ha;
  2376. (*rsp)->length = rsp_len;
  2377. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2378. ((*rsp)->length + 1) * sizeof(response_t),
  2379. &(*rsp)->dma, GFP_KERNEL);
  2380. if (!(*rsp)->ring) {
  2381. qla_printk(KERN_WARNING, ha,
  2382. "Unable to allocate memory for rsp_ring\n");
  2383. goto fail_rsp_ring;
  2384. }
  2385. (*req)->rsp = *rsp;
  2386. (*rsp)->req = *req;
  2387. /* Allocate memory for NVRAM data for vports */
  2388. if (ha->nvram_npiv_size) {
  2389. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  2390. ha->nvram_npiv_size, GFP_KERNEL);
  2391. if (!ha->npiv_info) {
  2392. qla_printk(KERN_WARNING, ha,
  2393. "Unable to allocate memory for npiv info\n");
  2394. goto fail_npiv_info;
  2395. }
  2396. } else
  2397. ha->npiv_info = NULL;
  2398. /* Get consistent memory allocated for EX-INIT-CB. */
  2399. if (IS_QLA8XXX_TYPE(ha)) {
  2400. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2401. &ha->ex_init_cb_dma);
  2402. if (!ha->ex_init_cb)
  2403. goto fail_ex_init_cb;
  2404. }
  2405. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  2406. /* Get consistent memory allocated for Async Port-Database. */
  2407. if (!IS_FWI2_CAPABLE(ha)) {
  2408. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2409. &ha->async_pd_dma);
  2410. if (!ha->async_pd)
  2411. goto fail_async_pd;
  2412. }
  2413. INIT_LIST_HEAD(&ha->vp_list);
  2414. return 1;
  2415. fail_async_pd:
  2416. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  2417. fail_ex_init_cb:
  2418. kfree(ha->npiv_info);
  2419. fail_npiv_info:
  2420. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  2421. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  2422. (*rsp)->ring = NULL;
  2423. (*rsp)->dma = 0;
  2424. fail_rsp_ring:
  2425. kfree(*rsp);
  2426. fail_rsp:
  2427. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  2428. sizeof(request_t), (*req)->ring, (*req)->dma);
  2429. (*req)->ring = NULL;
  2430. (*req)->dma = 0;
  2431. fail_req_ring:
  2432. kfree(*req);
  2433. fail_req:
  2434. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2435. ha->ct_sns, ha->ct_sns_dma);
  2436. ha->ct_sns = NULL;
  2437. ha->ct_sns_dma = 0;
  2438. fail_free_ms_iocb:
  2439. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2440. ha->ms_iocb = NULL;
  2441. ha->ms_iocb_dma = 0;
  2442. fail_dma_pool:
  2443. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2444. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2445. ha->fcp_cmnd_dma_pool = NULL;
  2446. }
  2447. fail_dl_dma_pool:
  2448. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2449. dma_pool_destroy(ha->dl_dma_pool);
  2450. ha->dl_dma_pool = NULL;
  2451. }
  2452. fail_s_dma_pool:
  2453. dma_pool_destroy(ha->s_dma_pool);
  2454. ha->s_dma_pool = NULL;
  2455. fail_free_nvram:
  2456. kfree(ha->nvram);
  2457. ha->nvram = NULL;
  2458. fail_free_ctx_mempool:
  2459. mempool_destroy(ha->ctx_mempool);
  2460. ha->ctx_mempool = NULL;
  2461. fail_free_srb_mempool:
  2462. mempool_destroy(ha->srb_mempool);
  2463. ha->srb_mempool = NULL;
  2464. fail_free_gid_list:
  2465. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2466. ha->gid_list_dma);
  2467. ha->gid_list = NULL;
  2468. ha->gid_list_dma = 0;
  2469. fail_free_init_cb:
  2470. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  2471. ha->init_cb_dma);
  2472. ha->init_cb = NULL;
  2473. ha->init_cb_dma = 0;
  2474. fail:
  2475. DEBUG(printk("%s: Memory allocation failure\n", __func__));
  2476. return -ENOMEM;
  2477. }
  2478. /*
  2479. * qla2x00_free_fw_dump
  2480. * Frees fw dump stuff.
  2481. *
  2482. * Input:
  2483. * ha = adapter block pointer.
  2484. */
  2485. static void
  2486. qla2x00_free_fw_dump(struct qla_hw_data *ha)
  2487. {
  2488. if (ha->fce)
  2489. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  2490. ha->fce_dma);
  2491. if (ha->fw_dump) {
  2492. if (ha->eft)
  2493. dma_free_coherent(&ha->pdev->dev,
  2494. ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
  2495. vfree(ha->fw_dump);
  2496. }
  2497. ha->fce = NULL;
  2498. ha->fce_dma = 0;
  2499. ha->eft = NULL;
  2500. ha->eft_dma = 0;
  2501. ha->fw_dump = NULL;
  2502. ha->fw_dumped = 0;
  2503. ha->fw_dump_reading = 0;
  2504. }
  2505. /*
  2506. * qla2x00_mem_free
  2507. * Frees all adapter allocated memory.
  2508. *
  2509. * Input:
  2510. * ha = adapter block pointer.
  2511. */
  2512. static void
  2513. qla2x00_mem_free(struct qla_hw_data *ha)
  2514. {
  2515. qla2x00_free_fw_dump(ha);
  2516. if (ha->srb_mempool)
  2517. mempool_destroy(ha->srb_mempool);
  2518. if (ha->dcbx_tlv)
  2519. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  2520. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  2521. if (ha->xgmac_data)
  2522. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  2523. ha->xgmac_data, ha->xgmac_data_dma);
  2524. if (ha->sns_cmd)
  2525. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  2526. ha->sns_cmd, ha->sns_cmd_dma);
  2527. if (ha->ct_sns)
  2528. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2529. ha->ct_sns, ha->ct_sns_dma);
  2530. if (ha->sfp_data)
  2531. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  2532. if (ha->edc_data)
  2533. dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
  2534. if (ha->ms_iocb)
  2535. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2536. if (ha->ex_init_cb)
  2537. dma_pool_free(ha->s_dma_pool,
  2538. ha->ex_init_cb, ha->ex_init_cb_dma);
  2539. if (ha->async_pd)
  2540. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  2541. if (ha->s_dma_pool)
  2542. dma_pool_destroy(ha->s_dma_pool);
  2543. if (ha->gid_list)
  2544. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2545. ha->gid_list_dma);
  2546. if (IS_QLA82XX(ha)) {
  2547. if (!list_empty(&ha->gbl_dsd_list)) {
  2548. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  2549. /* clean up allocated prev pool */
  2550. list_for_each_entry_safe(dsd_ptr,
  2551. tdsd_ptr, &ha->gbl_dsd_list, list) {
  2552. dma_pool_free(ha->dl_dma_pool,
  2553. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  2554. list_del(&dsd_ptr->list);
  2555. kfree(dsd_ptr);
  2556. }
  2557. }
  2558. }
  2559. if (ha->dl_dma_pool)
  2560. dma_pool_destroy(ha->dl_dma_pool);
  2561. if (ha->fcp_cmnd_dma_pool)
  2562. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2563. if (ha->ctx_mempool)
  2564. mempool_destroy(ha->ctx_mempool);
  2565. if (ha->init_cb)
  2566. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  2567. ha->init_cb, ha->init_cb_dma);
  2568. vfree(ha->optrom_buffer);
  2569. kfree(ha->nvram);
  2570. kfree(ha->npiv_info);
  2571. ha->srb_mempool = NULL;
  2572. ha->ctx_mempool = NULL;
  2573. ha->sns_cmd = NULL;
  2574. ha->sns_cmd_dma = 0;
  2575. ha->ct_sns = NULL;
  2576. ha->ct_sns_dma = 0;
  2577. ha->ms_iocb = NULL;
  2578. ha->ms_iocb_dma = 0;
  2579. ha->init_cb = NULL;
  2580. ha->init_cb_dma = 0;
  2581. ha->ex_init_cb = NULL;
  2582. ha->ex_init_cb_dma = 0;
  2583. ha->async_pd = NULL;
  2584. ha->async_pd_dma = 0;
  2585. ha->s_dma_pool = NULL;
  2586. ha->dl_dma_pool = NULL;
  2587. ha->fcp_cmnd_dma_pool = NULL;
  2588. ha->gid_list = NULL;
  2589. ha->gid_list_dma = 0;
  2590. }
  2591. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  2592. struct qla_hw_data *ha)
  2593. {
  2594. struct Scsi_Host *host;
  2595. struct scsi_qla_host *vha = NULL;
  2596. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  2597. if (host == NULL) {
  2598. printk(KERN_WARNING
  2599. "qla2xxx: Couldn't allocate host from scsi layer!\n");
  2600. goto fail;
  2601. }
  2602. /* Clear our data area */
  2603. vha = shost_priv(host);
  2604. memset(vha, 0, sizeof(scsi_qla_host_t));
  2605. vha->host = host;
  2606. vha->host_no = host->host_no;
  2607. vha->hw = ha;
  2608. INIT_LIST_HEAD(&vha->vp_fcports);
  2609. INIT_LIST_HEAD(&vha->work_list);
  2610. INIT_LIST_HEAD(&vha->list);
  2611. spin_lock_init(&vha->work_lock);
  2612. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  2613. return vha;
  2614. fail:
  2615. return vha;
  2616. }
  2617. static struct qla_work_evt *
  2618. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  2619. {
  2620. struct qla_work_evt *e;
  2621. uint8_t bail;
  2622. QLA_VHA_MARK_BUSY(vha, bail);
  2623. if (bail)
  2624. return NULL;
  2625. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  2626. if (!e) {
  2627. QLA_VHA_MARK_NOT_BUSY(vha);
  2628. return NULL;
  2629. }
  2630. INIT_LIST_HEAD(&e->list);
  2631. e->type = type;
  2632. e->flags = QLA_EVT_FLAG_FREE;
  2633. return e;
  2634. }
  2635. static int
  2636. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  2637. {
  2638. unsigned long flags;
  2639. spin_lock_irqsave(&vha->work_lock, flags);
  2640. list_add_tail(&e->list, &vha->work_list);
  2641. spin_unlock_irqrestore(&vha->work_lock, flags);
  2642. qla2xxx_wake_dpc(vha);
  2643. return QLA_SUCCESS;
  2644. }
  2645. int
  2646. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  2647. u32 data)
  2648. {
  2649. struct qla_work_evt *e;
  2650. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  2651. if (!e)
  2652. return QLA_FUNCTION_FAILED;
  2653. e->u.aen.code = code;
  2654. e->u.aen.data = data;
  2655. return qla2x00_post_work(vha, e);
  2656. }
  2657. int
  2658. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  2659. {
  2660. struct qla_work_evt *e;
  2661. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  2662. if (!e)
  2663. return QLA_FUNCTION_FAILED;
  2664. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2665. return qla2x00_post_work(vha, e);
  2666. }
  2667. #define qla2x00_post_async_work(name, type) \
  2668. int qla2x00_post_async_##name##_work( \
  2669. struct scsi_qla_host *vha, \
  2670. fc_port_t *fcport, uint16_t *data) \
  2671. { \
  2672. struct qla_work_evt *e; \
  2673. \
  2674. e = qla2x00_alloc_work(vha, type); \
  2675. if (!e) \
  2676. return QLA_FUNCTION_FAILED; \
  2677. \
  2678. e->u.logio.fcport = fcport; \
  2679. if (data) { \
  2680. e->u.logio.data[0] = data[0]; \
  2681. e->u.logio.data[1] = data[1]; \
  2682. } \
  2683. return qla2x00_post_work(vha, e); \
  2684. }
  2685. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  2686. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  2687. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  2688. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  2689. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  2690. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  2691. int
  2692. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  2693. {
  2694. struct qla_work_evt *e;
  2695. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  2696. if (!e)
  2697. return QLA_FUNCTION_FAILED;
  2698. e->u.uevent.code = code;
  2699. return qla2x00_post_work(vha, e);
  2700. }
  2701. static void
  2702. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  2703. {
  2704. char event_string[40];
  2705. char *envp[] = { event_string, NULL };
  2706. switch (code) {
  2707. case QLA_UEVENT_CODE_FW_DUMP:
  2708. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  2709. vha->host_no);
  2710. break;
  2711. default:
  2712. /* do nothing */
  2713. break;
  2714. }
  2715. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  2716. }
  2717. void
  2718. qla2x00_do_work(struct scsi_qla_host *vha)
  2719. {
  2720. struct qla_work_evt *e, *tmp;
  2721. unsigned long flags;
  2722. LIST_HEAD(work);
  2723. spin_lock_irqsave(&vha->work_lock, flags);
  2724. list_splice_init(&vha->work_list, &work);
  2725. spin_unlock_irqrestore(&vha->work_lock, flags);
  2726. list_for_each_entry_safe(e, tmp, &work, list) {
  2727. list_del_init(&e->list);
  2728. switch (e->type) {
  2729. case QLA_EVT_AEN:
  2730. fc_host_post_event(vha->host, fc_get_event_number(),
  2731. e->u.aen.code, e->u.aen.data);
  2732. break;
  2733. case QLA_EVT_IDC_ACK:
  2734. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  2735. break;
  2736. case QLA_EVT_ASYNC_LOGIN:
  2737. qla2x00_async_login(vha, e->u.logio.fcport,
  2738. e->u.logio.data);
  2739. break;
  2740. case QLA_EVT_ASYNC_LOGIN_DONE:
  2741. qla2x00_async_login_done(vha, e->u.logio.fcport,
  2742. e->u.logio.data);
  2743. break;
  2744. case QLA_EVT_ASYNC_LOGOUT:
  2745. qla2x00_async_logout(vha, e->u.logio.fcport);
  2746. break;
  2747. case QLA_EVT_ASYNC_LOGOUT_DONE:
  2748. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  2749. e->u.logio.data);
  2750. break;
  2751. case QLA_EVT_ASYNC_ADISC:
  2752. qla2x00_async_adisc(vha, e->u.logio.fcport,
  2753. e->u.logio.data);
  2754. break;
  2755. case QLA_EVT_ASYNC_ADISC_DONE:
  2756. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  2757. e->u.logio.data);
  2758. break;
  2759. case QLA_EVT_UEVENT:
  2760. qla2x00_uevent_emit(vha, e->u.uevent.code);
  2761. break;
  2762. }
  2763. if (e->flags & QLA_EVT_FLAG_FREE)
  2764. kfree(e);
  2765. /* For each work completed decrement vha ref count */
  2766. QLA_VHA_MARK_NOT_BUSY(vha);
  2767. }
  2768. }
  2769. /* Relogins all the fcports of a vport
  2770. * Context: dpc thread
  2771. */
  2772. void qla2x00_relogin(struct scsi_qla_host *vha)
  2773. {
  2774. fc_port_t *fcport;
  2775. int status;
  2776. uint16_t next_loopid = 0;
  2777. struct qla_hw_data *ha = vha->hw;
  2778. uint16_t data[2];
  2779. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2780. /*
  2781. * If the port is not ONLINE then try to login
  2782. * to it if we haven't run out of retries.
  2783. */
  2784. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  2785. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  2786. fcport->login_retry--;
  2787. if (fcport->flags & FCF_FABRIC_DEVICE) {
  2788. if (fcport->flags & FCF_FCP2_DEVICE)
  2789. ha->isp_ops->fabric_logout(vha,
  2790. fcport->loop_id,
  2791. fcport->d_id.b.domain,
  2792. fcport->d_id.b.area,
  2793. fcport->d_id.b.al_pa);
  2794. if (IS_ALOGIO_CAPABLE(ha)) {
  2795. fcport->flags |= FCF_ASYNC_SENT;
  2796. data[0] = 0;
  2797. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  2798. status = qla2x00_post_async_login_work(
  2799. vha, fcport, data);
  2800. if (status == QLA_SUCCESS)
  2801. continue;
  2802. /* Attempt a retry. */
  2803. status = 1;
  2804. } else
  2805. status = qla2x00_fabric_login(vha,
  2806. fcport, &next_loopid);
  2807. } else
  2808. status = qla2x00_local_device_login(vha,
  2809. fcport);
  2810. if (status == QLA_SUCCESS) {
  2811. fcport->old_loop_id = fcport->loop_id;
  2812. DEBUG(printk("scsi(%ld): port login OK: logged "
  2813. "in ID 0x%x\n", vha->host_no, fcport->loop_id));
  2814. qla2x00_update_fcport(vha, fcport);
  2815. } else if (status == 1) {
  2816. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2817. /* retry the login again */
  2818. DEBUG(printk("scsi(%ld): Retrying"
  2819. " %d login again loop_id 0x%x\n",
  2820. vha->host_no, fcport->login_retry,
  2821. fcport->loop_id));
  2822. } else {
  2823. fcport->login_retry = 0;
  2824. }
  2825. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  2826. fcport->loop_id = FC_NO_LOOP_ID;
  2827. }
  2828. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2829. break;
  2830. }
  2831. }
  2832. /**************************************************************************
  2833. * qla2x00_do_dpc
  2834. * This kernel thread is a task that is schedule by the interrupt handler
  2835. * to perform the background processing for interrupts.
  2836. *
  2837. * Notes:
  2838. * This task always run in the context of a kernel thread. It
  2839. * is kick-off by the driver's detect code and starts up
  2840. * up one per adapter. It immediately goes to sleep and waits for
  2841. * some fibre event. When either the interrupt handler or
  2842. * the timer routine detects a event it will one of the task
  2843. * bits then wake us up.
  2844. **************************************************************************/
  2845. static int
  2846. qla2x00_do_dpc(void *data)
  2847. {
  2848. int rval;
  2849. scsi_qla_host_t *base_vha;
  2850. struct qla_hw_data *ha;
  2851. ha = (struct qla_hw_data *)data;
  2852. base_vha = pci_get_drvdata(ha->pdev);
  2853. set_user_nice(current, -20);
  2854. set_current_state(TASK_INTERRUPTIBLE);
  2855. while (!kthread_should_stop()) {
  2856. DEBUG3(printk("qla2x00: DPC handler sleeping\n"));
  2857. schedule();
  2858. __set_current_state(TASK_RUNNING);
  2859. DEBUG3(printk("qla2x00: DPC handler waking up\n"));
  2860. /* Initialization not yet finished. Don't do anything yet. */
  2861. if (!base_vha->flags.init_done)
  2862. continue;
  2863. if (ha->flags.eeh_busy) {
  2864. DEBUG17(qla_printk(KERN_WARNING, ha,
  2865. "qla2x00_do_dpc: dpc_flags: %lx\n",
  2866. base_vha->dpc_flags));
  2867. continue;
  2868. }
  2869. DEBUG3(printk("scsi(%ld): DPC handler\n", base_vha->host_no));
  2870. ha->dpc_active = 1;
  2871. if (ha->flags.mbox_busy) {
  2872. ha->dpc_active = 0;
  2873. continue;
  2874. }
  2875. qla2x00_do_work(base_vha);
  2876. if (IS_QLA82XX(ha)) {
  2877. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  2878. &base_vha->dpc_flags)) {
  2879. qla82xx_idc_lock(ha);
  2880. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2881. QLA82XX_DEV_FAILED);
  2882. qla82xx_idc_unlock(ha);
  2883. qla_printk(KERN_INFO, ha,
  2884. "HW State: FAILED\n");
  2885. qla82xx_device_state_handler(base_vha);
  2886. continue;
  2887. }
  2888. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  2889. &base_vha->dpc_flags)) {
  2890. DEBUG(printk(KERN_INFO
  2891. "scsi(%ld): dpc: sched "
  2892. "qla82xx_fcoe_ctx_reset ha = %p\n",
  2893. base_vha->host_no, ha));
  2894. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2895. &base_vha->dpc_flags))) {
  2896. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  2897. /* FCoE-ctx reset failed.
  2898. * Escalate to chip-reset
  2899. */
  2900. set_bit(ISP_ABORT_NEEDED,
  2901. &base_vha->dpc_flags);
  2902. }
  2903. clear_bit(ABORT_ISP_ACTIVE,
  2904. &base_vha->dpc_flags);
  2905. }
  2906. DEBUG(printk("scsi(%ld): dpc:"
  2907. " qla82xx_fcoe_ctx_reset end\n",
  2908. base_vha->host_no));
  2909. }
  2910. }
  2911. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  2912. &base_vha->dpc_flags)) {
  2913. DEBUG(printk("scsi(%ld): dpc: sched "
  2914. "qla2x00_abort_isp ha = %p\n",
  2915. base_vha->host_no, ha));
  2916. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2917. &base_vha->dpc_flags))) {
  2918. if (ha->isp_ops->abort_isp(base_vha)) {
  2919. /* failed. retry later */
  2920. set_bit(ISP_ABORT_NEEDED,
  2921. &base_vha->dpc_flags);
  2922. }
  2923. clear_bit(ABORT_ISP_ACTIVE,
  2924. &base_vha->dpc_flags);
  2925. }
  2926. DEBUG(printk("scsi(%ld): dpc: qla2x00_abort_isp end\n",
  2927. base_vha->host_no));
  2928. }
  2929. if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
  2930. qla2x00_update_fcports(base_vha);
  2931. clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2932. }
  2933. if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
  2934. DEBUG(printk(KERN_INFO "scsi(%ld): dpc: sched "
  2935. "qla2x00_quiesce_needed ha = %p\n",
  2936. base_vha->host_no, ha));
  2937. qla82xx_device_state_handler(base_vha);
  2938. clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
  2939. if (!ha->flags.quiesce_owner) {
  2940. qla2x00_perform_loop_resync(base_vha);
  2941. qla82xx_idc_lock(ha);
  2942. qla82xx_clear_qsnt_ready(base_vha);
  2943. qla82xx_idc_unlock(ha);
  2944. }
  2945. }
  2946. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  2947. &base_vha->dpc_flags) &&
  2948. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  2949. DEBUG(printk("scsi(%ld): qla2x00_reset_marker()\n",
  2950. base_vha->host_no));
  2951. qla2x00_rst_aen(base_vha);
  2952. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  2953. }
  2954. /* Retry each device up to login retry count */
  2955. if ((test_and_clear_bit(RELOGIN_NEEDED,
  2956. &base_vha->dpc_flags)) &&
  2957. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  2958. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  2959. DEBUG(printk("scsi(%ld): qla2x00_port_login()\n",
  2960. base_vha->host_no));
  2961. qla2x00_relogin(base_vha);
  2962. DEBUG(printk("scsi(%ld): qla2x00_port_login - end\n",
  2963. base_vha->host_no));
  2964. }
  2965. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  2966. &base_vha->dpc_flags)) {
  2967. DEBUG(printk("scsi(%ld): qla2x00_loop_resync()\n",
  2968. base_vha->host_no));
  2969. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  2970. &base_vha->dpc_flags))) {
  2971. rval = qla2x00_loop_resync(base_vha);
  2972. clear_bit(LOOP_RESYNC_ACTIVE,
  2973. &base_vha->dpc_flags);
  2974. }
  2975. DEBUG(printk("scsi(%ld): qla2x00_loop_resync - end\n",
  2976. base_vha->host_no));
  2977. }
  2978. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  2979. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  2980. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  2981. qla2xxx_flash_npiv_conf(base_vha);
  2982. }
  2983. if (!ha->interrupts_on)
  2984. ha->isp_ops->enable_intrs(ha);
  2985. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  2986. &base_vha->dpc_flags))
  2987. ha->isp_ops->beacon_blink(base_vha);
  2988. qla2x00_do_dpc_all_vps(base_vha);
  2989. ha->dpc_active = 0;
  2990. set_current_state(TASK_INTERRUPTIBLE);
  2991. } /* End of while(1) */
  2992. __set_current_state(TASK_RUNNING);
  2993. DEBUG(printk("scsi(%ld): DPC handler exiting\n", base_vha->host_no));
  2994. /*
  2995. * Make sure that nobody tries to wake us up again.
  2996. */
  2997. ha->dpc_active = 0;
  2998. /* Cleanup any residual CTX SRBs. */
  2999. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  3000. return 0;
  3001. }
  3002. void
  3003. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  3004. {
  3005. struct qla_hw_data *ha = vha->hw;
  3006. struct task_struct *t = ha->dpc_thread;
  3007. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  3008. wake_up_process(t);
  3009. }
  3010. /*
  3011. * qla2x00_rst_aen
  3012. * Processes asynchronous reset.
  3013. *
  3014. * Input:
  3015. * ha = adapter block pointer.
  3016. */
  3017. static void
  3018. qla2x00_rst_aen(scsi_qla_host_t *vha)
  3019. {
  3020. if (vha->flags.online && !vha->flags.reset_active &&
  3021. !atomic_read(&vha->loop_down_timer) &&
  3022. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  3023. do {
  3024. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3025. /*
  3026. * Issue marker command only when we are going to start
  3027. * the I/O.
  3028. */
  3029. vha->marker_needed = 1;
  3030. } while (!atomic_read(&vha->loop_down_timer) &&
  3031. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  3032. }
  3033. }
  3034. static void
  3035. qla2x00_sp_free_dma(srb_t *sp)
  3036. {
  3037. struct scsi_cmnd *cmd = sp->cmd;
  3038. struct qla_hw_data *ha = sp->fcport->vha->hw;
  3039. if (sp->flags & SRB_DMA_VALID) {
  3040. scsi_dma_unmap(cmd);
  3041. sp->flags &= ~SRB_DMA_VALID;
  3042. }
  3043. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  3044. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  3045. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  3046. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  3047. }
  3048. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  3049. /* List assured to be having elements */
  3050. qla2x00_clean_dsd_pool(ha, sp);
  3051. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  3052. }
  3053. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  3054. dma_pool_free(ha->dl_dma_pool, sp->ctx,
  3055. ((struct crc_context *)sp->ctx)->crc_ctx_dma);
  3056. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  3057. }
  3058. CMD_SP(cmd) = NULL;
  3059. }
  3060. static void
  3061. qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
  3062. {
  3063. struct scsi_cmnd *cmd = sp->cmd;
  3064. qla2x00_sp_free_dma(sp);
  3065. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  3066. struct ct6_dsd *ctx = sp->ctx;
  3067. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
  3068. ctx->fcp_cmnd_dma);
  3069. list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
  3070. ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
  3071. ha->gbl_dsd_avail += ctx->dsd_use_cnt;
  3072. mempool_free(sp->ctx, ha->ctx_mempool);
  3073. sp->ctx = NULL;
  3074. }
  3075. mempool_free(sp, ha->srb_mempool);
  3076. cmd->scsi_done(cmd);
  3077. }
  3078. void
  3079. qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
  3080. {
  3081. if (atomic_read(&sp->ref_count) == 0) {
  3082. DEBUG2(qla_printk(KERN_WARNING, ha,
  3083. "SP reference-count to ZERO -- sp=%p\n", sp));
  3084. DEBUG2(BUG());
  3085. return;
  3086. }
  3087. if (!atomic_dec_and_test(&sp->ref_count))
  3088. return;
  3089. qla2x00_sp_final_compl(ha, sp);
  3090. }
  3091. /**************************************************************************
  3092. * qla2x00_timer
  3093. *
  3094. * Description:
  3095. * One second timer
  3096. *
  3097. * Context: Interrupt
  3098. ***************************************************************************/
  3099. void
  3100. qla2x00_timer(scsi_qla_host_t *vha)
  3101. {
  3102. unsigned long cpu_flags = 0;
  3103. int start_dpc = 0;
  3104. int index;
  3105. srb_t *sp;
  3106. uint16_t w;
  3107. struct qla_hw_data *ha = vha->hw;
  3108. struct req_que *req;
  3109. if (ha->flags.eeh_busy) {
  3110. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3111. return;
  3112. }
  3113. /* Hardware read to raise pending EEH errors during mailbox waits. */
  3114. if (!pci_channel_offline(ha->pdev))
  3115. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  3116. if (IS_QLA82XX(ha)) {
  3117. if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
  3118. start_dpc++;
  3119. qla82xx_watchdog(vha);
  3120. }
  3121. /* Loop down handler. */
  3122. if (atomic_read(&vha->loop_down_timer) > 0 &&
  3123. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
  3124. && vha->flags.online) {
  3125. if (atomic_read(&vha->loop_down_timer) ==
  3126. vha->loop_down_abort_time) {
  3127. DEBUG(printk("scsi(%ld): Loop Down - aborting the "
  3128. "queues before time expire\n",
  3129. vha->host_no));
  3130. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  3131. atomic_set(&vha->loop_state, LOOP_DEAD);
  3132. /*
  3133. * Schedule an ISP abort to return any FCP2-device
  3134. * commands.
  3135. */
  3136. /* NPIV - scan physical port only */
  3137. if (!vha->vp_idx) {
  3138. spin_lock_irqsave(&ha->hardware_lock,
  3139. cpu_flags);
  3140. req = ha->req_q_map[0];
  3141. for (index = 1;
  3142. index < MAX_OUTSTANDING_COMMANDS;
  3143. index++) {
  3144. fc_port_t *sfcp;
  3145. sp = req->outstanding_cmds[index];
  3146. if (!sp)
  3147. continue;
  3148. if (sp->ctx && !IS_PROT_IO(sp))
  3149. continue;
  3150. sfcp = sp->fcport;
  3151. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  3152. continue;
  3153. set_bit(ISP_ABORT_NEEDED,
  3154. &vha->dpc_flags);
  3155. break;
  3156. }
  3157. spin_unlock_irqrestore(&ha->hardware_lock,
  3158. cpu_flags);
  3159. }
  3160. start_dpc++;
  3161. }
  3162. /* if the loop has been down for 4 minutes, reinit adapter */
  3163. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  3164. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  3165. DEBUG(printk("scsi(%ld): Loop down - "
  3166. "aborting ISP.\n",
  3167. vha->host_no));
  3168. qla_printk(KERN_WARNING, ha,
  3169. "Loop down - aborting ISP.\n");
  3170. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3171. }
  3172. }
  3173. DEBUG3(printk("scsi(%ld): Loop Down - seconds remaining %d\n",
  3174. vha->host_no,
  3175. atomic_read(&vha->loop_down_timer)));
  3176. }
  3177. /* Check if beacon LED needs to be blinked */
  3178. if (ha->beacon_blink_led == 1) {
  3179. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  3180. start_dpc++;
  3181. }
  3182. /* Process any deferred work. */
  3183. if (!list_empty(&vha->work_list))
  3184. start_dpc++;
  3185. /* Schedule the DPC routine if needed */
  3186. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  3187. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  3188. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  3189. start_dpc ||
  3190. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  3191. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  3192. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  3193. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  3194. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  3195. test_bit(RELOGIN_NEEDED, &vha->dpc_flags)))
  3196. qla2xxx_wake_dpc(vha);
  3197. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3198. }
  3199. /* Firmware interface routines. */
  3200. #define FW_BLOBS 8
  3201. #define FW_ISP21XX 0
  3202. #define FW_ISP22XX 1
  3203. #define FW_ISP2300 2
  3204. #define FW_ISP2322 3
  3205. #define FW_ISP24XX 4
  3206. #define FW_ISP25XX 5
  3207. #define FW_ISP81XX 6
  3208. #define FW_ISP82XX 7
  3209. #define FW_FILE_ISP21XX "ql2100_fw.bin"
  3210. #define FW_FILE_ISP22XX "ql2200_fw.bin"
  3211. #define FW_FILE_ISP2300 "ql2300_fw.bin"
  3212. #define FW_FILE_ISP2322 "ql2322_fw.bin"
  3213. #define FW_FILE_ISP24XX "ql2400_fw.bin"
  3214. #define FW_FILE_ISP25XX "ql2500_fw.bin"
  3215. #define FW_FILE_ISP81XX "ql8100_fw.bin"
  3216. #define FW_FILE_ISP82XX "ql8200_fw.bin"
  3217. static DEFINE_MUTEX(qla_fw_lock);
  3218. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  3219. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  3220. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  3221. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  3222. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  3223. { .name = FW_FILE_ISP24XX, },
  3224. { .name = FW_FILE_ISP25XX, },
  3225. { .name = FW_FILE_ISP81XX, },
  3226. { .name = FW_FILE_ISP82XX, },
  3227. };
  3228. struct fw_blob *
  3229. qla2x00_request_firmware(scsi_qla_host_t *vha)
  3230. {
  3231. struct qla_hw_data *ha = vha->hw;
  3232. struct fw_blob *blob;
  3233. blob = NULL;
  3234. if (IS_QLA2100(ha)) {
  3235. blob = &qla_fw_blobs[FW_ISP21XX];
  3236. } else if (IS_QLA2200(ha)) {
  3237. blob = &qla_fw_blobs[FW_ISP22XX];
  3238. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3239. blob = &qla_fw_blobs[FW_ISP2300];
  3240. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  3241. blob = &qla_fw_blobs[FW_ISP2322];
  3242. } else if (IS_QLA24XX_TYPE(ha)) {
  3243. blob = &qla_fw_blobs[FW_ISP24XX];
  3244. } else if (IS_QLA25XX(ha)) {
  3245. blob = &qla_fw_blobs[FW_ISP25XX];
  3246. } else if (IS_QLA81XX(ha)) {
  3247. blob = &qla_fw_blobs[FW_ISP81XX];
  3248. } else if (IS_QLA82XX(ha)) {
  3249. blob = &qla_fw_blobs[FW_ISP82XX];
  3250. }
  3251. mutex_lock(&qla_fw_lock);
  3252. if (blob->fw)
  3253. goto out;
  3254. if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  3255. DEBUG2(printk("scsi(%ld): Failed to load firmware image "
  3256. "(%s).\n", vha->host_no, blob->name));
  3257. blob->fw = NULL;
  3258. blob = NULL;
  3259. goto out;
  3260. }
  3261. out:
  3262. mutex_unlock(&qla_fw_lock);
  3263. return blob;
  3264. }
  3265. static void
  3266. qla2x00_release_firmware(void)
  3267. {
  3268. int idx;
  3269. mutex_lock(&qla_fw_lock);
  3270. for (idx = 0; idx < FW_BLOBS; idx++)
  3271. if (qla_fw_blobs[idx].fw)
  3272. release_firmware(qla_fw_blobs[idx].fw);
  3273. mutex_unlock(&qla_fw_lock);
  3274. }
  3275. static pci_ers_result_t
  3276. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  3277. {
  3278. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  3279. struct qla_hw_data *ha = vha->hw;
  3280. DEBUG2(qla_printk(KERN_WARNING, ha, "error_detected:state %x\n",
  3281. state));
  3282. switch (state) {
  3283. case pci_channel_io_normal:
  3284. ha->flags.eeh_busy = 0;
  3285. return PCI_ERS_RESULT_CAN_RECOVER;
  3286. case pci_channel_io_frozen:
  3287. ha->flags.eeh_busy = 1;
  3288. /* For ISP82XX complete any pending mailbox cmd */
  3289. if (IS_QLA82XX(ha)) {
  3290. ha->flags.isp82xx_fw_hung = 1;
  3291. if (ha->flags.mbox_busy) {
  3292. ha->flags.mbox_int = 1;
  3293. DEBUG2(qla_printk(KERN_ERR, ha,
  3294. "Due to pci channel io frozen, doing premature "
  3295. "completion of mbx command\n"));
  3296. complete(&ha->mbx_intr_comp);
  3297. }
  3298. }
  3299. qla2x00_free_irqs(vha);
  3300. pci_disable_device(pdev);
  3301. /* Return back all IOs */
  3302. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3303. return PCI_ERS_RESULT_NEED_RESET;
  3304. case pci_channel_io_perm_failure:
  3305. ha->flags.pci_channel_io_perm_failure = 1;
  3306. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  3307. return PCI_ERS_RESULT_DISCONNECT;
  3308. }
  3309. return PCI_ERS_RESULT_NEED_RESET;
  3310. }
  3311. static pci_ers_result_t
  3312. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  3313. {
  3314. int risc_paused = 0;
  3315. uint32_t stat;
  3316. unsigned long flags;
  3317. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3318. struct qla_hw_data *ha = base_vha->hw;
  3319. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3320. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  3321. if (IS_QLA82XX(ha))
  3322. return PCI_ERS_RESULT_RECOVERED;
  3323. spin_lock_irqsave(&ha->hardware_lock, flags);
  3324. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  3325. stat = RD_REG_DWORD(&reg->hccr);
  3326. if (stat & HCCR_RISC_PAUSE)
  3327. risc_paused = 1;
  3328. } else if (IS_QLA23XX(ha)) {
  3329. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  3330. if (stat & HSR_RISC_PAUSED)
  3331. risc_paused = 1;
  3332. } else if (IS_FWI2_CAPABLE(ha)) {
  3333. stat = RD_REG_DWORD(&reg24->host_status);
  3334. if (stat & HSRX_RISC_PAUSED)
  3335. risc_paused = 1;
  3336. }
  3337. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3338. if (risc_paused) {
  3339. qla_printk(KERN_INFO, ha, "RISC paused -- mmio_enabled, "
  3340. "Dumping firmware!\n");
  3341. ha->isp_ops->fw_dump(base_vha, 0);
  3342. return PCI_ERS_RESULT_NEED_RESET;
  3343. } else
  3344. return PCI_ERS_RESULT_RECOVERED;
  3345. }
  3346. uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  3347. {
  3348. uint32_t rval = QLA_FUNCTION_FAILED;
  3349. uint32_t drv_active = 0;
  3350. struct qla_hw_data *ha = base_vha->hw;
  3351. int fn;
  3352. struct pci_dev *other_pdev = NULL;
  3353. DEBUG17(qla_printk(KERN_INFO, ha,
  3354. "scsi(%ld): In qla82xx_error_recovery\n", base_vha->host_no));
  3355. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3356. if (base_vha->flags.online) {
  3357. /* Abort all outstanding commands,
  3358. * so as to be requeued later */
  3359. qla2x00_abort_isp_cleanup(base_vha);
  3360. }
  3361. fn = PCI_FUNC(ha->pdev->devfn);
  3362. while (fn > 0) {
  3363. fn--;
  3364. DEBUG17(qla_printk(KERN_INFO, ha,
  3365. "Finding pci device at function = 0x%x\n", fn));
  3366. other_pdev =
  3367. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  3368. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  3369. fn));
  3370. if (!other_pdev)
  3371. continue;
  3372. if (atomic_read(&other_pdev->enable_cnt)) {
  3373. DEBUG17(qla_printk(KERN_INFO, ha,
  3374. "Found PCI func availabe and enabled at 0x%x\n",
  3375. fn));
  3376. pci_dev_put(other_pdev);
  3377. break;
  3378. }
  3379. pci_dev_put(other_pdev);
  3380. }
  3381. if (!fn) {
  3382. /* Reset owner */
  3383. DEBUG17(qla_printk(KERN_INFO, ha,
  3384. "This devfn is reset owner = 0x%x\n", ha->pdev->devfn));
  3385. qla82xx_idc_lock(ha);
  3386. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3387. QLA82XX_DEV_INITIALIZING);
  3388. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  3389. QLA82XX_IDC_VERSION);
  3390. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  3391. DEBUG17(qla_printk(KERN_INFO, ha,
  3392. "drv_active = 0x%x\n", drv_active));
  3393. qla82xx_idc_unlock(ha);
  3394. /* Reset if device is not already reset
  3395. * drv_active would be 0 if a reset has already been done
  3396. */
  3397. if (drv_active)
  3398. rval = qla82xx_start_firmware(base_vha);
  3399. else
  3400. rval = QLA_SUCCESS;
  3401. qla82xx_idc_lock(ha);
  3402. if (rval != QLA_SUCCESS) {
  3403. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  3404. qla82xx_clear_drv_active(ha);
  3405. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3406. QLA82XX_DEV_FAILED);
  3407. } else {
  3408. qla_printk(KERN_INFO, ha, "HW State: READY\n");
  3409. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3410. QLA82XX_DEV_READY);
  3411. qla82xx_idc_unlock(ha);
  3412. ha->flags.isp82xx_fw_hung = 0;
  3413. rval = qla82xx_restart_isp(base_vha);
  3414. qla82xx_idc_lock(ha);
  3415. /* Clear driver state register */
  3416. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  3417. qla82xx_set_drv_active(base_vha);
  3418. }
  3419. qla82xx_idc_unlock(ha);
  3420. } else {
  3421. DEBUG17(qla_printk(KERN_INFO, ha,
  3422. "This devfn is not reset owner = 0x%x\n", ha->pdev->devfn));
  3423. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  3424. QLA82XX_DEV_READY)) {
  3425. ha->flags.isp82xx_fw_hung = 0;
  3426. rval = qla82xx_restart_isp(base_vha);
  3427. qla82xx_idc_lock(ha);
  3428. qla82xx_set_drv_active(base_vha);
  3429. qla82xx_idc_unlock(ha);
  3430. }
  3431. }
  3432. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3433. return rval;
  3434. }
  3435. static pci_ers_result_t
  3436. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  3437. {
  3438. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  3439. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3440. struct qla_hw_data *ha = base_vha->hw;
  3441. struct rsp_que *rsp;
  3442. int rc, retries = 10;
  3443. DEBUG17(qla_printk(KERN_WARNING, ha, "slot_reset\n"));
  3444. /* Workaround: qla2xxx driver which access hardware earlier
  3445. * needs error state to be pci_channel_io_online.
  3446. * Otherwise mailbox command timesout.
  3447. */
  3448. pdev->error_state = pci_channel_io_normal;
  3449. pci_restore_state(pdev);
  3450. /* pci_restore_state() clears the saved_state flag of the device
  3451. * save restored state which resets saved_state flag
  3452. */
  3453. pci_save_state(pdev);
  3454. if (ha->mem_only)
  3455. rc = pci_enable_device_mem(pdev);
  3456. else
  3457. rc = pci_enable_device(pdev);
  3458. if (rc) {
  3459. qla_printk(KERN_WARNING, ha,
  3460. "Can't re-enable PCI device after reset.\n");
  3461. goto exit_slot_reset;
  3462. }
  3463. rsp = ha->rsp_q_map[0];
  3464. if (qla2x00_request_irqs(ha, rsp))
  3465. goto exit_slot_reset;
  3466. if (ha->isp_ops->pci_config(base_vha))
  3467. goto exit_slot_reset;
  3468. if (IS_QLA82XX(ha)) {
  3469. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  3470. ret = PCI_ERS_RESULT_RECOVERED;
  3471. goto exit_slot_reset;
  3472. } else
  3473. goto exit_slot_reset;
  3474. }
  3475. while (ha->flags.mbox_busy && retries--)
  3476. msleep(1000);
  3477. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3478. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  3479. ret = PCI_ERS_RESULT_RECOVERED;
  3480. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3481. exit_slot_reset:
  3482. DEBUG17(qla_printk(KERN_WARNING, ha,
  3483. "slot_reset-return:ret=%x\n", ret));
  3484. return ret;
  3485. }
  3486. static void
  3487. qla2xxx_pci_resume(struct pci_dev *pdev)
  3488. {
  3489. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3490. struct qla_hw_data *ha = base_vha->hw;
  3491. int ret;
  3492. DEBUG17(qla_printk(KERN_WARNING, ha, "pci_resume\n"));
  3493. ret = qla2x00_wait_for_hba_online(base_vha);
  3494. if (ret != QLA_SUCCESS) {
  3495. qla_printk(KERN_ERR, ha,
  3496. "the device failed to resume I/O "
  3497. "from slot/link_reset");
  3498. }
  3499. pci_cleanup_aer_uncorrect_error_status(pdev);
  3500. ha->flags.eeh_busy = 0;
  3501. }
  3502. static struct pci_error_handlers qla2xxx_err_handler = {
  3503. .error_detected = qla2xxx_pci_error_detected,
  3504. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  3505. .slot_reset = qla2xxx_pci_slot_reset,
  3506. .resume = qla2xxx_pci_resume,
  3507. };
  3508. static struct pci_device_id qla2xxx_pci_tbl[] = {
  3509. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  3510. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  3511. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  3512. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  3513. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  3514. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  3515. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  3516. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  3517. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  3518. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  3519. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  3520. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  3521. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  3522. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  3523. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  3524. { 0 },
  3525. };
  3526. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  3527. static struct pci_driver qla2xxx_pci_driver = {
  3528. .name = QLA2XXX_DRIVER_NAME,
  3529. .driver = {
  3530. .owner = THIS_MODULE,
  3531. },
  3532. .id_table = qla2xxx_pci_tbl,
  3533. .probe = qla2x00_probe_one,
  3534. .remove = qla2x00_remove_one,
  3535. .shutdown = qla2x00_shutdown,
  3536. .err_handler = &qla2xxx_err_handler,
  3537. };
  3538. static struct file_operations apidev_fops = {
  3539. .owner = THIS_MODULE,
  3540. .llseek = noop_llseek,
  3541. };
  3542. /**
  3543. * qla2x00_module_init - Module initialization.
  3544. **/
  3545. static int __init
  3546. qla2x00_module_init(void)
  3547. {
  3548. int ret = 0;
  3549. /* Allocate cache for SRBs. */
  3550. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  3551. SLAB_HWCACHE_ALIGN, NULL);
  3552. if (srb_cachep == NULL) {
  3553. printk(KERN_ERR
  3554. "qla2xxx: Unable to allocate SRB cache...Failing load!\n");
  3555. return -ENOMEM;
  3556. }
  3557. /* Derive version string. */
  3558. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  3559. if (ql2xextended_error_logging)
  3560. strcat(qla2x00_version_str, "-debug");
  3561. qla2xxx_transport_template =
  3562. fc_attach_transport(&qla2xxx_transport_functions);
  3563. if (!qla2xxx_transport_template) {
  3564. kmem_cache_destroy(srb_cachep);
  3565. return -ENODEV;
  3566. }
  3567. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  3568. if (apidev_major < 0) {
  3569. printk(KERN_WARNING "qla2xxx: Unable to register char device "
  3570. "%s\n", QLA2XXX_APIDEV);
  3571. }
  3572. qla2xxx_transport_vport_template =
  3573. fc_attach_transport(&qla2xxx_transport_vport_functions);
  3574. if (!qla2xxx_transport_vport_template) {
  3575. kmem_cache_destroy(srb_cachep);
  3576. fc_release_transport(qla2xxx_transport_template);
  3577. return -ENODEV;
  3578. }
  3579. printk(KERN_INFO "QLogic Fibre Channel HBA Driver: %s\n",
  3580. qla2x00_version_str);
  3581. ret = pci_register_driver(&qla2xxx_pci_driver);
  3582. if (ret) {
  3583. kmem_cache_destroy(srb_cachep);
  3584. fc_release_transport(qla2xxx_transport_template);
  3585. fc_release_transport(qla2xxx_transport_vport_template);
  3586. }
  3587. return ret;
  3588. }
  3589. /**
  3590. * qla2x00_module_exit - Module cleanup.
  3591. **/
  3592. static void __exit
  3593. qla2x00_module_exit(void)
  3594. {
  3595. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  3596. pci_unregister_driver(&qla2xxx_pci_driver);
  3597. qla2x00_release_firmware();
  3598. kmem_cache_destroy(srb_cachep);
  3599. if (ctx_cachep)
  3600. kmem_cache_destroy(ctx_cachep);
  3601. fc_release_transport(qla2xxx_transport_template);
  3602. fc_release_transport(qla2xxx_transport_vport_template);
  3603. }
  3604. module_init(qla2x00_module_init);
  3605. module_exit(qla2x00_module_exit);
  3606. MODULE_AUTHOR("QLogic Corporation");
  3607. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  3608. MODULE_LICENSE("GPL");
  3609. MODULE_VERSION(QLA2XXX_VERSION);
  3610. MODULE_FIRMWARE(FW_FILE_ISP21XX);
  3611. MODULE_FIRMWARE(FW_FILE_ISP22XX);
  3612. MODULE_FIRMWARE(FW_FILE_ISP2300);
  3613. MODULE_FIRMWARE(FW_FILE_ISP2322);
  3614. MODULE_FIRMWARE(FW_FILE_ISP24XX);
  3615. MODULE_FIRMWARE(FW_FILE_ISP25XX);