mv_sas.c 57 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. *
  7. * This file is licensed under GPLv2.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; version 2 of the
  12. * License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  22. * USA
  23. */
  24. #include "mv_sas.h"
  25. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  26. {
  27. if (task->lldd_task) {
  28. struct mvs_slot_info *slot;
  29. slot = task->lldd_task;
  30. *tag = slot->slot_tag;
  31. return 1;
  32. }
  33. return 0;
  34. }
  35. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  36. {
  37. void *bitmap = &mvi->tags;
  38. clear_bit(tag, bitmap);
  39. }
  40. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  41. {
  42. mvs_tag_clear(mvi, tag);
  43. }
  44. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  45. {
  46. void *bitmap = &mvi->tags;
  47. set_bit(tag, bitmap);
  48. }
  49. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  50. {
  51. unsigned int index, tag;
  52. void *bitmap = &mvi->tags;
  53. index = find_first_zero_bit(bitmap, mvi->tags_num);
  54. tag = index;
  55. if (tag >= mvi->tags_num)
  56. return -SAS_QUEUE_FULL;
  57. mvs_tag_set(mvi, tag);
  58. *tag_out = tag;
  59. return 0;
  60. }
  61. void mvs_tag_init(struct mvs_info *mvi)
  62. {
  63. int i;
  64. for (i = 0; i < mvi->tags_num; ++i)
  65. mvs_tag_clear(mvi, i);
  66. }
  67. void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
  68. {
  69. u32 i;
  70. u32 run;
  71. u32 offset;
  72. offset = 0;
  73. while (size) {
  74. printk(KERN_DEBUG"%08X : ", baseaddr + offset);
  75. if (size >= 16)
  76. run = 16;
  77. else
  78. run = size;
  79. size -= run;
  80. for (i = 0; i < 16; i++) {
  81. if (i < run)
  82. printk(KERN_DEBUG"%02X ", (u32)data[i]);
  83. else
  84. printk(KERN_DEBUG" ");
  85. }
  86. printk(KERN_DEBUG": ");
  87. for (i = 0; i < run; i++)
  88. printk(KERN_DEBUG"%c",
  89. isalnum(data[i]) ? data[i] : '.');
  90. printk(KERN_DEBUG"\n");
  91. data = &data[16];
  92. offset += run;
  93. }
  94. printk(KERN_DEBUG"\n");
  95. }
  96. #if (_MV_DUMP > 1)
  97. static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
  98. enum sas_protocol proto)
  99. {
  100. u32 offset;
  101. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  102. offset = slot->cmd_size + MVS_OAF_SZ +
  103. MVS_CHIP_DISP->prd_size() * slot->n_elem;
  104. dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
  105. tag);
  106. mvs_hexdump(32, (u8 *) slot->response,
  107. (u32) slot->buf_dma + offset);
  108. }
  109. #endif
  110. static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
  111. enum sas_protocol proto)
  112. {
  113. #if (_MV_DUMP > 1)
  114. u32 sz, w_ptr;
  115. u64 addr;
  116. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  117. /*Delivery Queue */
  118. sz = MVS_CHIP_SLOT_SZ;
  119. w_ptr = slot->tx;
  120. addr = mvi->tx_dma;
  121. dev_printk(KERN_DEBUG, mvi->dev,
  122. "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
  123. dev_printk(KERN_DEBUG, mvi->dev,
  124. "Delivery Queue Base Address=0x%llX (PA)"
  125. "(tx_dma=0x%llX), Entry=%04d\n",
  126. addr, (unsigned long long)mvi->tx_dma, w_ptr);
  127. mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
  128. (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
  129. /*Command List */
  130. addr = mvi->slot_dma;
  131. dev_printk(KERN_DEBUG, mvi->dev,
  132. "Command List Base Address=0x%llX (PA)"
  133. "(slot_dma=0x%llX), Header=%03d\n",
  134. addr, (unsigned long long)slot->buf_dma, tag);
  135. dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
  136. /*mvs_cmd_hdr */
  137. mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
  138. (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
  139. /*1.command table area */
  140. dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
  141. mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
  142. /*2.open address frame area */
  143. dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
  144. mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
  145. (u32) slot->buf_dma + slot->cmd_size);
  146. /*3.status buffer */
  147. mvs_hba_sb_dump(mvi, tag, proto);
  148. /*4.PRD table */
  149. dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
  150. mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
  151. (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
  152. (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
  153. #endif
  154. }
  155. static void mvs_hba_cq_dump(struct mvs_info *mvi)
  156. {
  157. #if (_MV_DUMP > 2)
  158. u64 addr;
  159. void __iomem *regs = mvi->regs;
  160. u32 entry = mvi->rx_cons + 1;
  161. u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
  162. /*Completion Queue */
  163. addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
  164. dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
  165. mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
  166. dev_printk(KERN_DEBUG, mvi->dev,
  167. "Completion List Base Address=0x%llX (PA), "
  168. "CQ_Entry=%04d, CQ_WP=0x%08X\n",
  169. addr, entry - 1, mvi->rx[0]);
  170. mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
  171. mvi->rx_dma + sizeof(u32) * entry);
  172. #endif
  173. }
  174. void mvs_get_sas_addr(void *buf, u32 buflen)
  175. {
  176. /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
  177. }
  178. struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  179. {
  180. unsigned long i = 0, j = 0, hi = 0;
  181. struct sas_ha_struct *sha = dev->port->ha;
  182. struct mvs_info *mvi = NULL;
  183. struct asd_sas_phy *phy;
  184. while (sha->sas_port[i]) {
  185. if (sha->sas_port[i] == dev->port) {
  186. phy = container_of(sha->sas_port[i]->phy_list.next,
  187. struct asd_sas_phy, port_phy_el);
  188. j = 0;
  189. while (sha->sas_phy[j]) {
  190. if (sha->sas_phy[j] == phy)
  191. break;
  192. j++;
  193. }
  194. break;
  195. }
  196. i++;
  197. }
  198. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  199. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  200. return mvi;
  201. }
  202. /* FIXME */
  203. int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  204. {
  205. unsigned long i = 0, j = 0, n = 0, num = 0;
  206. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  207. struct mvs_info *mvi = mvi_dev->mvi_info;
  208. struct sas_ha_struct *sha = dev->port->ha;
  209. while (sha->sas_port[i]) {
  210. if (sha->sas_port[i] == dev->port) {
  211. struct asd_sas_phy *phy;
  212. list_for_each_entry(phy,
  213. &sha->sas_port[i]->phy_list, port_phy_el) {
  214. j = 0;
  215. while (sha->sas_phy[j]) {
  216. if (sha->sas_phy[j] == phy)
  217. break;
  218. j++;
  219. }
  220. phyno[n] = (j >= mvi->chip->n_phy) ?
  221. (j - mvi->chip->n_phy) : j;
  222. num++;
  223. n++;
  224. }
  225. break;
  226. }
  227. i++;
  228. }
  229. return num;
  230. }
  231. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  232. struct mvs_device *dev)
  233. {
  234. if (!dev) {
  235. mv_printk("device has been free.\n");
  236. return;
  237. }
  238. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  239. return;
  240. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  241. }
  242. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  243. struct mvs_device *dev)
  244. {
  245. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  246. return 0;
  247. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  248. }
  249. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  250. {
  251. u32 no;
  252. for_each_phy(phy_mask, phy_mask, no) {
  253. if (!(phy_mask & 1))
  254. continue;
  255. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  256. }
  257. }
  258. /* FIXME: locking? */
  259. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  260. void *funcdata)
  261. {
  262. int rc = 0, phy_id = sas_phy->id;
  263. u32 tmp, i = 0, hi;
  264. struct sas_ha_struct *sha = sas_phy->ha;
  265. struct mvs_info *mvi = NULL;
  266. while (sha->sas_phy[i]) {
  267. if (sha->sas_phy[i] == sas_phy)
  268. break;
  269. i++;
  270. }
  271. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  272. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  273. switch (func) {
  274. case PHY_FUNC_SET_LINK_RATE:
  275. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  276. break;
  277. case PHY_FUNC_HARD_RESET:
  278. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  279. if (tmp & PHY_RST_HARD)
  280. break;
  281. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
  282. break;
  283. case PHY_FUNC_LINK_RESET:
  284. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  285. MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
  286. break;
  287. case PHY_FUNC_DISABLE:
  288. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  289. break;
  290. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  291. default:
  292. rc = -EOPNOTSUPP;
  293. }
  294. msleep(200);
  295. return rc;
  296. }
  297. void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
  298. u32 off_lo, u32 off_hi, u64 sas_addr)
  299. {
  300. u32 lo = (u32)sas_addr;
  301. u32 hi = (u32)(sas_addr>>32);
  302. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  303. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  304. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  305. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  306. }
  307. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  308. {
  309. struct mvs_phy *phy = &mvi->phy[i];
  310. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  311. struct sas_ha_struct *sas_ha;
  312. if (!phy->phy_attached)
  313. return;
  314. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  315. && phy->phy_type & PORT_TYPE_SAS) {
  316. return;
  317. }
  318. sas_ha = mvi->sas;
  319. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  320. if (sas_phy->phy) {
  321. struct sas_phy *sphy = sas_phy->phy;
  322. sphy->negotiated_linkrate = sas_phy->linkrate;
  323. sphy->minimum_linkrate = phy->minimum_linkrate;
  324. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  325. sphy->maximum_linkrate = phy->maximum_linkrate;
  326. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  327. }
  328. if (phy->phy_type & PORT_TYPE_SAS) {
  329. struct sas_identify_frame *id;
  330. id = (struct sas_identify_frame *)phy->frame_rcvd;
  331. id->dev_type = phy->identify.device_type;
  332. id->initiator_bits = SAS_PROTOCOL_ALL;
  333. id->target_bits = phy->identify.target_port_protocols;
  334. } else if (phy->phy_type & PORT_TYPE_SATA) {
  335. /*Nothing*/
  336. }
  337. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  338. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  339. mvi->sas->notify_port_event(sas_phy,
  340. PORTE_BYTES_DMAED);
  341. }
  342. int mvs_slave_alloc(struct scsi_device *scsi_dev)
  343. {
  344. struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
  345. if (dev_is_sata(dev)) {
  346. /* We don't need to rescan targets
  347. * if REPORT_LUNS request is failed
  348. */
  349. if (scsi_dev->lun > 0)
  350. return -ENXIO;
  351. scsi_dev->tagged_supported = 1;
  352. }
  353. return sas_slave_alloc(scsi_dev);
  354. }
  355. int mvs_slave_configure(struct scsi_device *sdev)
  356. {
  357. struct domain_device *dev = sdev_to_domain_dev(sdev);
  358. int ret = sas_slave_configure(sdev);
  359. if (ret)
  360. return ret;
  361. if (dev_is_sata(dev)) {
  362. /* may set PIO mode */
  363. #if MV_DISABLE_NCQ
  364. struct ata_port *ap = dev->sata_dev.ap;
  365. struct ata_device *adev = ap->link.device;
  366. adev->flags |= ATA_DFLAG_NCQ_OFF;
  367. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
  368. #endif
  369. }
  370. return 0;
  371. }
  372. void mvs_scan_start(struct Scsi_Host *shost)
  373. {
  374. int i, j;
  375. unsigned short core_nr;
  376. struct mvs_info *mvi;
  377. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  378. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  379. for (j = 0; j < core_nr; j++) {
  380. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  381. for (i = 0; i < mvi->chip->n_phy; ++i)
  382. mvs_bytes_dmaed(mvi, i);
  383. }
  384. }
  385. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  386. {
  387. /* give the phy enabling interrupt event time to come in (1s
  388. * is empirically about all it takes) */
  389. if (time < HZ)
  390. return 0;
  391. /* Wait for discovery to finish */
  392. scsi_flush_work(shost);
  393. return 1;
  394. }
  395. static int mvs_task_prep_smp(struct mvs_info *mvi,
  396. struct mvs_task_exec_info *tei)
  397. {
  398. int elem, rc, i;
  399. struct sas_task *task = tei->task;
  400. struct mvs_cmd_hdr *hdr = tei->hdr;
  401. struct domain_device *dev = task->dev;
  402. struct asd_sas_port *sas_port = dev->port;
  403. struct scatterlist *sg_req, *sg_resp;
  404. u32 req_len, resp_len, tag = tei->tag;
  405. void *buf_tmp;
  406. u8 *buf_oaf;
  407. dma_addr_t buf_tmp_dma;
  408. void *buf_prd;
  409. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  410. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  411. #if _MV_DUMP
  412. u8 *buf_cmd;
  413. void *from;
  414. #endif
  415. /*
  416. * DMA-map SMP request, response buffers
  417. */
  418. sg_req = &task->smp_task.smp_req;
  419. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  420. if (!elem)
  421. return -ENOMEM;
  422. req_len = sg_dma_len(sg_req);
  423. sg_resp = &task->smp_task.smp_resp;
  424. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  425. if (!elem) {
  426. rc = -ENOMEM;
  427. goto err_out;
  428. }
  429. resp_len = SB_RFB_MAX;
  430. /* must be in dwords */
  431. if ((req_len & 0x3) || (resp_len & 0x3)) {
  432. rc = -EINVAL;
  433. goto err_out_2;
  434. }
  435. /*
  436. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  437. */
  438. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  439. buf_tmp = slot->buf;
  440. buf_tmp_dma = slot->buf_dma;
  441. #if _MV_DUMP
  442. buf_cmd = buf_tmp;
  443. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  444. buf_tmp += req_len;
  445. buf_tmp_dma += req_len;
  446. slot->cmd_size = req_len;
  447. #else
  448. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  449. #endif
  450. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  451. buf_oaf = buf_tmp;
  452. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  453. buf_tmp += MVS_OAF_SZ;
  454. buf_tmp_dma += MVS_OAF_SZ;
  455. /* region 3: PRD table *********************************** */
  456. buf_prd = buf_tmp;
  457. if (tei->n_elem)
  458. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  459. else
  460. hdr->prd_tbl = 0;
  461. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  462. buf_tmp += i;
  463. buf_tmp_dma += i;
  464. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  465. slot->response = buf_tmp;
  466. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  467. if (mvi->flags & MVF_FLAG_SOC)
  468. hdr->reserved[0] = 0;
  469. /*
  470. * Fill in TX ring and command slot header
  471. */
  472. slot->tx = mvi->tx_prod;
  473. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  474. TXQ_MODE_I | tag |
  475. (sas_port->phy_mask << TXQ_PHY_SHIFT));
  476. hdr->flags |= flags;
  477. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  478. hdr->tags = cpu_to_le32(tag);
  479. hdr->data_len = 0;
  480. /* generate open address frame hdr (first 12 bytes) */
  481. /* initiator, SMP, ftype 1h */
  482. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  483. buf_oaf[1] = dev->linkrate & 0xf;
  484. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  485. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  486. /* fill in PRD (scatter/gather) table, if any */
  487. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  488. #if _MV_DUMP
  489. /* copy cmd table */
  490. from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
  491. memcpy(buf_cmd, from + sg_req->offset, req_len);
  492. kunmap_atomic(from, KM_IRQ0);
  493. #endif
  494. return 0;
  495. err_out_2:
  496. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  497. PCI_DMA_FROMDEVICE);
  498. err_out:
  499. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  500. PCI_DMA_TODEVICE);
  501. return rc;
  502. }
  503. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  504. {
  505. struct ata_queued_cmd *qc = task->uldd_task;
  506. if (qc) {
  507. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  508. qc->tf.command == ATA_CMD_FPDMA_READ) {
  509. *tag = qc->tag;
  510. return 1;
  511. }
  512. }
  513. return 0;
  514. }
  515. static int mvs_task_prep_ata(struct mvs_info *mvi,
  516. struct mvs_task_exec_info *tei)
  517. {
  518. struct sas_task *task = tei->task;
  519. struct domain_device *dev = task->dev;
  520. struct mvs_device *mvi_dev = dev->lldd_dev;
  521. struct mvs_cmd_hdr *hdr = tei->hdr;
  522. struct asd_sas_port *sas_port = dev->port;
  523. struct mvs_slot_info *slot;
  524. void *buf_prd;
  525. u32 tag = tei->tag, hdr_tag;
  526. u32 flags, del_q;
  527. void *buf_tmp;
  528. u8 *buf_cmd, *buf_oaf;
  529. dma_addr_t buf_tmp_dma;
  530. u32 i, req_len, resp_len;
  531. const u32 max_resp_len = SB_RFB_MAX;
  532. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  533. mv_dprintk("Have not enough regiset for dev %d.\n",
  534. mvi_dev->device_id);
  535. return -EBUSY;
  536. }
  537. slot = &mvi->slot_info[tag];
  538. slot->tx = mvi->tx_prod;
  539. del_q = TXQ_MODE_I | tag |
  540. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  541. (sas_port->phy_mask << TXQ_PHY_SHIFT) |
  542. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  543. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  544. #ifndef DISABLE_HOTPLUG_DMA_FIX
  545. if (task->data_dir == DMA_FROM_DEVICE)
  546. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  547. else
  548. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  549. #else
  550. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  551. #endif
  552. if (task->ata_task.use_ncq)
  553. flags |= MCH_FPDMA;
  554. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
  555. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  556. flags |= MCH_ATAPI;
  557. }
  558. /* FIXME: fill in port multiplier number */
  559. hdr->flags = cpu_to_le32(flags);
  560. /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
  561. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  562. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  563. else
  564. hdr_tag = tag;
  565. hdr->tags = cpu_to_le32(hdr_tag);
  566. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  567. /*
  568. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  569. */
  570. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  571. buf_cmd = buf_tmp = slot->buf;
  572. buf_tmp_dma = slot->buf_dma;
  573. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  574. buf_tmp += MVS_ATA_CMD_SZ;
  575. buf_tmp_dma += MVS_ATA_CMD_SZ;
  576. #if _MV_DUMP
  577. slot->cmd_size = MVS_ATA_CMD_SZ;
  578. #endif
  579. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  580. /* used for STP. unused for SATA? */
  581. buf_oaf = buf_tmp;
  582. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  583. buf_tmp += MVS_OAF_SZ;
  584. buf_tmp_dma += MVS_OAF_SZ;
  585. /* region 3: PRD table ********************************************* */
  586. buf_prd = buf_tmp;
  587. if (tei->n_elem)
  588. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  589. else
  590. hdr->prd_tbl = 0;
  591. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  592. buf_tmp += i;
  593. buf_tmp_dma += i;
  594. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  595. /* FIXME: probably unused, for SATA. kept here just in case
  596. * we get a STP/SATA error information record
  597. */
  598. slot->response = buf_tmp;
  599. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  600. if (mvi->flags & MVF_FLAG_SOC)
  601. hdr->reserved[0] = 0;
  602. req_len = sizeof(struct host_to_dev_fis);
  603. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  604. sizeof(struct mvs_err_info) - i;
  605. /* request, response lengths */
  606. resp_len = min(resp_len, max_resp_len);
  607. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  608. if (likely(!task->ata_task.device_control_reg_update))
  609. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  610. /* fill in command FIS and ATAPI CDB */
  611. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  612. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
  613. memcpy(buf_cmd + STP_ATAPI_CMD,
  614. task->ata_task.atapi_packet, 16);
  615. /* generate open address frame hdr (first 12 bytes) */
  616. /* initiator, STP, ftype 1h */
  617. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  618. buf_oaf[1] = dev->linkrate & 0xf;
  619. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  620. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  621. /* fill in PRD (scatter/gather) table, if any */
  622. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  623. #ifndef DISABLE_HOTPLUG_DMA_FIX
  624. if (task->data_dir == DMA_FROM_DEVICE)
  625. MVS_CHIP_DISP->dma_fix(mvi->bulk_buffer_dma,
  626. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  627. #endif
  628. return 0;
  629. }
  630. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  631. struct mvs_task_exec_info *tei, int is_tmf,
  632. struct mvs_tmf_task *tmf)
  633. {
  634. struct sas_task *task = tei->task;
  635. struct mvs_cmd_hdr *hdr = tei->hdr;
  636. struct mvs_port *port = tei->port;
  637. struct domain_device *dev = task->dev;
  638. struct mvs_device *mvi_dev = dev->lldd_dev;
  639. struct asd_sas_port *sas_port = dev->port;
  640. struct mvs_slot_info *slot;
  641. void *buf_prd;
  642. struct ssp_frame_hdr *ssp_hdr;
  643. void *buf_tmp;
  644. u8 *buf_cmd, *buf_oaf, fburst = 0;
  645. dma_addr_t buf_tmp_dma;
  646. u32 flags;
  647. u32 resp_len, req_len, i, tag = tei->tag;
  648. const u32 max_resp_len = SB_RFB_MAX;
  649. u32 phy_mask;
  650. slot = &mvi->slot_info[tag];
  651. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  652. sas_port->phy_mask) & TXQ_PHY_MASK;
  653. slot->tx = mvi->tx_prod;
  654. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  655. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  656. (phy_mask << TXQ_PHY_SHIFT));
  657. flags = MCH_RETRY;
  658. if (task->ssp_task.enable_first_burst) {
  659. flags |= MCH_FBURST;
  660. fburst = (1 << 7);
  661. }
  662. if (is_tmf)
  663. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  664. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  665. hdr->tags = cpu_to_le32(tag);
  666. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  667. /*
  668. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  669. */
  670. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  671. buf_cmd = buf_tmp = slot->buf;
  672. buf_tmp_dma = slot->buf_dma;
  673. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  674. buf_tmp += MVS_SSP_CMD_SZ;
  675. buf_tmp_dma += MVS_SSP_CMD_SZ;
  676. #if _MV_DUMP
  677. slot->cmd_size = MVS_SSP_CMD_SZ;
  678. #endif
  679. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  680. buf_oaf = buf_tmp;
  681. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  682. buf_tmp += MVS_OAF_SZ;
  683. buf_tmp_dma += MVS_OAF_SZ;
  684. /* region 3: PRD table ********************************************* */
  685. buf_prd = buf_tmp;
  686. if (tei->n_elem)
  687. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  688. else
  689. hdr->prd_tbl = 0;
  690. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  691. buf_tmp += i;
  692. buf_tmp_dma += i;
  693. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  694. slot->response = buf_tmp;
  695. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  696. if (mvi->flags & MVF_FLAG_SOC)
  697. hdr->reserved[0] = 0;
  698. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  699. sizeof(struct mvs_err_info) - i;
  700. resp_len = min(resp_len, max_resp_len);
  701. req_len = sizeof(struct ssp_frame_hdr) + 28;
  702. /* request, response lengths */
  703. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  704. /* generate open address frame hdr (first 12 bytes) */
  705. /* initiator, SSP, ftype 1h */
  706. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  707. buf_oaf[1] = dev->linkrate & 0xf;
  708. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  709. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  710. /* fill in SSP frame header (Command Table.SSP frame header) */
  711. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  712. if (is_tmf)
  713. ssp_hdr->frame_type = SSP_TASK;
  714. else
  715. ssp_hdr->frame_type = SSP_COMMAND;
  716. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  717. HASHED_SAS_ADDR_SIZE);
  718. memcpy(ssp_hdr->hashed_src_addr,
  719. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  720. ssp_hdr->tag = cpu_to_be16(tag);
  721. /* fill in IU for TASK and Command Frame */
  722. buf_cmd += sizeof(*ssp_hdr);
  723. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  724. if (ssp_hdr->frame_type != SSP_TASK) {
  725. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  726. (task->ssp_task.task_prio << 3);
  727. memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
  728. } else{
  729. buf_cmd[10] = tmf->tmf;
  730. switch (tmf->tmf) {
  731. case TMF_ABORT_TASK:
  732. case TMF_QUERY_TASK:
  733. buf_cmd[12] =
  734. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  735. buf_cmd[13] =
  736. tmf->tag_of_task_to_be_managed & 0xff;
  737. break;
  738. default:
  739. break;
  740. }
  741. }
  742. /* fill in PRD (scatter/gather) table, if any */
  743. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  744. return 0;
  745. }
  746. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
  747. static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  748. struct completion *completion,int is_tmf,
  749. struct mvs_tmf_task *tmf)
  750. {
  751. struct domain_device *dev = task->dev;
  752. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  753. struct mvs_info *mvi = mvi_dev->mvi_info;
  754. struct mvs_task_exec_info tei;
  755. struct sas_task *t = task;
  756. struct mvs_slot_info *slot;
  757. u32 tag = 0xdeadbeef, rc, n_elem = 0;
  758. u32 n = num, pass = 0;
  759. unsigned long flags = 0, flags_libsas = 0;
  760. if (!dev->port) {
  761. struct task_status_struct *tsm = &t->task_status;
  762. tsm->resp = SAS_TASK_UNDELIVERED;
  763. tsm->stat = SAS_PHY_DOWN;
  764. if (dev->dev_type != SATA_DEV)
  765. t->task_done(t);
  766. return 0;
  767. }
  768. spin_lock_irqsave(&mvi->lock, flags);
  769. do {
  770. dev = t->dev;
  771. mvi_dev = dev->lldd_dev;
  772. if (DEV_IS_GONE(mvi_dev)) {
  773. if (mvi_dev)
  774. mv_dprintk("device %d not ready.\n",
  775. mvi_dev->device_id);
  776. else
  777. mv_dprintk("device %016llx not ready.\n",
  778. SAS_ADDR(dev->sas_addr));
  779. rc = SAS_PHY_DOWN;
  780. goto out_done;
  781. }
  782. if (dev->port->id >= mvi->chip->n_phy)
  783. tei.port = &mvi->port[dev->port->id - mvi->chip->n_phy];
  784. else
  785. tei.port = &mvi->port[dev->port->id];
  786. if (tei.port && !tei.port->port_attached) {
  787. if (sas_protocol_ata(t->task_proto)) {
  788. struct task_status_struct *ts = &t->task_status;
  789. mv_dprintk("port %d does not"
  790. "attached device.\n", dev->port->id);
  791. ts->stat = SAS_PROTO_RESPONSE;
  792. ts->stat = SAS_PHY_DOWN;
  793. spin_unlock_irqrestore(dev->sata_dev.ap->lock,
  794. flags_libsas);
  795. spin_unlock_irqrestore(&mvi->lock, flags);
  796. t->task_done(t);
  797. spin_lock_irqsave(&mvi->lock, flags);
  798. spin_lock_irqsave(dev->sata_dev.ap->lock,
  799. flags_libsas);
  800. if (n > 1)
  801. t = list_entry(t->list.next,
  802. struct sas_task, list);
  803. continue;
  804. } else {
  805. struct task_status_struct *ts = &t->task_status;
  806. ts->resp = SAS_TASK_UNDELIVERED;
  807. ts->stat = SAS_PHY_DOWN;
  808. t->task_done(t);
  809. if (n > 1)
  810. t = list_entry(t->list.next,
  811. struct sas_task, list);
  812. continue;
  813. }
  814. }
  815. if (!sas_protocol_ata(t->task_proto)) {
  816. if (t->num_scatter) {
  817. n_elem = dma_map_sg(mvi->dev,
  818. t->scatter,
  819. t->num_scatter,
  820. t->data_dir);
  821. if (!n_elem) {
  822. rc = -ENOMEM;
  823. goto err_out;
  824. }
  825. }
  826. } else {
  827. n_elem = t->num_scatter;
  828. }
  829. rc = mvs_tag_alloc(mvi, &tag);
  830. if (rc)
  831. goto err_out;
  832. slot = &mvi->slot_info[tag];
  833. t->lldd_task = NULL;
  834. slot->n_elem = n_elem;
  835. slot->slot_tag = tag;
  836. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  837. tei.task = t;
  838. tei.hdr = &mvi->slot[tag];
  839. tei.tag = tag;
  840. tei.n_elem = n_elem;
  841. switch (t->task_proto) {
  842. case SAS_PROTOCOL_SMP:
  843. rc = mvs_task_prep_smp(mvi, &tei);
  844. break;
  845. case SAS_PROTOCOL_SSP:
  846. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  847. break;
  848. case SAS_PROTOCOL_SATA:
  849. case SAS_PROTOCOL_STP:
  850. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  851. rc = mvs_task_prep_ata(mvi, &tei);
  852. break;
  853. default:
  854. dev_printk(KERN_ERR, mvi->dev,
  855. "unknown sas_task proto: 0x%x\n",
  856. t->task_proto);
  857. rc = -EINVAL;
  858. break;
  859. }
  860. if (rc) {
  861. mv_dprintk("rc is %x\n", rc);
  862. goto err_out_tag;
  863. }
  864. slot->task = t;
  865. slot->port = tei.port;
  866. t->lldd_task = slot;
  867. list_add_tail(&slot->entry, &tei.port->list);
  868. /* TODO: select normal or high priority */
  869. spin_lock(&t->task_state_lock);
  870. t->task_state_flags |= SAS_TASK_AT_INITIATOR;
  871. spin_unlock(&t->task_state_lock);
  872. mvs_hba_memory_dump(mvi, tag, t->task_proto);
  873. mvi_dev->running_req++;
  874. ++pass;
  875. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  876. if (n > 1)
  877. t = list_entry(t->list.next, struct sas_task, list);
  878. if (likely(pass))
  879. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  880. (MVS_CHIP_SLOT_SZ - 1));
  881. } while (--n);
  882. rc = 0;
  883. goto out_done;
  884. err_out_tag:
  885. mvs_tag_free(mvi, tag);
  886. err_out:
  887. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  888. if (!sas_protocol_ata(t->task_proto))
  889. if (n_elem)
  890. dma_unmap_sg(mvi->dev, t->scatter, n_elem,
  891. t->data_dir);
  892. out_done:
  893. spin_unlock_irqrestore(&mvi->lock, flags);
  894. return rc;
  895. }
  896. int mvs_queue_command(struct sas_task *task, const int num,
  897. gfp_t gfp_flags)
  898. {
  899. return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  900. }
  901. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  902. {
  903. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  904. mvs_tag_clear(mvi, slot_idx);
  905. }
  906. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  907. struct mvs_slot_info *slot, u32 slot_idx)
  908. {
  909. if (!slot->task)
  910. return;
  911. if (!sas_protocol_ata(task->task_proto))
  912. if (slot->n_elem)
  913. dma_unmap_sg(mvi->dev, task->scatter,
  914. slot->n_elem, task->data_dir);
  915. switch (task->task_proto) {
  916. case SAS_PROTOCOL_SMP:
  917. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  918. PCI_DMA_FROMDEVICE);
  919. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  920. PCI_DMA_TODEVICE);
  921. break;
  922. case SAS_PROTOCOL_SATA:
  923. case SAS_PROTOCOL_STP:
  924. case SAS_PROTOCOL_SSP:
  925. default:
  926. /* do nothing */
  927. break;
  928. }
  929. list_del_init(&slot->entry);
  930. task->lldd_task = NULL;
  931. slot->task = NULL;
  932. slot->port = NULL;
  933. slot->slot_tag = 0xFFFFFFFF;
  934. mvs_slot_free(mvi, slot_idx);
  935. }
  936. static void mvs_update_wideport(struct mvs_info *mvi, int i)
  937. {
  938. struct mvs_phy *phy = &mvi->phy[i];
  939. struct mvs_port *port = phy->port;
  940. int j, no;
  941. for_each_phy(port->wide_port_phymap, j, no) {
  942. if (j & 1) {
  943. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  944. PHYR_WIDE_PORT);
  945. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  946. port->wide_port_phymap);
  947. } else {
  948. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  949. PHYR_WIDE_PORT);
  950. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  951. 0);
  952. }
  953. }
  954. }
  955. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  956. {
  957. u32 tmp;
  958. struct mvs_phy *phy = &mvi->phy[i];
  959. struct mvs_port *port = phy->port;
  960. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  961. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  962. if (!port)
  963. phy->phy_attached = 1;
  964. return tmp;
  965. }
  966. if (port) {
  967. if (phy->phy_type & PORT_TYPE_SAS) {
  968. port->wide_port_phymap &= ~(1U << i);
  969. if (!port->wide_port_phymap)
  970. port->port_attached = 0;
  971. mvs_update_wideport(mvi, i);
  972. } else if (phy->phy_type & PORT_TYPE_SATA)
  973. port->port_attached = 0;
  974. phy->port = NULL;
  975. phy->phy_attached = 0;
  976. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  977. }
  978. return 0;
  979. }
  980. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  981. {
  982. u32 *s = (u32 *) buf;
  983. if (!s)
  984. return NULL;
  985. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  986. s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  987. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  988. s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  989. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  990. s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  991. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  992. s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
  993. /* Workaround: take some ATAPI devices for ATA */
  994. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  995. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  996. return s;
  997. }
  998. static u32 mvs_is_sig_fis_received(u32 irq_status)
  999. {
  1000. return irq_status & PHYEV_SIG_FIS;
  1001. }
  1002. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  1003. {
  1004. struct mvs_phy *phy = &mvi->phy[i];
  1005. struct sas_identify_frame *id;
  1006. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1007. if (get_st) {
  1008. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  1009. phy->phy_status = mvs_is_phy_ready(mvi, i);
  1010. }
  1011. if (phy->phy_status) {
  1012. int oob_done = 0;
  1013. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  1014. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  1015. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  1016. if (phy->phy_type & PORT_TYPE_SATA) {
  1017. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  1018. if (mvs_is_sig_fis_received(phy->irq_status)) {
  1019. phy->phy_attached = 1;
  1020. phy->att_dev_sas_addr =
  1021. i + mvi->id * mvi->chip->n_phy;
  1022. if (oob_done)
  1023. sas_phy->oob_mode = SATA_OOB_MODE;
  1024. phy->frame_rcvd_size =
  1025. sizeof(struct dev_to_host_fis);
  1026. mvs_get_d2h_reg(mvi, i, id);
  1027. } else {
  1028. u32 tmp;
  1029. dev_printk(KERN_DEBUG, mvi->dev,
  1030. "Phy%d : No sig fis\n", i);
  1031. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  1032. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  1033. tmp | PHYEV_SIG_FIS);
  1034. phy->phy_attached = 0;
  1035. phy->phy_type &= ~PORT_TYPE_SATA;
  1036. MVS_CHIP_DISP->phy_reset(mvi, i, 0);
  1037. goto out_done;
  1038. }
  1039. } else if (phy->phy_type & PORT_TYPE_SAS
  1040. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  1041. phy->phy_attached = 1;
  1042. phy->identify.device_type =
  1043. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  1044. if (phy->identify.device_type == SAS_END_DEV)
  1045. phy->identify.target_port_protocols =
  1046. SAS_PROTOCOL_SSP;
  1047. else if (phy->identify.device_type != NO_DEVICE)
  1048. phy->identify.target_port_protocols =
  1049. SAS_PROTOCOL_SMP;
  1050. if (oob_done)
  1051. sas_phy->oob_mode = SAS_OOB_MODE;
  1052. phy->frame_rcvd_size =
  1053. sizeof(struct sas_identify_frame);
  1054. }
  1055. memcpy(sas_phy->attached_sas_addr,
  1056. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  1057. if (MVS_CHIP_DISP->phy_work_around)
  1058. MVS_CHIP_DISP->phy_work_around(mvi, i);
  1059. }
  1060. mv_dprintk("port %d attach dev info is %x\n",
  1061. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  1062. mv_dprintk("port %d attach sas addr is %llx\n",
  1063. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  1064. out_done:
  1065. if (get_st)
  1066. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  1067. }
  1068. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  1069. {
  1070. struct sas_ha_struct *sas_ha = sas_phy->ha;
  1071. struct mvs_info *mvi = NULL; int i = 0, hi;
  1072. struct mvs_phy *phy = sas_phy->lldd_phy;
  1073. struct asd_sas_port *sas_port = sas_phy->port;
  1074. struct mvs_port *port;
  1075. unsigned long flags = 0;
  1076. if (!sas_port)
  1077. return;
  1078. while (sas_ha->sas_phy[i]) {
  1079. if (sas_ha->sas_phy[i] == sas_phy)
  1080. break;
  1081. i++;
  1082. }
  1083. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  1084. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  1085. if (sas_port->id >= mvi->chip->n_phy)
  1086. port = &mvi->port[sas_port->id - mvi->chip->n_phy];
  1087. else
  1088. port = &mvi->port[sas_port->id];
  1089. if (lock)
  1090. spin_lock_irqsave(&mvi->lock, flags);
  1091. port->port_attached = 1;
  1092. phy->port = port;
  1093. if (phy->phy_type & PORT_TYPE_SAS) {
  1094. port->wide_port_phymap = sas_port->phy_mask;
  1095. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  1096. mvs_update_wideport(mvi, sas_phy->id);
  1097. }
  1098. if (lock)
  1099. spin_unlock_irqrestore(&mvi->lock, flags);
  1100. }
  1101. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  1102. {
  1103. struct domain_device *dev;
  1104. struct mvs_phy *phy = sas_phy->lldd_phy;
  1105. struct mvs_info *mvi = phy->mvi;
  1106. struct asd_sas_port *port = sas_phy->port;
  1107. int phy_no = 0;
  1108. while (phy != &mvi->phy[phy_no]) {
  1109. phy_no++;
  1110. if (phy_no >= MVS_MAX_PHYS)
  1111. return;
  1112. }
  1113. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  1114. mvs_do_release_task(phy->mvi, phy_no, NULL);
  1115. }
  1116. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  1117. {
  1118. mvs_port_notify_formed(sas_phy, 1);
  1119. }
  1120. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  1121. {
  1122. mvs_port_notify_deformed(sas_phy, 1);
  1123. }
  1124. struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  1125. {
  1126. u32 dev;
  1127. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  1128. if (mvi->devices[dev].dev_type == NO_DEVICE) {
  1129. mvi->devices[dev].device_id = dev;
  1130. return &mvi->devices[dev];
  1131. }
  1132. }
  1133. if (dev == MVS_MAX_DEVICES)
  1134. mv_printk("max support %d devices, ignore ..\n",
  1135. MVS_MAX_DEVICES);
  1136. return NULL;
  1137. }
  1138. void mvs_free_dev(struct mvs_device *mvi_dev)
  1139. {
  1140. u32 id = mvi_dev->device_id;
  1141. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1142. mvi_dev->device_id = id;
  1143. mvi_dev->dev_type = NO_DEVICE;
  1144. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1145. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1146. }
  1147. int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1148. {
  1149. unsigned long flags = 0;
  1150. int res = 0;
  1151. struct mvs_info *mvi = NULL;
  1152. struct domain_device *parent_dev = dev->parent;
  1153. struct mvs_device *mvi_device;
  1154. mvi = mvs_find_dev_mvi(dev);
  1155. if (lock)
  1156. spin_lock_irqsave(&mvi->lock, flags);
  1157. mvi_device = mvs_alloc_dev(mvi);
  1158. if (!mvi_device) {
  1159. res = -1;
  1160. goto found_out;
  1161. }
  1162. dev->lldd_dev = mvi_device;
  1163. mvi_device->dev_status = MVS_DEV_NORMAL;
  1164. mvi_device->dev_type = dev->dev_type;
  1165. mvi_device->mvi_info = mvi;
  1166. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1167. int phy_id;
  1168. u8 phy_num = parent_dev->ex_dev.num_phys;
  1169. struct ex_phy *phy;
  1170. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1171. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1172. if (SAS_ADDR(phy->attached_sas_addr) ==
  1173. SAS_ADDR(dev->sas_addr)) {
  1174. mvi_device->attached_phy = phy_id;
  1175. break;
  1176. }
  1177. }
  1178. if (phy_id == phy_num) {
  1179. mv_printk("Error: no attached dev:%016llx"
  1180. "at ex:%016llx.\n",
  1181. SAS_ADDR(dev->sas_addr),
  1182. SAS_ADDR(parent_dev->sas_addr));
  1183. res = -1;
  1184. }
  1185. }
  1186. found_out:
  1187. if (lock)
  1188. spin_unlock_irqrestore(&mvi->lock, flags);
  1189. return res;
  1190. }
  1191. int mvs_dev_found(struct domain_device *dev)
  1192. {
  1193. return mvs_dev_found_notify(dev, 1);
  1194. }
  1195. void mvs_dev_gone_notify(struct domain_device *dev)
  1196. {
  1197. unsigned long flags = 0;
  1198. struct mvs_device *mvi_dev = dev->lldd_dev;
  1199. struct mvs_info *mvi = mvi_dev->mvi_info;
  1200. spin_lock_irqsave(&mvi->lock, flags);
  1201. if (mvi_dev) {
  1202. mv_dprintk("found dev[%d:%x] is gone.\n",
  1203. mvi_dev->device_id, mvi_dev->dev_type);
  1204. mvs_release_task(mvi, dev);
  1205. mvs_free_reg_set(mvi, mvi_dev);
  1206. mvs_free_dev(mvi_dev);
  1207. } else {
  1208. mv_dprintk("found dev has gone.\n");
  1209. }
  1210. dev->lldd_dev = NULL;
  1211. spin_unlock_irqrestore(&mvi->lock, flags);
  1212. }
  1213. void mvs_dev_gone(struct domain_device *dev)
  1214. {
  1215. mvs_dev_gone_notify(dev);
  1216. }
  1217. static struct sas_task *mvs_alloc_task(void)
  1218. {
  1219. struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
  1220. if (task) {
  1221. INIT_LIST_HEAD(&task->list);
  1222. spin_lock_init(&task->task_state_lock);
  1223. task->task_state_flags = SAS_TASK_STATE_PENDING;
  1224. init_timer(&task->timer);
  1225. init_completion(&task->completion);
  1226. }
  1227. return task;
  1228. }
  1229. static void mvs_free_task(struct sas_task *task)
  1230. {
  1231. if (task) {
  1232. BUG_ON(!list_empty(&task->list));
  1233. kfree(task);
  1234. }
  1235. }
  1236. static void mvs_task_done(struct sas_task *task)
  1237. {
  1238. if (!del_timer(&task->timer))
  1239. return;
  1240. complete(&task->completion);
  1241. }
  1242. static void mvs_tmf_timedout(unsigned long data)
  1243. {
  1244. struct sas_task *task = (struct sas_task *)data;
  1245. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1246. complete(&task->completion);
  1247. }
  1248. /* XXX */
  1249. #define MVS_TASK_TIMEOUT 20
  1250. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1251. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1252. {
  1253. int res, retry;
  1254. struct sas_task *task = NULL;
  1255. for (retry = 0; retry < 3; retry++) {
  1256. task = mvs_alloc_task();
  1257. if (!task)
  1258. return -ENOMEM;
  1259. task->dev = dev;
  1260. task->task_proto = dev->tproto;
  1261. memcpy(&task->ssp_task, parameter, para_len);
  1262. task->task_done = mvs_task_done;
  1263. task->timer.data = (unsigned long) task;
  1264. task->timer.function = mvs_tmf_timedout;
  1265. task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1266. add_timer(&task->timer);
  1267. res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
  1268. if (res) {
  1269. del_timer(&task->timer);
  1270. mv_printk("executing internel task failed:%d\n", res);
  1271. goto ex_err;
  1272. }
  1273. wait_for_completion(&task->completion);
  1274. res = -TMF_RESP_FUNC_FAILED;
  1275. /* Even TMF timed out, return direct. */
  1276. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1277. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1278. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1279. goto ex_err;
  1280. }
  1281. }
  1282. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1283. task->task_status.stat == SAM_STAT_GOOD) {
  1284. res = TMF_RESP_FUNC_COMPLETE;
  1285. break;
  1286. }
  1287. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1288. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1289. /* no error, but return the number of bytes of
  1290. * underrun */
  1291. res = task->task_status.residual;
  1292. break;
  1293. }
  1294. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1295. task->task_status.stat == SAS_DATA_OVERRUN) {
  1296. mv_dprintk("blocked task error.\n");
  1297. res = -EMSGSIZE;
  1298. break;
  1299. } else {
  1300. mv_dprintk(" task to dev %016llx response: 0x%x "
  1301. "status 0x%x\n",
  1302. SAS_ADDR(dev->sas_addr),
  1303. task->task_status.resp,
  1304. task->task_status.stat);
  1305. mvs_free_task(task);
  1306. task = NULL;
  1307. }
  1308. }
  1309. ex_err:
  1310. BUG_ON(retry == 3 && task != NULL);
  1311. if (task != NULL)
  1312. mvs_free_task(task);
  1313. return res;
  1314. }
  1315. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1316. u8 *lun, struct mvs_tmf_task *tmf)
  1317. {
  1318. struct sas_ssp_task ssp_task;
  1319. DECLARE_COMPLETION_ONSTACK(completion);
  1320. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1321. return TMF_RESP_FUNC_ESUPP;
  1322. strncpy((u8 *)&ssp_task.LUN, lun, 8);
  1323. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1324. sizeof(ssp_task), tmf);
  1325. }
  1326. /* Standard mandates link reset for ATA (type 0)
  1327. and hard reset for SSP (type 1) , only for RECOVERY */
  1328. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1329. {
  1330. int rc;
  1331. struct sas_phy *phy = sas_find_local_phy(dev);
  1332. int reset_type = (dev->dev_type == SATA_DEV ||
  1333. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1334. rc = sas_phy_reset(phy, reset_type);
  1335. msleep(2000);
  1336. return rc;
  1337. }
  1338. /* mandatory SAM-3 */
  1339. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1340. {
  1341. unsigned long flags;
  1342. int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
  1343. struct mvs_tmf_task tmf_task;
  1344. struct mvs_device * mvi_dev = dev->lldd_dev;
  1345. struct mvs_info *mvi = mvi_dev->mvi_info;
  1346. tmf_task.tmf = TMF_LU_RESET;
  1347. mvi_dev->dev_status = MVS_DEV_EH;
  1348. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1349. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1350. num = mvs_find_dev_phyno(dev, phyno);
  1351. spin_lock_irqsave(&mvi->lock, flags);
  1352. for (i = 0; i < num; i++)
  1353. mvs_release_task(mvi, dev);
  1354. spin_unlock_irqrestore(&mvi->lock, flags);
  1355. }
  1356. /* If failed, fall-through I_T_Nexus reset */
  1357. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1358. mvi_dev->device_id, rc);
  1359. return rc;
  1360. }
  1361. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1362. {
  1363. unsigned long flags;
  1364. int rc = TMF_RESP_FUNC_FAILED;
  1365. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1366. struct mvs_info *mvi = mvi_dev->mvi_info;
  1367. if (mvi_dev->dev_status != MVS_DEV_EH)
  1368. return TMF_RESP_FUNC_COMPLETE;
  1369. rc = mvs_debug_I_T_nexus_reset(dev);
  1370. mv_printk("%s for device[%x]:rc= %d\n",
  1371. __func__, mvi_dev->device_id, rc);
  1372. /* housekeeper */
  1373. spin_lock_irqsave(&mvi->lock, flags);
  1374. mvs_release_task(mvi, dev);
  1375. spin_unlock_irqrestore(&mvi->lock, flags);
  1376. return rc;
  1377. }
  1378. /* optional SAM-3 */
  1379. int mvs_query_task(struct sas_task *task)
  1380. {
  1381. u32 tag;
  1382. struct scsi_lun lun;
  1383. struct mvs_tmf_task tmf_task;
  1384. int rc = TMF_RESP_FUNC_FAILED;
  1385. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1386. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1387. struct domain_device *dev = task->dev;
  1388. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1389. struct mvs_info *mvi = mvi_dev->mvi_info;
  1390. int_to_scsilun(cmnd->device->lun, &lun);
  1391. rc = mvs_find_tag(mvi, task, &tag);
  1392. if (rc == 0) {
  1393. rc = TMF_RESP_FUNC_FAILED;
  1394. return rc;
  1395. }
  1396. tmf_task.tmf = TMF_QUERY_TASK;
  1397. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1398. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1399. switch (rc) {
  1400. /* The task is still in Lun, release it then */
  1401. case TMF_RESP_FUNC_SUCC:
  1402. /* The task is not in Lun or failed, reset the phy */
  1403. case TMF_RESP_FUNC_FAILED:
  1404. case TMF_RESP_FUNC_COMPLETE:
  1405. break;
  1406. default:
  1407. rc = TMF_RESP_FUNC_COMPLETE;
  1408. break;
  1409. }
  1410. }
  1411. mv_printk("%s:rc= %d\n", __func__, rc);
  1412. return rc;
  1413. }
  1414. /* mandatory SAM-3, still need free task/slot info */
  1415. int mvs_abort_task(struct sas_task *task)
  1416. {
  1417. struct scsi_lun lun;
  1418. struct mvs_tmf_task tmf_task;
  1419. struct domain_device *dev = task->dev;
  1420. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1421. struct mvs_info *mvi;
  1422. int rc = TMF_RESP_FUNC_FAILED;
  1423. unsigned long flags;
  1424. u32 tag;
  1425. if (!mvi_dev) {
  1426. mv_printk("%s:%d TMF_RESP_FUNC_FAILED\n", __func__, __LINE__);
  1427. rc = TMF_RESP_FUNC_FAILED;
  1428. }
  1429. mvi = mvi_dev->mvi_info;
  1430. spin_lock_irqsave(&task->task_state_lock, flags);
  1431. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1432. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1433. rc = TMF_RESP_FUNC_COMPLETE;
  1434. goto out;
  1435. }
  1436. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1437. mvi_dev->dev_status = MVS_DEV_EH;
  1438. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1439. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1440. int_to_scsilun(cmnd->device->lun, &lun);
  1441. rc = mvs_find_tag(mvi, task, &tag);
  1442. if (rc == 0) {
  1443. mv_printk("No such tag in %s\n", __func__);
  1444. rc = TMF_RESP_FUNC_FAILED;
  1445. return rc;
  1446. }
  1447. tmf_task.tmf = TMF_ABORT_TASK;
  1448. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1449. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1450. /* if successful, clear the task and callback forwards.*/
  1451. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1452. u32 slot_no;
  1453. struct mvs_slot_info *slot;
  1454. if (task->lldd_task) {
  1455. slot = task->lldd_task;
  1456. slot_no = (u32) (slot - mvi->slot_info);
  1457. spin_lock_irqsave(&mvi->lock, flags);
  1458. mvs_slot_complete(mvi, slot_no, 1);
  1459. spin_unlock_irqrestore(&mvi->lock, flags);
  1460. }
  1461. }
  1462. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1463. task->task_proto & SAS_PROTOCOL_STP) {
  1464. /* to do free register_set */
  1465. if (SATA_DEV == dev->dev_type) {
  1466. struct mvs_slot_info *slot = task->lldd_task;
  1467. struct task_status_struct *tstat;
  1468. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1469. tstat = &task->task_status;
  1470. mv_dprintk(KERN_DEBUG "mv_abort_task() mvi=%p task=%p "
  1471. "slot=%p slot_idx=x%x\n",
  1472. mvi, task, slot, slot_idx);
  1473. tstat->stat = SAS_ABORTED_TASK;
  1474. if (mvi_dev && mvi_dev->running_req)
  1475. mvi_dev->running_req--;
  1476. if (sas_protocol_ata(task->task_proto))
  1477. mvs_free_reg_set(mvi, mvi_dev);
  1478. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1479. return -1;
  1480. }
  1481. } else {
  1482. /* SMP */
  1483. }
  1484. out:
  1485. if (rc != TMF_RESP_FUNC_COMPLETE)
  1486. mv_printk("%s:rc= %d\n", __func__, rc);
  1487. return rc;
  1488. }
  1489. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1490. {
  1491. int rc = TMF_RESP_FUNC_FAILED;
  1492. struct mvs_tmf_task tmf_task;
  1493. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1494. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1495. return rc;
  1496. }
  1497. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1498. {
  1499. int rc = TMF_RESP_FUNC_FAILED;
  1500. struct mvs_tmf_task tmf_task;
  1501. tmf_task.tmf = TMF_CLEAR_ACA;
  1502. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1503. return rc;
  1504. }
  1505. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1506. {
  1507. int rc = TMF_RESP_FUNC_FAILED;
  1508. struct mvs_tmf_task tmf_task;
  1509. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1510. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1511. return rc;
  1512. }
  1513. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1514. u32 slot_idx, int err)
  1515. {
  1516. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1517. struct task_status_struct *tstat = &task->task_status;
  1518. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1519. int stat = SAM_STAT_GOOD;
  1520. resp->frame_len = sizeof(struct dev_to_host_fis);
  1521. memcpy(&resp->ending_fis[0],
  1522. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1523. sizeof(struct dev_to_host_fis));
  1524. tstat->buf_valid_size = sizeof(*resp);
  1525. if (unlikely(err)) {
  1526. if (unlikely(err & CMD_ISS_STPD))
  1527. stat = SAS_OPEN_REJECT;
  1528. else
  1529. stat = SAS_PROTO_RESPONSE;
  1530. }
  1531. return stat;
  1532. }
  1533. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1534. u32 slot_idx)
  1535. {
  1536. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1537. int stat;
  1538. u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
  1539. u32 tfs = 0;
  1540. enum mvs_port_type type = PORT_TYPE_SAS;
  1541. if (err_dw0 & CMD_ISS_STPD)
  1542. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1543. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1544. stat = SAM_STAT_CHECK_CONDITION;
  1545. switch (task->task_proto) {
  1546. case SAS_PROTOCOL_SSP:
  1547. stat = SAS_ABORTED_TASK;
  1548. break;
  1549. case SAS_PROTOCOL_SMP:
  1550. stat = SAM_STAT_CHECK_CONDITION;
  1551. break;
  1552. case SAS_PROTOCOL_SATA:
  1553. case SAS_PROTOCOL_STP:
  1554. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1555. {
  1556. if (err_dw0 == 0x80400002)
  1557. mv_printk("find reserved error, why?\n");
  1558. task->ata_task.use_ncq = 0;
  1559. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1560. }
  1561. break;
  1562. default:
  1563. break;
  1564. }
  1565. return stat;
  1566. }
  1567. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1568. {
  1569. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1570. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1571. struct sas_task *task = slot->task;
  1572. struct mvs_device *mvi_dev = NULL;
  1573. struct task_status_struct *tstat;
  1574. struct domain_device *dev;
  1575. u32 aborted;
  1576. void *to;
  1577. enum exec_status sts;
  1578. if (mvi->exp_req)
  1579. mvi->exp_req--;
  1580. if (unlikely(!task || !task->lldd_task || !task->dev))
  1581. return -1;
  1582. tstat = &task->task_status;
  1583. dev = task->dev;
  1584. mvi_dev = dev->lldd_dev;
  1585. mvs_hba_cq_dump(mvi);
  1586. spin_lock(&task->task_state_lock);
  1587. task->task_state_flags &=
  1588. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1589. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1590. /* race condition*/
  1591. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1592. spin_unlock(&task->task_state_lock);
  1593. memset(tstat, 0, sizeof(*tstat));
  1594. tstat->resp = SAS_TASK_COMPLETE;
  1595. if (unlikely(aborted)) {
  1596. tstat->stat = SAS_ABORTED_TASK;
  1597. if (mvi_dev && mvi_dev->running_req)
  1598. mvi_dev->running_req--;
  1599. if (sas_protocol_ata(task->task_proto))
  1600. mvs_free_reg_set(mvi, mvi_dev);
  1601. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1602. return -1;
  1603. }
  1604. if (unlikely(!mvi_dev || flags)) {
  1605. if (!mvi_dev)
  1606. mv_dprintk("port has not device.\n");
  1607. tstat->stat = SAS_PHY_DOWN;
  1608. goto out;
  1609. }
  1610. /* error info record present */
  1611. if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
  1612. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1613. tstat->resp = SAS_TASK_COMPLETE;
  1614. goto out;
  1615. }
  1616. switch (task->task_proto) {
  1617. case SAS_PROTOCOL_SSP:
  1618. /* hw says status == 0, datapres == 0 */
  1619. if (rx_desc & RXQ_GOOD) {
  1620. tstat->stat = SAM_STAT_GOOD;
  1621. tstat->resp = SAS_TASK_COMPLETE;
  1622. }
  1623. /* response frame present */
  1624. else if (rx_desc & RXQ_RSP) {
  1625. struct ssp_response_iu *iu = slot->response +
  1626. sizeof(struct mvs_err_info);
  1627. sas_ssp_task_response(mvi->dev, task, iu);
  1628. } else
  1629. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1630. break;
  1631. case SAS_PROTOCOL_SMP: {
  1632. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1633. tstat->stat = SAM_STAT_GOOD;
  1634. to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
  1635. memcpy(to + sg_resp->offset,
  1636. slot->response + sizeof(struct mvs_err_info),
  1637. sg_dma_len(sg_resp));
  1638. kunmap_atomic(to, KM_IRQ0);
  1639. break;
  1640. }
  1641. case SAS_PROTOCOL_SATA:
  1642. case SAS_PROTOCOL_STP:
  1643. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1644. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1645. break;
  1646. }
  1647. default:
  1648. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1649. break;
  1650. }
  1651. if (!slot->port->port_attached) {
  1652. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1653. tstat->stat = SAS_PHY_DOWN;
  1654. }
  1655. out:
  1656. if (mvi_dev && mvi_dev->running_req) {
  1657. mvi_dev->running_req--;
  1658. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1659. mvs_free_reg_set(mvi, mvi_dev);
  1660. }
  1661. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1662. sts = tstat->stat;
  1663. spin_unlock(&mvi->lock);
  1664. if (task->task_done)
  1665. task->task_done(task);
  1666. else
  1667. mv_dprintk("why has not task_done.\n");
  1668. spin_lock(&mvi->lock);
  1669. return sts;
  1670. }
  1671. void mvs_do_release_task(struct mvs_info *mvi,
  1672. int phy_no, struct domain_device *dev)
  1673. {
  1674. u32 slot_idx;
  1675. struct mvs_phy *phy;
  1676. struct mvs_port *port;
  1677. struct mvs_slot_info *slot, *slot2;
  1678. phy = &mvi->phy[phy_no];
  1679. port = phy->port;
  1680. if (!port)
  1681. return;
  1682. /* clean cmpl queue in case request is already finished */
  1683. mvs_int_rx(mvi, false);
  1684. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1685. struct sas_task *task;
  1686. slot_idx = (u32) (slot - mvi->slot_info);
  1687. task = slot->task;
  1688. if (dev && task->dev != dev)
  1689. continue;
  1690. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1691. slot_idx, slot->slot_tag, task);
  1692. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1693. mvs_slot_complete(mvi, slot_idx, 1);
  1694. }
  1695. }
  1696. void mvs_release_task(struct mvs_info *mvi,
  1697. struct domain_device *dev)
  1698. {
  1699. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1700. /* housekeeper */
  1701. num = mvs_find_dev_phyno(dev, phyno);
  1702. for (i = 0; i < num; i++)
  1703. mvs_do_release_task(mvi, phyno[i], dev);
  1704. }
  1705. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1706. {
  1707. phy->phy_attached = 0;
  1708. phy->att_dev_info = 0;
  1709. phy->att_dev_sas_addr = 0;
  1710. }
  1711. static void mvs_work_queue(struct work_struct *work)
  1712. {
  1713. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1714. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1715. struct mvs_info *mvi = mwq->mvi;
  1716. unsigned long flags;
  1717. spin_lock_irqsave(&mvi->lock, flags);
  1718. if (mwq->handler & PHY_PLUG_EVENT) {
  1719. u32 phy_no = (unsigned long) mwq->data;
  1720. struct sas_ha_struct *sas_ha = mvi->sas;
  1721. struct mvs_phy *phy = &mvi->phy[phy_no];
  1722. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1723. if (phy->phy_event & PHY_PLUG_OUT) {
  1724. u32 tmp;
  1725. struct sas_identify_frame *id;
  1726. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1727. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1728. phy->phy_event &= ~PHY_PLUG_OUT;
  1729. if (!(tmp & PHY_READY_MASK)) {
  1730. sas_phy_disconnected(sas_phy);
  1731. mvs_phy_disconnected(phy);
  1732. sas_ha->notify_phy_event(sas_phy,
  1733. PHYE_LOSS_OF_SIGNAL);
  1734. mv_dprintk("phy%d Removed Device\n", phy_no);
  1735. } else {
  1736. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1737. mvs_update_phyinfo(mvi, phy_no, 1);
  1738. mvs_bytes_dmaed(mvi, phy_no);
  1739. mvs_port_notify_formed(sas_phy, 0);
  1740. mv_dprintk("phy%d Attached Device\n", phy_no);
  1741. }
  1742. }
  1743. }
  1744. list_del(&mwq->entry);
  1745. spin_unlock_irqrestore(&mvi->lock, flags);
  1746. kfree(mwq);
  1747. }
  1748. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1749. {
  1750. struct mvs_wq *mwq;
  1751. int ret = 0;
  1752. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1753. if (mwq) {
  1754. mwq->mvi = mvi;
  1755. mwq->data = data;
  1756. mwq->handler = handler;
  1757. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1758. list_add_tail(&mwq->entry, &mvi->wq_list);
  1759. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1760. } else
  1761. ret = -ENOMEM;
  1762. return ret;
  1763. }
  1764. static void mvs_sig_time_out(unsigned long tphy)
  1765. {
  1766. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1767. struct mvs_info *mvi = phy->mvi;
  1768. u8 phy_no;
  1769. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1770. if (&mvi->phy[phy_no] == phy) {
  1771. mv_dprintk("Get signature time out, reset phy %d\n",
  1772. phy_no+mvi->id*mvi->chip->n_phy);
  1773. MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
  1774. }
  1775. }
  1776. }
  1777. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  1778. {
  1779. if (phy->timer.function)
  1780. del_timer(&phy->timer);
  1781. phy->timer.function = NULL;
  1782. }
  1783. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1784. {
  1785. u32 tmp;
  1786. struct sas_ha_struct *sas_ha = mvi->sas;
  1787. struct mvs_phy *phy = &mvi->phy[phy_no];
  1788. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1789. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1790. mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1791. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1792. mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1793. phy->irq_status);
  1794. /*
  1795. * events is port event now ,
  1796. * we need check the interrupt status which belongs to per port.
  1797. */
  1798. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1799. mv_dprintk("port %d STP decoding error.\n",
  1800. phy_no + mvi->id*mvi->chip->n_phy);
  1801. }
  1802. if (phy->irq_status & PHYEV_POOF) {
  1803. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1804. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1805. int ready;
  1806. mvs_do_release_task(mvi, phy_no, NULL);
  1807. phy->phy_event |= PHY_PLUG_OUT;
  1808. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1809. mvs_handle_event(mvi,
  1810. (void *)(unsigned long)phy_no,
  1811. PHY_PLUG_EVENT);
  1812. ready = mvs_is_phy_ready(mvi, phy_no);
  1813. if (!ready)
  1814. mv_dprintk("phy%d Unplug Notice\n",
  1815. phy_no +
  1816. mvi->id * mvi->chip->n_phy);
  1817. if (ready || dev_sata) {
  1818. if (MVS_CHIP_DISP->stp_reset)
  1819. MVS_CHIP_DISP->stp_reset(mvi,
  1820. phy_no);
  1821. else
  1822. MVS_CHIP_DISP->phy_reset(mvi,
  1823. phy_no, 0);
  1824. return;
  1825. }
  1826. }
  1827. }
  1828. if (phy->irq_status & PHYEV_COMWAKE) {
  1829. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1830. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1831. tmp | PHYEV_SIG_FIS);
  1832. if (phy->timer.function == NULL) {
  1833. phy->timer.data = (unsigned long)phy;
  1834. phy->timer.function = mvs_sig_time_out;
  1835. phy->timer.expires = jiffies + 10*HZ;
  1836. add_timer(&phy->timer);
  1837. }
  1838. }
  1839. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1840. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1841. mvs_sig_remove_timer(phy);
  1842. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1843. if (phy->phy_status) {
  1844. mdelay(10);
  1845. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1846. if (phy->phy_type & PORT_TYPE_SATA) {
  1847. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1848. mvi, phy_no);
  1849. tmp &= ~PHYEV_SIG_FIS;
  1850. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1851. phy_no, tmp);
  1852. }
  1853. mvs_update_phyinfo(mvi, phy_no, 0);
  1854. if (phy->phy_type & PORT_TYPE_SAS) {
  1855. MVS_CHIP_DISP->phy_reset(mvi, phy_no, 2);
  1856. mdelay(10);
  1857. }
  1858. mvs_bytes_dmaed(mvi, phy_no);
  1859. /* whether driver is going to handle hot plug */
  1860. if (phy->phy_event & PHY_PLUG_OUT) {
  1861. mvs_port_notify_formed(sas_phy, 0);
  1862. phy->phy_event &= ~PHY_PLUG_OUT;
  1863. }
  1864. } else {
  1865. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1866. phy_no + mvi->id*mvi->chip->n_phy);
  1867. }
  1868. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1869. mv_dprintk("port %d broadcast change.\n",
  1870. phy_no + mvi->id*mvi->chip->n_phy);
  1871. /* exception for Samsung disk drive*/
  1872. mdelay(1000);
  1873. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  1874. }
  1875. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1876. }
  1877. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1878. {
  1879. u32 rx_prod_idx, rx_desc;
  1880. bool attn = false;
  1881. /* the first dword in the RX ring is special: it contains
  1882. * a mirror of the hardware's RX producer index, so that
  1883. * we don't have to stall the CPU reading that register.
  1884. * The actual RX ring is offset by one dword, due to this.
  1885. */
  1886. rx_prod_idx = mvi->rx_cons;
  1887. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1888. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1889. return 0;
  1890. /* The CMPL_Q may come late, read from register and try again
  1891. * note: if coalescing is enabled,
  1892. * it will need to read from register every time for sure
  1893. */
  1894. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1895. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1896. if (mvi->rx_cons == rx_prod_idx)
  1897. return 0;
  1898. while (mvi->rx_cons != rx_prod_idx) {
  1899. /* increment our internal RX consumer pointer */
  1900. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1901. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1902. if (likely(rx_desc & RXQ_DONE))
  1903. mvs_slot_complete(mvi, rx_desc, 0);
  1904. if (rx_desc & RXQ_ATTN) {
  1905. attn = true;
  1906. } else if (rx_desc & RXQ_ERR) {
  1907. if (!(rx_desc & RXQ_DONE))
  1908. mvs_slot_complete(mvi, rx_desc, 0);
  1909. } else if (rx_desc & RXQ_SLOT_RESET) {
  1910. mvs_slot_free(mvi, rx_desc);
  1911. }
  1912. }
  1913. if (attn && self_clear)
  1914. MVS_CHIP_DISP->int_full(mvi);
  1915. return 0;
  1916. }