bnx2fc_hwi.c 52 KB

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  1. /* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2010 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation.
  10. *
  11. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  12. */
  13. #include "bnx2fc.h"
  14. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  15. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  16. struct fcoe_kcqe *new_cqe_kcqe);
  17. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *ofld_kcqe);
  19. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  22. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  23. struct fcoe_kcqe *conn_destroy);
  24. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  25. {
  26. struct fcoe_kwqe_stat stat_req;
  27. struct kwqe *kwqe_arr[2];
  28. int num_kwqes = 1;
  29. int rc = 0;
  30. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  31. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  32. stat_req.hdr.flags =
  33. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  34. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  35. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  36. kwqe_arr[0] = (struct kwqe *) &stat_req;
  37. if (hba->cnic && hba->cnic->submit_kwqes)
  38. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  39. return rc;
  40. }
  41. /**
  42. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  43. *
  44. * @hba: adapter structure pointer
  45. *
  46. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  47. * with the f/w.
  48. *
  49. */
  50. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  51. {
  52. struct fcoe_kwqe_init1 fcoe_init1;
  53. struct fcoe_kwqe_init2 fcoe_init2;
  54. struct fcoe_kwqe_init3 fcoe_init3;
  55. struct kwqe *kwqe_arr[3];
  56. int num_kwqes = 3;
  57. int rc = 0;
  58. if (!hba->cnic) {
  59. printk(KERN_ALERT PFX "hba->cnic NULL during fcoe fw init\n");
  60. return -ENODEV;
  61. }
  62. /* fill init1 KWQE */
  63. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  64. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  65. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  66. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  67. fcoe_init1.num_tasks = BNX2FC_MAX_TASKS;
  68. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  69. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  70. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  71. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  72. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  73. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  74. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  75. fcoe_init1.task_list_pbl_addr_hi =
  76. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  77. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  78. fcoe_init1.flags = (PAGE_SHIFT <<
  79. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  80. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  81. /* fill init2 KWQE */
  82. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  83. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  84. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  85. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  86. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  87. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  88. ((u64) hba->hash_tbl_pbl_dma >> 32);
  89. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  90. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  91. ((u64) hba->t2_hash_tbl_dma >> 32);
  92. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  93. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  94. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  95. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  96. /* fill init3 KWQE */
  97. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  98. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  99. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  100. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  101. fcoe_init3.error_bit_map_lo = 0xffffffff;
  102. fcoe_init3.error_bit_map_hi = 0xffffffff;
  103. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  104. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  105. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  106. if (hba->cnic && hba->cnic->submit_kwqes)
  107. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  108. return rc;
  109. }
  110. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  111. {
  112. struct fcoe_kwqe_destroy fcoe_destroy;
  113. struct kwqe *kwqe_arr[2];
  114. int num_kwqes = 1;
  115. int rc = -1;
  116. /* fill destroy KWQE */
  117. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  118. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  119. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  120. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  121. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  122. if (hba->cnic && hba->cnic->submit_kwqes)
  123. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  124. return rc;
  125. }
  126. /**
  127. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  128. *
  129. * @port: port structure pointer
  130. * @tgt: bnx2fc_rport structure pointer
  131. */
  132. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  133. struct bnx2fc_rport *tgt)
  134. {
  135. struct fc_lport *lport = port->lport;
  136. struct bnx2fc_hba *hba = port->priv;
  137. struct kwqe *kwqe_arr[4];
  138. struct fcoe_kwqe_conn_offload1 ofld_req1;
  139. struct fcoe_kwqe_conn_offload2 ofld_req2;
  140. struct fcoe_kwqe_conn_offload3 ofld_req3;
  141. struct fcoe_kwqe_conn_offload4 ofld_req4;
  142. struct fc_rport_priv *rdata = tgt->rdata;
  143. struct fc_rport *rport = tgt->rport;
  144. int num_kwqes = 4;
  145. u32 port_id;
  146. int rc = 0;
  147. u16 conn_id;
  148. /* Initialize offload request 1 structure */
  149. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  150. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  151. ofld_req1.hdr.flags =
  152. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  153. conn_id = (u16)tgt->fcoe_conn_id;
  154. ofld_req1.fcoe_conn_id = conn_id;
  155. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  156. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  157. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  158. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  159. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  160. ofld_req1.rq_first_pbe_addr_hi =
  161. (u32)((u64) tgt->rq_dma >> 32);
  162. ofld_req1.rq_prod = 0x8000;
  163. /* Initialize offload request 2 structure */
  164. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  165. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  166. ofld_req2.hdr.flags =
  167. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  168. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  169. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  170. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  171. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  172. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  173. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  174. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  175. /* Initialize offload request 3 structure */
  176. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  177. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  178. ofld_req3.hdr.flags =
  179. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  180. ofld_req3.vlan_tag = hba->vlan_id <<
  181. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  182. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  183. port_id = fc_host_port_id(lport->host);
  184. if (port_id == 0) {
  185. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  186. return -EINVAL;
  187. }
  188. /*
  189. * Store s_id of the initiator for further reference. This will
  190. * be used during disable/destroy during linkdown processing as
  191. * when the lport is reset, the port_id also is reset to 0
  192. */
  193. tgt->sid = port_id;
  194. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  195. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  196. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  197. port_id = rport->port_id;
  198. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  199. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  200. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  201. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  202. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  203. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  204. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  205. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  206. ofld_req3.rx_open_seqs_exch_c3 = 1;
  207. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  208. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  209. /* set mul_n_port_ids supported flag to 0, until it is supported */
  210. ofld_req3.flags = 0;
  211. /*
  212. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  213. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  214. */
  215. /* Info from PLOGI response */
  216. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  217. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  218. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  219. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  220. /* vlan flag */
  221. ofld_req3.flags |= (hba->vlan_enabled <<
  222. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  223. /* C2_VALID and ACK flags are not set as they are not suppported */
  224. /* Initialize offload request 4 structure */
  225. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  226. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  227. ofld_req4.hdr.flags =
  228. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  229. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  230. ofld_req4.src_mac_addr_lo32[0] = port->data_src_addr[5];
  231. /* local mac */
  232. ofld_req4.src_mac_addr_lo32[1] = port->data_src_addr[4];
  233. ofld_req4.src_mac_addr_lo32[2] = port->data_src_addr[3];
  234. ofld_req4.src_mac_addr_lo32[3] = port->data_src_addr[2];
  235. ofld_req4.src_mac_addr_hi16[0] = port->data_src_addr[1];
  236. ofld_req4.src_mac_addr_hi16[1] = port->data_src_addr[0];
  237. ofld_req4.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  238. ofld_req4.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  239. ofld_req4.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  240. ofld_req4.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  241. ofld_req4.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  242. ofld_req4.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  243. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  244. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  245. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  246. ofld_req4.confq_pbl_base_addr_hi =
  247. (u32)((u64) tgt->confq_pbl_dma >> 32);
  248. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  249. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  250. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  251. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  252. if (hba->cnic && hba->cnic->submit_kwqes)
  253. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  254. return rc;
  255. }
  256. /**
  257. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  258. *
  259. * @port: port structure pointer
  260. * @tgt: bnx2fc_rport structure pointer
  261. */
  262. static int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  263. struct bnx2fc_rport *tgt)
  264. {
  265. struct kwqe *kwqe_arr[2];
  266. struct bnx2fc_hba *hba = port->priv;
  267. struct fcoe_kwqe_conn_enable_disable enbl_req;
  268. struct fc_lport *lport = port->lport;
  269. struct fc_rport *rport = tgt->rport;
  270. int num_kwqes = 1;
  271. int rc = 0;
  272. u32 port_id;
  273. memset(&enbl_req, 0x00,
  274. sizeof(struct fcoe_kwqe_conn_enable_disable));
  275. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  276. enbl_req.hdr.flags =
  277. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  278. enbl_req.src_mac_addr_lo32[0] = port->data_src_addr[5];
  279. /* local mac */
  280. enbl_req.src_mac_addr_lo32[1] = port->data_src_addr[4];
  281. enbl_req.src_mac_addr_lo32[2] = port->data_src_addr[3];
  282. enbl_req.src_mac_addr_lo32[3] = port->data_src_addr[2];
  283. enbl_req.src_mac_addr_hi16[0] = port->data_src_addr[1];
  284. enbl_req.src_mac_addr_hi16[1] = port->data_src_addr[0];
  285. enbl_req.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  286. enbl_req.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  287. enbl_req.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  288. enbl_req.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  289. enbl_req.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  290. enbl_req.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  291. port_id = fc_host_port_id(lport->host);
  292. if (port_id != tgt->sid) {
  293. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  294. "sid = 0x%x\n", port_id, tgt->sid);
  295. port_id = tgt->sid;
  296. }
  297. enbl_req.s_id[0] = (port_id & 0x000000FF);
  298. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  299. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  300. port_id = rport->port_id;
  301. enbl_req.d_id[0] = (port_id & 0x000000FF);
  302. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  303. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  304. enbl_req.vlan_tag = hba->vlan_id <<
  305. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  306. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  307. enbl_req.vlan_flag = hba->vlan_enabled;
  308. enbl_req.context_id = tgt->context_id;
  309. enbl_req.conn_id = tgt->fcoe_conn_id;
  310. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  311. if (hba->cnic && hba->cnic->submit_kwqes)
  312. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  313. return rc;
  314. }
  315. /**
  316. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  317. *
  318. * @port: port structure pointer
  319. * @tgt: bnx2fc_rport structure pointer
  320. */
  321. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  322. struct bnx2fc_rport *tgt)
  323. {
  324. struct bnx2fc_hba *hba = port->priv;
  325. struct fcoe_kwqe_conn_enable_disable disable_req;
  326. struct kwqe *kwqe_arr[2];
  327. struct fc_rport *rport = tgt->rport;
  328. int num_kwqes = 1;
  329. int rc = 0;
  330. u32 port_id;
  331. memset(&disable_req, 0x00,
  332. sizeof(struct fcoe_kwqe_conn_enable_disable));
  333. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  334. disable_req.hdr.flags =
  335. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  336. disable_req.src_mac_addr_lo32[0] = port->data_src_addr[5];
  337. disable_req.src_mac_addr_lo32[2] = port->data_src_addr[3];
  338. disable_req.src_mac_addr_lo32[3] = port->data_src_addr[2];
  339. disable_req.src_mac_addr_hi16[0] = port->data_src_addr[1];
  340. disable_req.src_mac_addr_hi16[1] = port->data_src_addr[0];
  341. disable_req.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  342. disable_req.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  343. disable_req.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  344. disable_req.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  345. disable_req.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  346. disable_req.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  347. port_id = tgt->sid;
  348. disable_req.s_id[0] = (port_id & 0x000000FF);
  349. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  350. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  351. port_id = rport->port_id;
  352. disable_req.d_id[0] = (port_id & 0x000000FF);
  353. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  354. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  355. disable_req.context_id = tgt->context_id;
  356. disable_req.conn_id = tgt->fcoe_conn_id;
  357. disable_req.vlan_tag = hba->vlan_id <<
  358. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  359. disable_req.vlan_tag |=
  360. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  361. disable_req.vlan_flag = hba->vlan_enabled;
  362. kwqe_arr[0] = (struct kwqe *) &disable_req;
  363. if (hba->cnic && hba->cnic->submit_kwqes)
  364. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  365. return rc;
  366. }
  367. /**
  368. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  369. *
  370. * @port: port structure pointer
  371. * @tgt: bnx2fc_rport structure pointer
  372. */
  373. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  374. struct bnx2fc_rport *tgt)
  375. {
  376. struct fcoe_kwqe_conn_destroy destroy_req;
  377. struct kwqe *kwqe_arr[2];
  378. int num_kwqes = 1;
  379. int rc = 0;
  380. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  381. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  382. destroy_req.hdr.flags =
  383. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  384. destroy_req.context_id = tgt->context_id;
  385. destroy_req.conn_id = tgt->fcoe_conn_id;
  386. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  387. if (hba->cnic && hba->cnic->submit_kwqes)
  388. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  389. return rc;
  390. }
  391. static void bnx2fc_unsol_els_work(struct work_struct *work)
  392. {
  393. struct bnx2fc_unsol_els *unsol_els;
  394. struct fc_lport *lport;
  395. struct fc_frame *fp;
  396. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  397. lport = unsol_els->lport;
  398. fp = unsol_els->fp;
  399. fc_exch_recv(lport, fp);
  400. kfree(unsol_els);
  401. }
  402. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  403. unsigned char *buf,
  404. u32 frame_len, u16 l2_oxid)
  405. {
  406. struct fcoe_port *port = tgt->port;
  407. struct fc_lport *lport = port->lport;
  408. struct bnx2fc_unsol_els *unsol_els;
  409. struct fc_frame_header *fh;
  410. struct fc_frame *fp;
  411. struct sk_buff *skb;
  412. u32 payload_len;
  413. u32 crc;
  414. u8 op;
  415. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  416. if (!unsol_els) {
  417. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  418. return;
  419. }
  420. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  421. l2_oxid, frame_len);
  422. payload_len = frame_len - sizeof(struct fc_frame_header);
  423. fp = fc_frame_alloc(lport, payload_len);
  424. if (!fp) {
  425. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  426. return;
  427. }
  428. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  429. /* Copy FC Frame header and payload into the frame */
  430. memcpy(fh, buf, frame_len);
  431. if (l2_oxid != FC_XID_UNKNOWN)
  432. fh->fh_ox_id = htons(l2_oxid);
  433. skb = fp_skb(fp);
  434. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  435. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  436. if (fh->fh_type == FC_TYPE_ELS) {
  437. op = fc_frame_payload_op(fp);
  438. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  439. (op == ELS_FAN) || (op == ELS_CSU)) {
  440. /*
  441. * No need to reply for these
  442. * ELS requests
  443. */
  444. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  445. kfree_skb(skb);
  446. return;
  447. }
  448. }
  449. crc = fcoe_fc_crc(fp);
  450. fc_frame_init(fp);
  451. fr_dev(fp) = lport;
  452. fr_sof(fp) = FC_SOF_I3;
  453. fr_eof(fp) = FC_EOF_T;
  454. fr_crc(fp) = cpu_to_le32(~crc);
  455. unsol_els->lport = lport;
  456. unsol_els->fp = fp;
  457. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  458. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  459. } else {
  460. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  461. kfree_skb(skb);
  462. }
  463. }
  464. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  465. {
  466. u8 num_rq;
  467. struct fcoe_err_report_entry *err_entry;
  468. unsigned char *rq_data;
  469. unsigned char *buf = NULL, *buf1;
  470. int i;
  471. u16 xid;
  472. u32 frame_len, len;
  473. struct bnx2fc_cmd *io_req = NULL;
  474. struct fcoe_task_ctx_entry *task, *task_page;
  475. struct bnx2fc_hba *hba = tgt->port->priv;
  476. int task_idx, index;
  477. int rc = 0;
  478. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  479. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  480. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  481. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  482. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  483. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  484. spin_lock_bh(&tgt->tgt_lock);
  485. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  486. spin_unlock_bh(&tgt->tgt_lock);
  487. if (rq_data) {
  488. buf = rq_data;
  489. } else {
  490. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  491. GFP_ATOMIC);
  492. if (!buf1) {
  493. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  494. break;
  495. }
  496. for (i = 0; i < num_rq; i++) {
  497. spin_lock_bh(&tgt->tgt_lock);
  498. rq_data = (unsigned char *)
  499. bnx2fc_get_next_rqe(tgt, 1);
  500. spin_unlock_bh(&tgt->tgt_lock);
  501. len = BNX2FC_RQ_BUF_SZ;
  502. memcpy(buf1, rq_data, len);
  503. buf1 += len;
  504. }
  505. }
  506. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  507. FC_XID_UNKNOWN);
  508. if (buf != rq_data)
  509. kfree(buf);
  510. spin_lock_bh(&tgt->tgt_lock);
  511. bnx2fc_return_rqe(tgt, num_rq);
  512. spin_unlock_bh(&tgt->tgt_lock);
  513. break;
  514. case FCOE_ERROR_DETECTION_CQE_TYPE:
  515. /*
  516. * In case of error reporting CQE a single RQ entry
  517. * is consumed.
  518. */
  519. spin_lock_bh(&tgt->tgt_lock);
  520. num_rq = 1;
  521. err_entry = (struct fcoe_err_report_entry *)
  522. bnx2fc_get_next_rqe(tgt, 1);
  523. xid = err_entry->fc_hdr.ox_id;
  524. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  525. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  526. err_entry->err_warn_bitmap_hi,
  527. err_entry->err_warn_bitmap_lo);
  528. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  529. err_entry->tx_buf_off, err_entry->rx_buf_off);
  530. bnx2fc_return_rqe(tgt, 1);
  531. if (xid > BNX2FC_MAX_XID) {
  532. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  533. xid);
  534. spin_unlock_bh(&tgt->tgt_lock);
  535. break;
  536. }
  537. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  538. index = xid % BNX2FC_TASKS_PER_PAGE;
  539. task_page = (struct fcoe_task_ctx_entry *)
  540. hba->task_ctx[task_idx];
  541. task = &(task_page[index]);
  542. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  543. if (!io_req) {
  544. spin_unlock_bh(&tgt->tgt_lock);
  545. break;
  546. }
  547. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  548. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  549. spin_unlock_bh(&tgt->tgt_lock);
  550. break;
  551. }
  552. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  553. &io_req->req_flags)) {
  554. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  555. "progress.. ignore unsol err\n");
  556. spin_unlock_bh(&tgt->tgt_lock);
  557. break;
  558. }
  559. /*
  560. * If ABTS is already in progress, and FW error is
  561. * received after that, do not cancel the timeout_work
  562. * and let the error recovery continue by explicitly
  563. * logging out the target, when the ABTS eventually
  564. * times out.
  565. */
  566. if (!test_and_set_bit(BNX2FC_FLAG_ISSUE_ABTS,
  567. &io_req->req_flags)) {
  568. /*
  569. * Cancel the timeout_work, as we received IO
  570. * completion with FW error.
  571. */
  572. if (cancel_delayed_work(&io_req->timeout_work))
  573. kref_put(&io_req->refcount,
  574. bnx2fc_cmd_release); /* timer hold */
  575. rc = bnx2fc_initiate_abts(io_req);
  576. if (rc != SUCCESS) {
  577. BNX2FC_IO_DBG(io_req, "err_warn: initiate_abts "
  578. "failed. issue cleanup\n");
  579. rc = bnx2fc_initiate_cleanup(io_req);
  580. BUG_ON(rc);
  581. }
  582. } else
  583. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  584. "in ABTS processing\n", xid);
  585. spin_unlock_bh(&tgt->tgt_lock);
  586. break;
  587. case FCOE_WARNING_DETECTION_CQE_TYPE:
  588. /*
  589. *In case of warning reporting CQE a single RQ entry
  590. * is consumes.
  591. */
  592. spin_lock_bh(&tgt->tgt_lock);
  593. num_rq = 1;
  594. err_entry = (struct fcoe_err_report_entry *)
  595. bnx2fc_get_next_rqe(tgt, 1);
  596. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  597. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  598. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  599. err_entry->err_warn_bitmap_hi,
  600. err_entry->err_warn_bitmap_lo);
  601. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  602. err_entry->tx_buf_off, err_entry->rx_buf_off);
  603. bnx2fc_return_rqe(tgt, 1);
  604. spin_unlock_bh(&tgt->tgt_lock);
  605. break;
  606. default:
  607. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  608. break;
  609. }
  610. }
  611. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  612. {
  613. struct fcoe_task_ctx_entry *task;
  614. struct fcoe_task_ctx_entry *task_page;
  615. struct fcoe_port *port = tgt->port;
  616. struct bnx2fc_hba *hba = port->priv;
  617. struct bnx2fc_cmd *io_req;
  618. int task_idx, index;
  619. u16 xid;
  620. u8 cmd_type;
  621. u8 rx_state = 0;
  622. u8 num_rq;
  623. spin_lock_bh(&tgt->tgt_lock);
  624. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  625. if (xid >= BNX2FC_MAX_TASKS) {
  626. printk(KERN_ALERT PFX "ERROR:xid out of range\n");
  627. spin_unlock_bh(&tgt->tgt_lock);
  628. return;
  629. }
  630. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  631. index = xid % BNX2FC_TASKS_PER_PAGE;
  632. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  633. task = &(task_page[index]);
  634. num_rq = ((task->rx_wr_tx_rd.rx_flags &
  635. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE) >>
  636. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT);
  637. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  638. if (io_req == NULL) {
  639. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  640. spin_unlock_bh(&tgt->tgt_lock);
  641. return;
  642. }
  643. /* Timestamp IO completion time */
  644. cmd_type = io_req->cmd_type;
  645. /* optimized completion path */
  646. if (cmd_type == BNX2FC_SCSI_CMD) {
  647. rx_state = ((task->rx_wr_tx_rd.rx_flags &
  648. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE) >>
  649. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT);
  650. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  651. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  652. spin_unlock_bh(&tgt->tgt_lock);
  653. return;
  654. }
  655. }
  656. /* Process other IO completion types */
  657. switch (cmd_type) {
  658. case BNX2FC_SCSI_CMD:
  659. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  660. bnx2fc_process_abts_compl(io_req, task, num_rq);
  661. else if (rx_state ==
  662. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  663. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  664. else
  665. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  666. rx_state);
  667. break;
  668. case BNX2FC_TASK_MGMT_CMD:
  669. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  670. bnx2fc_process_tm_compl(io_req, task, num_rq);
  671. break;
  672. case BNX2FC_ABTS:
  673. /*
  674. * ABTS request received by firmware. ABTS response
  675. * will be delivered to the task belonging to the IO
  676. * that was aborted
  677. */
  678. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  679. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  680. break;
  681. case BNX2FC_ELS:
  682. BNX2FC_IO_DBG(io_req, "cq_compl - call process_els_compl\n");
  683. bnx2fc_process_els_compl(io_req, task, num_rq);
  684. break;
  685. case BNX2FC_CLEANUP:
  686. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  687. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  688. break;
  689. default:
  690. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  691. break;
  692. }
  693. spin_unlock_bh(&tgt->tgt_lock);
  694. }
  695. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  696. {
  697. struct bnx2fc_work *work;
  698. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  699. if (!work)
  700. return NULL;
  701. INIT_LIST_HEAD(&work->list);
  702. work->tgt = tgt;
  703. work->wqe = wqe;
  704. return work;
  705. }
  706. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  707. {
  708. struct fcoe_cqe *cq;
  709. u32 cq_cons;
  710. struct fcoe_cqe *cqe;
  711. u16 wqe;
  712. bool more_cqes_found = false;
  713. /*
  714. * cq_lock is a low contention lock used to protect
  715. * the CQ data structure from being freed up during
  716. * the upload operation
  717. */
  718. spin_lock_bh(&tgt->cq_lock);
  719. if (!tgt->cq) {
  720. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  721. spin_unlock_bh(&tgt->cq_lock);
  722. return 0;
  723. }
  724. cq = tgt->cq;
  725. cq_cons = tgt->cq_cons_idx;
  726. cqe = &cq[cq_cons];
  727. do {
  728. more_cqes_found ^= true;
  729. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  730. (tgt->cq_curr_toggle_bit <<
  731. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  732. /* new entry on the cq */
  733. if (wqe & FCOE_CQE_CQE_TYPE) {
  734. /* Unsolicited event notification */
  735. bnx2fc_process_unsol_compl(tgt, wqe);
  736. } else {
  737. struct bnx2fc_work *work = NULL;
  738. struct bnx2fc_percpu_s *fps = NULL;
  739. unsigned int cpu = wqe % num_possible_cpus();
  740. fps = &per_cpu(bnx2fc_percpu, cpu);
  741. spin_lock_bh(&fps->fp_work_lock);
  742. if (unlikely(!fps->iothread))
  743. goto unlock;
  744. work = bnx2fc_alloc_work(tgt, wqe);
  745. if (work)
  746. list_add_tail(&work->list,
  747. &fps->work_list);
  748. unlock:
  749. spin_unlock_bh(&fps->fp_work_lock);
  750. /* Pending work request completion */
  751. if (fps->iothread && work)
  752. wake_up_process(fps->iothread);
  753. else
  754. bnx2fc_process_cq_compl(tgt, wqe);
  755. }
  756. cqe++;
  757. tgt->cq_cons_idx++;
  758. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  759. tgt->cq_cons_idx = 0;
  760. cqe = cq;
  761. tgt->cq_curr_toggle_bit =
  762. 1 - tgt->cq_curr_toggle_bit;
  763. }
  764. }
  765. /* Re-arm CQ */
  766. if (more_cqes_found) {
  767. tgt->conn_db->cq_arm.lo = -1;
  768. wmb();
  769. }
  770. } while (more_cqes_found);
  771. /*
  772. * Commit tgt->cq_cons_idx change to the memory
  773. * spin_lock implies full memory barrier, no need to smp_wmb
  774. */
  775. spin_unlock_bh(&tgt->cq_lock);
  776. return 0;
  777. }
  778. /**
  779. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  780. *
  781. * @hba: adapter structure pointer
  782. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  783. *
  784. * Fast path event notification handler
  785. */
  786. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  787. struct fcoe_kcqe *new_cqe_kcqe)
  788. {
  789. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  790. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  791. if (!tgt) {
  792. printk(KERN_ALERT PFX "conn_id 0x%x not valid\n", conn_id);
  793. return;
  794. }
  795. bnx2fc_process_new_cqes(tgt);
  796. }
  797. /**
  798. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  799. *
  800. * @hba: adapter structure pointer
  801. * @ofld_kcqe: connection offload kcqe pointer
  802. *
  803. * handle session offload completion, enable the session if offload is
  804. * successful.
  805. */
  806. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  807. struct fcoe_kcqe *ofld_kcqe)
  808. {
  809. struct bnx2fc_rport *tgt;
  810. struct fcoe_port *port;
  811. u32 conn_id;
  812. u32 context_id;
  813. int rc;
  814. conn_id = ofld_kcqe->fcoe_conn_id;
  815. context_id = ofld_kcqe->fcoe_conn_context_id;
  816. tgt = hba->tgt_ofld_list[conn_id];
  817. if (!tgt) {
  818. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  819. return;
  820. }
  821. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  822. ofld_kcqe->fcoe_conn_context_id);
  823. port = tgt->port;
  824. if (hba != tgt->port->priv) {
  825. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  826. goto ofld_cmpl_err;
  827. }
  828. /*
  829. * cnic has allocated a context_id for this session; use this
  830. * while enabling the session.
  831. */
  832. tgt->context_id = context_id;
  833. if (ofld_kcqe->completion_status) {
  834. if (ofld_kcqe->completion_status ==
  835. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  836. printk(KERN_ERR PFX "unable to allocate FCoE context "
  837. "resources\n");
  838. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  839. }
  840. goto ofld_cmpl_err;
  841. } else {
  842. /* now enable the session */
  843. rc = bnx2fc_send_session_enable_req(port, tgt);
  844. if (rc) {
  845. printk(KERN_ALERT PFX "enable session failed\n");
  846. goto ofld_cmpl_err;
  847. }
  848. }
  849. return;
  850. ofld_cmpl_err:
  851. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  852. wake_up_interruptible(&tgt->ofld_wait);
  853. }
  854. /**
  855. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  856. *
  857. * @hba: adapter structure pointer
  858. * @ofld_kcqe: connection offload kcqe pointer
  859. *
  860. * handle session enable completion, mark the rport as ready
  861. */
  862. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  863. struct fcoe_kcqe *ofld_kcqe)
  864. {
  865. struct bnx2fc_rport *tgt;
  866. u32 conn_id;
  867. u32 context_id;
  868. context_id = ofld_kcqe->fcoe_conn_context_id;
  869. conn_id = ofld_kcqe->fcoe_conn_id;
  870. tgt = hba->tgt_ofld_list[conn_id];
  871. if (!tgt) {
  872. printk(KERN_ALERT PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  873. return;
  874. }
  875. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  876. ofld_kcqe->fcoe_conn_context_id);
  877. /*
  878. * context_id should be the same for this target during offload
  879. * and enable
  880. */
  881. if (tgt->context_id != context_id) {
  882. printk(KERN_ALERT PFX "context id mis-match\n");
  883. return;
  884. }
  885. if (hba != tgt->port->priv) {
  886. printk(KERN_ALERT PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  887. goto enbl_cmpl_err;
  888. }
  889. if (ofld_kcqe->completion_status) {
  890. goto enbl_cmpl_err;
  891. } else {
  892. /* enable successful - rport ready for issuing IOs */
  893. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  894. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  895. wake_up_interruptible(&tgt->ofld_wait);
  896. }
  897. return;
  898. enbl_cmpl_err:
  899. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  900. wake_up_interruptible(&tgt->ofld_wait);
  901. }
  902. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  903. struct fcoe_kcqe *disable_kcqe)
  904. {
  905. struct bnx2fc_rport *tgt;
  906. u32 conn_id;
  907. conn_id = disable_kcqe->fcoe_conn_id;
  908. tgt = hba->tgt_ofld_list[conn_id];
  909. if (!tgt) {
  910. printk(KERN_ALERT PFX "ERROR: disable_cmpl: No disable req\n");
  911. return;
  912. }
  913. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  914. if (disable_kcqe->completion_status) {
  915. printk(KERN_ALERT PFX "ERROR: Disable failed with cmpl status %d\n",
  916. disable_kcqe->completion_status);
  917. return;
  918. } else {
  919. /* disable successful */
  920. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  921. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  922. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  923. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  924. wake_up_interruptible(&tgt->upld_wait);
  925. }
  926. }
  927. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  928. struct fcoe_kcqe *destroy_kcqe)
  929. {
  930. struct bnx2fc_rport *tgt;
  931. u32 conn_id;
  932. conn_id = destroy_kcqe->fcoe_conn_id;
  933. tgt = hba->tgt_ofld_list[conn_id];
  934. if (!tgt) {
  935. printk(KERN_ALERT PFX "destroy_cmpl: No destroy req\n");
  936. return;
  937. }
  938. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  939. if (destroy_kcqe->completion_status) {
  940. printk(KERN_ALERT PFX "Destroy conn failed, cmpl status %d\n",
  941. destroy_kcqe->completion_status);
  942. return;
  943. } else {
  944. /* destroy successful */
  945. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  946. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  947. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  948. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  949. wake_up_interruptible(&tgt->upld_wait);
  950. }
  951. }
  952. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  953. {
  954. switch (err_code) {
  955. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  956. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  957. break;
  958. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  959. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  960. break;
  961. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  962. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  963. break;
  964. default:
  965. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  966. }
  967. }
  968. /**
  969. * bnx2fc_indicae_kcqe - process KCQE
  970. *
  971. * @hba: adapter structure pointer
  972. * @kcqe: kcqe pointer
  973. * @num_cqe: Number of completion queue elements
  974. *
  975. * Generic KCQ event handler
  976. */
  977. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  978. u32 num_cqe)
  979. {
  980. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  981. int i = 0;
  982. struct fcoe_kcqe *kcqe = NULL;
  983. while (i < num_cqe) {
  984. kcqe = (struct fcoe_kcqe *) kcq[i++];
  985. switch (kcqe->op_code) {
  986. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  987. bnx2fc_fastpath_notification(hba, kcqe);
  988. break;
  989. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  990. bnx2fc_process_ofld_cmpl(hba, kcqe);
  991. break;
  992. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  993. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  994. break;
  995. case FCOE_KCQE_OPCODE_INIT_FUNC:
  996. if (kcqe->completion_status !=
  997. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  998. bnx2fc_init_failure(hba,
  999. kcqe->completion_status);
  1000. } else {
  1001. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1002. bnx2fc_get_link_state(hba);
  1003. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1004. (u8)hba->pcidev->bus->number);
  1005. }
  1006. break;
  1007. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1008. if (kcqe->completion_status !=
  1009. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1010. printk(KERN_ERR PFX "DESTROY failed\n");
  1011. } else {
  1012. printk(KERN_ERR PFX "DESTROY success\n");
  1013. }
  1014. hba->flags |= BNX2FC_FLAG_DESTROY_CMPL;
  1015. wake_up_interruptible(&hba->destroy_wait);
  1016. break;
  1017. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1018. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1019. break;
  1020. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1021. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1022. break;
  1023. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1024. if (kcqe->completion_status !=
  1025. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1026. printk(KERN_ERR PFX "STAT failed\n");
  1027. complete(&hba->stat_req_done);
  1028. break;
  1029. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1030. /* fall thru */
  1031. default:
  1032. printk(KERN_ALERT PFX "unknown opcode 0x%x\n",
  1033. kcqe->op_code);
  1034. }
  1035. }
  1036. }
  1037. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1038. {
  1039. struct fcoe_sqe *sqe;
  1040. sqe = &tgt->sq[tgt->sq_prod_idx];
  1041. /* Fill SQ WQE */
  1042. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1043. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1044. /* Advance SQ Prod Idx */
  1045. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1046. tgt->sq_prod_idx = 0;
  1047. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1048. }
  1049. }
  1050. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1051. {
  1052. struct b577xx_doorbell_set_prod ev_doorbell;
  1053. u32 msg;
  1054. wmb();
  1055. memset(&ev_doorbell, 0, sizeof(struct b577xx_doorbell_set_prod));
  1056. ev_doorbell.header.header = B577XX_DOORBELL_HDR_DB_TYPE;
  1057. ev_doorbell.prod = tgt->sq_prod_idx |
  1058. (tgt->sq_curr_toggle_bit << 15);
  1059. ev_doorbell.header.header |= B577XX_FCOE_CONNECTION_TYPE <<
  1060. B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT;
  1061. msg = *((u32 *)&ev_doorbell);
  1062. writel(cpu_to_le32(msg), tgt->ctx_base);
  1063. mmiowb();
  1064. }
  1065. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1066. {
  1067. u32 context_id = tgt->context_id;
  1068. struct fcoe_port *port = tgt->port;
  1069. u32 reg_off;
  1070. resource_size_t reg_base;
  1071. struct bnx2fc_hba *hba = port->priv;
  1072. reg_base = pci_resource_start(hba->pcidev,
  1073. BNX2X_DOORBELL_PCI_BAR);
  1074. reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
  1075. (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
  1076. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1077. if (!tgt->ctx_base)
  1078. return -ENOMEM;
  1079. return 0;
  1080. }
  1081. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1082. {
  1083. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1084. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1085. return NULL;
  1086. tgt->rq_cons_idx += num_items;
  1087. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1088. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1089. return buf;
  1090. }
  1091. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1092. {
  1093. /* return the rq buffer */
  1094. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1095. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1096. /* Wrap around RQ */
  1097. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1098. }
  1099. tgt->rq_prod_idx = next_prod_idx;
  1100. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1101. }
  1102. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1103. struct fcoe_task_ctx_entry *task,
  1104. u16 orig_xid)
  1105. {
  1106. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1107. struct bnx2fc_rport *tgt = io_req->tgt;
  1108. u32 context_id = tgt->context_id;
  1109. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1110. /* Tx Write Rx Read */
  1111. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1112. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1113. task->tx_wr_rx_rd.init_flags = task_type <<
  1114. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1115. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1116. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1117. /* Common */
  1118. task->cmn.common_flags = context_id <<
  1119. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1120. task->cmn.general.cleanup_info.task_id = orig_xid;
  1121. }
  1122. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1123. struct fcoe_task_ctx_entry *task)
  1124. {
  1125. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1126. struct bnx2fc_rport *tgt = io_req->tgt;
  1127. struct fc_frame_header *fc_hdr;
  1128. u8 task_type = 0;
  1129. u64 *hdr;
  1130. u64 temp_hdr[3];
  1131. u32 context_id;
  1132. /* Obtain task_type */
  1133. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1134. (io_req->cmd_type == BNX2FC_ELS)) {
  1135. task_type = FCOE_TASK_TYPE_MIDPATH;
  1136. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1137. task_type = FCOE_TASK_TYPE_ABTS;
  1138. }
  1139. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1140. /* Setup the task from io_req for easy reference */
  1141. io_req->task = task;
  1142. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1143. io_req->cmd_type, task_type);
  1144. /* Tx only */
  1145. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1146. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1147. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1148. (u32)mp_req->mp_req_bd_dma;
  1149. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1150. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1151. task->tx_wr_only.sgl_ctx.mul_sges.sgl_size = 1;
  1152. BNX2FC_IO_DBG(io_req, "init_mp_task - bd_dma = 0x%llx\n",
  1153. (unsigned long long)mp_req->mp_req_bd_dma);
  1154. }
  1155. /* Tx Write Rx Read */
  1156. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1157. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1158. task->tx_wr_rx_rd.init_flags = task_type <<
  1159. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1160. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_DEV_TYPE_DISK <<
  1161. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT;
  1162. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1163. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1164. /* Common */
  1165. task->cmn.data_2_trns = io_req->data_xfer_len;
  1166. context_id = tgt->context_id;
  1167. task->cmn.common_flags = context_id <<
  1168. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1169. task->cmn.common_flags |= 1 <<
  1170. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT;
  1171. task->cmn.common_flags |= 1 <<
  1172. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT;
  1173. /* Rx Write Tx Read */
  1174. fc_hdr = &(mp_req->req_fc_hdr);
  1175. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1176. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1177. fc_hdr->fh_rx_id = htons(0xffff);
  1178. task->rx_wr_tx_rd.rx_id = 0xffff;
  1179. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1180. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1181. }
  1182. /* Fill FC Header into middle path buffer */
  1183. hdr = (u64 *) &task->cmn.general.cmd_info.mp_fc_frame.fc_hdr;
  1184. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1185. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1186. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1187. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1188. /* Rx Only */
  1189. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1190. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1191. (u32)mp_req->mp_resp_bd_dma;
  1192. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1193. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1194. task->rx_wr_only.sgl_ctx.mul_sges.sgl_size = 1;
  1195. }
  1196. }
  1197. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1198. struct fcoe_task_ctx_entry *task)
  1199. {
  1200. u8 task_type;
  1201. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1202. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1203. struct bnx2fc_rport *tgt = io_req->tgt;
  1204. u64 *fcp_cmnd;
  1205. u64 tmp_fcp_cmnd[4];
  1206. u32 context_id;
  1207. int cnt, i;
  1208. int bd_count;
  1209. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1210. /* Setup the task from io_req for easy reference */
  1211. io_req->task = task;
  1212. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1213. task_type = FCOE_TASK_TYPE_WRITE;
  1214. else
  1215. task_type = FCOE_TASK_TYPE_READ;
  1216. /* Tx only */
  1217. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1218. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1219. (u32)bd_tbl->bd_tbl_dma;
  1220. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1221. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1222. task->tx_wr_only.sgl_ctx.mul_sges.sgl_size =
  1223. bd_tbl->bd_valid;
  1224. }
  1225. /*Tx Write Rx Read */
  1226. /* Init state to NORMAL */
  1227. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1228. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1229. task->tx_wr_rx_rd.init_flags = task_type <<
  1230. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1231. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_DEV_TYPE_DISK <<
  1232. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT;
  1233. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1234. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1235. /* Common */
  1236. task->cmn.data_2_trns = io_req->data_xfer_len;
  1237. context_id = tgt->context_id;
  1238. task->cmn.common_flags = context_id <<
  1239. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1240. task->cmn.common_flags |= 1 <<
  1241. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT;
  1242. task->cmn.common_flags |= 1 <<
  1243. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT;
  1244. /* Set initiative ownership */
  1245. task->cmn.common_flags |= FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT;
  1246. /* Set initial seq counter */
  1247. task->cmn.tx_low_seq_cnt = 1;
  1248. /* Set state to "waiting for the first packet" */
  1249. task->cmn.common_flags |= FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME;
  1250. /* Fill FCP_CMND IU */
  1251. fcp_cmnd = (u64 *)
  1252. task->cmn.general.cmd_info.fcp_cmd_payload.opaque;
  1253. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1254. /* swap fcp_cmnd */
  1255. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1256. for (i = 0; i < cnt; i++) {
  1257. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1258. fcp_cmnd++;
  1259. }
  1260. /* Rx Write Tx Read */
  1261. task->rx_wr_tx_rd.rx_id = 0xffff;
  1262. /* Rx Only */
  1263. if (task_type == FCOE_TASK_TYPE_READ) {
  1264. bd_count = bd_tbl->bd_valid;
  1265. if (bd_count == 1) {
  1266. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1267. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_addr.lo =
  1268. fcoe_bd_tbl->buf_addr_lo;
  1269. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_addr.hi =
  1270. fcoe_bd_tbl->buf_addr_hi;
  1271. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_rem =
  1272. fcoe_bd_tbl->buf_len;
  1273. task->tx_wr_rx_rd.init_flags |= 1 <<
  1274. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT;
  1275. } else {
  1276. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1277. (u32)bd_tbl->bd_tbl_dma;
  1278. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1279. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1280. task->rx_wr_only.sgl_ctx.mul_sges.sgl_size =
  1281. bd_tbl->bd_valid;
  1282. }
  1283. }
  1284. }
  1285. /**
  1286. * bnx2fc_setup_task_ctx - allocate and map task context
  1287. *
  1288. * @hba: pointer to adapter structure
  1289. *
  1290. * allocate memory for task context, and associated BD table to be used
  1291. * by firmware
  1292. *
  1293. */
  1294. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1295. {
  1296. int rc = 0;
  1297. struct regpair *task_ctx_bdt;
  1298. dma_addr_t addr;
  1299. int i;
  1300. /*
  1301. * Allocate task context bd table. A page size of bd table
  1302. * can map 256 buffers. Each buffer contains 32 task context
  1303. * entries. Hence the limit with one page is 8192 task context
  1304. * entries.
  1305. */
  1306. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1307. PAGE_SIZE,
  1308. &hba->task_ctx_bd_dma,
  1309. GFP_KERNEL);
  1310. if (!hba->task_ctx_bd_tbl) {
  1311. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1312. rc = -1;
  1313. goto out;
  1314. }
  1315. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1316. /*
  1317. * Allocate task_ctx which is an array of pointers pointing to
  1318. * a page containing 32 task contexts
  1319. */
  1320. hba->task_ctx = kzalloc((BNX2FC_TASK_CTX_ARR_SZ * sizeof(void *)),
  1321. GFP_KERNEL);
  1322. if (!hba->task_ctx) {
  1323. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1324. rc = -1;
  1325. goto out1;
  1326. }
  1327. /*
  1328. * Allocate task_ctx_dma which is an array of dma addresses
  1329. */
  1330. hba->task_ctx_dma = kmalloc((BNX2FC_TASK_CTX_ARR_SZ *
  1331. sizeof(dma_addr_t)), GFP_KERNEL);
  1332. if (!hba->task_ctx_dma) {
  1333. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1334. rc = -1;
  1335. goto out2;
  1336. }
  1337. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1338. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1339. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1340. PAGE_SIZE,
  1341. &hba->task_ctx_dma[i],
  1342. GFP_KERNEL);
  1343. if (!hba->task_ctx[i]) {
  1344. printk(KERN_ERR PFX "unable to alloc task context\n");
  1345. rc = -1;
  1346. goto out3;
  1347. }
  1348. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1349. addr = (u64)hba->task_ctx_dma[i];
  1350. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1351. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1352. task_ctx_bdt++;
  1353. }
  1354. return 0;
  1355. out3:
  1356. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1357. if (hba->task_ctx[i]) {
  1358. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1359. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1360. hba->task_ctx[i] = NULL;
  1361. }
  1362. }
  1363. kfree(hba->task_ctx_dma);
  1364. hba->task_ctx_dma = NULL;
  1365. out2:
  1366. kfree(hba->task_ctx);
  1367. hba->task_ctx = NULL;
  1368. out1:
  1369. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1370. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1371. hba->task_ctx_bd_tbl = NULL;
  1372. out:
  1373. return rc;
  1374. }
  1375. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1376. {
  1377. int i;
  1378. if (hba->task_ctx_bd_tbl) {
  1379. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1380. hba->task_ctx_bd_tbl,
  1381. hba->task_ctx_bd_dma);
  1382. hba->task_ctx_bd_tbl = NULL;
  1383. }
  1384. if (hba->task_ctx) {
  1385. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1386. if (hba->task_ctx[i]) {
  1387. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1388. hba->task_ctx[i],
  1389. hba->task_ctx_dma[i]);
  1390. hba->task_ctx[i] = NULL;
  1391. }
  1392. }
  1393. kfree(hba->task_ctx);
  1394. hba->task_ctx = NULL;
  1395. }
  1396. kfree(hba->task_ctx_dma);
  1397. hba->task_ctx_dma = NULL;
  1398. }
  1399. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1400. {
  1401. int i;
  1402. int segment_count;
  1403. int hash_table_size;
  1404. u32 *pbl;
  1405. segment_count = hba->hash_tbl_segment_count;
  1406. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1407. sizeof(struct fcoe_hash_table_entry);
  1408. pbl = hba->hash_tbl_pbl;
  1409. for (i = 0; i < segment_count; ++i) {
  1410. dma_addr_t dma_address;
  1411. dma_address = le32_to_cpu(*pbl);
  1412. ++pbl;
  1413. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1414. ++pbl;
  1415. dma_free_coherent(&hba->pcidev->dev,
  1416. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1417. hba->hash_tbl_segments[i],
  1418. dma_address);
  1419. }
  1420. if (hba->hash_tbl_pbl) {
  1421. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1422. hba->hash_tbl_pbl,
  1423. hba->hash_tbl_pbl_dma);
  1424. hba->hash_tbl_pbl = NULL;
  1425. }
  1426. }
  1427. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1428. {
  1429. int i;
  1430. int hash_table_size;
  1431. int segment_count;
  1432. int segment_array_size;
  1433. int dma_segment_array_size;
  1434. dma_addr_t *dma_segment_array;
  1435. u32 *pbl;
  1436. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1437. sizeof(struct fcoe_hash_table_entry);
  1438. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1439. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1440. hba->hash_tbl_segment_count = segment_count;
  1441. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1442. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1443. if (!hba->hash_tbl_segments) {
  1444. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1445. return -ENOMEM;
  1446. }
  1447. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1448. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1449. if (!dma_segment_array) {
  1450. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1451. return -ENOMEM;
  1452. }
  1453. for (i = 0; i < segment_count; ++i) {
  1454. hba->hash_tbl_segments[i] =
  1455. dma_alloc_coherent(&hba->pcidev->dev,
  1456. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1457. &dma_segment_array[i],
  1458. GFP_KERNEL);
  1459. if (!hba->hash_tbl_segments[i]) {
  1460. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1461. while (--i >= 0) {
  1462. dma_free_coherent(&hba->pcidev->dev,
  1463. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1464. hba->hash_tbl_segments[i],
  1465. dma_segment_array[i]);
  1466. hba->hash_tbl_segments[i] = NULL;
  1467. }
  1468. kfree(dma_segment_array);
  1469. return -ENOMEM;
  1470. }
  1471. memset(hba->hash_tbl_segments[i], 0,
  1472. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1473. }
  1474. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1475. PAGE_SIZE,
  1476. &hba->hash_tbl_pbl_dma,
  1477. GFP_KERNEL);
  1478. if (!hba->hash_tbl_pbl) {
  1479. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1480. kfree(dma_segment_array);
  1481. return -ENOMEM;
  1482. }
  1483. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1484. pbl = hba->hash_tbl_pbl;
  1485. for (i = 0; i < segment_count; ++i) {
  1486. u64 paddr = dma_segment_array[i];
  1487. *pbl = cpu_to_le32((u32) paddr);
  1488. ++pbl;
  1489. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1490. ++pbl;
  1491. }
  1492. pbl = hba->hash_tbl_pbl;
  1493. i = 0;
  1494. while (*pbl && *(pbl + 1)) {
  1495. u32 lo;
  1496. u32 hi;
  1497. lo = *pbl;
  1498. ++pbl;
  1499. hi = *pbl;
  1500. ++pbl;
  1501. ++i;
  1502. }
  1503. kfree(dma_segment_array);
  1504. return 0;
  1505. }
  1506. /**
  1507. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1508. *
  1509. * @hba: Pointer to adapter structure
  1510. *
  1511. */
  1512. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1513. {
  1514. u64 addr;
  1515. u32 mem_size;
  1516. int i;
  1517. if (bnx2fc_allocate_hash_table(hba))
  1518. return -ENOMEM;
  1519. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1520. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1521. &hba->t2_hash_tbl_ptr_dma,
  1522. GFP_KERNEL);
  1523. if (!hba->t2_hash_tbl_ptr) {
  1524. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1525. bnx2fc_free_fw_resc(hba);
  1526. return -ENOMEM;
  1527. }
  1528. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1529. mem_size = BNX2FC_NUM_MAX_SESS *
  1530. sizeof(struct fcoe_t2_hash_table_entry);
  1531. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1532. &hba->t2_hash_tbl_dma,
  1533. GFP_KERNEL);
  1534. if (!hba->t2_hash_tbl) {
  1535. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1536. bnx2fc_free_fw_resc(hba);
  1537. return -ENOMEM;
  1538. }
  1539. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1540. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1541. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1542. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1543. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1544. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1545. }
  1546. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1547. PAGE_SIZE, &hba->dummy_buf_dma,
  1548. GFP_KERNEL);
  1549. if (!hba->dummy_buffer) {
  1550. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1551. bnx2fc_free_fw_resc(hba);
  1552. return -ENOMEM;
  1553. }
  1554. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1555. PAGE_SIZE,
  1556. &hba->stats_buf_dma,
  1557. GFP_KERNEL);
  1558. if (!hba->stats_buffer) {
  1559. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1560. bnx2fc_free_fw_resc(hba);
  1561. return -ENOMEM;
  1562. }
  1563. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1564. return 0;
  1565. }
  1566. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1567. {
  1568. u32 mem_size;
  1569. if (hba->stats_buffer) {
  1570. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1571. hba->stats_buffer, hba->stats_buf_dma);
  1572. hba->stats_buffer = NULL;
  1573. }
  1574. if (hba->dummy_buffer) {
  1575. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1576. hba->dummy_buffer, hba->dummy_buf_dma);
  1577. hba->dummy_buffer = NULL;
  1578. }
  1579. if (hba->t2_hash_tbl_ptr) {
  1580. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1581. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1582. hba->t2_hash_tbl_ptr,
  1583. hba->t2_hash_tbl_ptr_dma);
  1584. hba->t2_hash_tbl_ptr = NULL;
  1585. }
  1586. if (hba->t2_hash_tbl) {
  1587. mem_size = BNX2FC_NUM_MAX_SESS *
  1588. sizeof(struct fcoe_t2_hash_table_entry);
  1589. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1590. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1591. hba->t2_hash_tbl = NULL;
  1592. }
  1593. bnx2fc_free_hash_table(hba);
  1594. }