arcmsr_hba.c 99 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Nick Cheng
  6. ** Description: SCSI RAID Device Driver for
  7. ** ARECA RAID Host adapter
  8. *******************************************************************************
  9. ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
  10. **
  11. ** Web site: www.areca.com.tw
  12. ** E-mail: support@areca.com.tw
  13. **
  14. ** This program is free software; you can redistribute it and/or modify
  15. ** it under the terms of the GNU General Public License version 2 as
  16. ** published by the Free Software Foundation.
  17. ** This program is distributed in the hope that it will be useful,
  18. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. ** GNU General Public License for more details.
  21. *******************************************************************************
  22. ** Redistribution and use in source and binary forms, with or without
  23. ** modification, are permitted provided that the following conditions
  24. ** are met:
  25. ** 1. Redistributions of source code must retain the above copyright
  26. ** notice, this list of conditions and the following disclaimer.
  27. ** 2. Redistributions in binary form must reproduce the above copyright
  28. ** notice, this list of conditions and the following disclaimer in the
  29. ** documentation and/or other materials provided with the distribution.
  30. ** 3. The name of the author may not be used to endorse or promote products
  31. ** derived from this software without specific prior written permission.
  32. **
  33. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  34. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  35. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  36. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  37. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  38. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  39. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  40. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  41. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  42. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  43. *******************************************************************************
  44. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  45. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  46. *******************************************************************************
  47. */
  48. #include <linux/module.h>
  49. #include <linux/reboot.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/pci_ids.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/errno.h>
  55. #include <linux/types.h>
  56. #include <linux/delay.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/timer.h>
  59. #include <linux/slab.h>
  60. #include <linux/pci.h>
  61. #include <linux/aer.h>
  62. #include <asm/dma.h>
  63. #include <asm/io.h>
  64. #include <asm/system.h>
  65. #include <asm/uaccess.h>
  66. #include <scsi/scsi_host.h>
  67. #include <scsi/scsi.h>
  68. #include <scsi/scsi_cmnd.h>
  69. #include <scsi/scsi_tcq.h>
  70. #include <scsi/scsi_device.h>
  71. #include <scsi/scsi_transport.h>
  72. #include <scsi/scsicam.h>
  73. #include "arcmsr.h"
  74. MODULE_AUTHOR("Nick Cheng <support@areca.com.tw>");
  75. MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/16xx/1880) SATA/SAS RAID Host Bus Adapter");
  76. MODULE_LICENSE("Dual BSD/GPL");
  77. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  78. static int sleeptime = 10;
  79. static int retrycount = 12;
  80. wait_queue_head_t wait_q;
  81. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  82. struct scsi_cmnd *cmd);
  83. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  84. static int arcmsr_abort(struct scsi_cmnd *);
  85. static int arcmsr_bus_reset(struct scsi_cmnd *);
  86. static int arcmsr_bios_param(struct scsi_device *sdev,
  87. struct block_device *bdev, sector_t capacity, int *info);
  88. static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  89. static int arcmsr_probe(struct pci_dev *pdev,
  90. const struct pci_device_id *id);
  91. static void arcmsr_remove(struct pci_dev *pdev);
  92. static void arcmsr_shutdown(struct pci_dev *pdev);
  93. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  94. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  95. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  96. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  97. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
  98. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
  99. static void arcmsr_request_device_map(unsigned long pacb);
  100. static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb);
  101. static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb);
  102. static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb);
  103. static void arcmsr_message_isr_bh_fn(struct work_struct *work);
  104. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
  105. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
  106. static void arcmsr_hbc_message_isr(struct AdapterControlBlock *pACB);
  107. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
  108. static const char *arcmsr_info(struct Scsi_Host *);
  109. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  110. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
  111. int queue_depth, int reason)
  112. {
  113. if (reason != SCSI_QDEPTH_DEFAULT)
  114. return -EOPNOTSUPP;
  115. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  116. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  117. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
  118. return queue_depth;
  119. }
  120. static struct scsi_host_template arcmsr_scsi_host_template = {
  121. .module = THIS_MODULE,
  122. .name = "ARCMSR ARECA SATA/SAS RAID Controller"
  123. ARCMSR_DRIVER_VERSION,
  124. .info = arcmsr_info,
  125. .queuecommand = arcmsr_queue_command,
  126. .eh_abort_handler = arcmsr_abort,
  127. .eh_bus_reset_handler = arcmsr_bus_reset,
  128. .bios_param = arcmsr_bios_param,
  129. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  130. .can_queue = ARCMSR_MAX_FREECCB_NUM,
  131. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  132. .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
  133. .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
  134. .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
  135. .use_clustering = ENABLE_CLUSTERING,
  136. .shost_attrs = arcmsr_host_attrs,
  137. };
  138. static struct pci_device_id arcmsr_device_id_table[] = {
  139. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
  153. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
  154. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
  155. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
  156. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
  157. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880)},
  158. {0, 0}, /* Terminating entry */
  159. };
  160. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  161. static struct pci_driver arcmsr_pci_driver = {
  162. .name = "arcmsr",
  163. .id_table = arcmsr_device_id_table,
  164. .probe = arcmsr_probe,
  165. .remove = arcmsr_remove,
  166. .shutdown = arcmsr_shutdown,
  167. };
  168. /*
  169. ****************************************************************************
  170. ****************************************************************************
  171. */
  172. int arcmsr_sleep_for_bus_reset(struct scsi_cmnd *cmd)
  173. {
  174. struct Scsi_Host *shost = NULL;
  175. int i, isleep;
  176. shost = cmd->device->host;
  177. isleep = sleeptime / 10;
  178. if (isleep > 0) {
  179. for (i = 0; i < isleep; i++) {
  180. msleep(10000);
  181. }
  182. }
  183. isleep = sleeptime % 10;
  184. if (isleep > 0) {
  185. msleep(isleep*1000);
  186. }
  187. return 0;
  188. }
  189. static void arcmsr_free_hbb_mu(struct AdapterControlBlock *acb)
  190. {
  191. switch (acb->adapter_type) {
  192. case ACB_ADAPTER_TYPE_A:
  193. case ACB_ADAPTER_TYPE_C:
  194. break;
  195. case ACB_ADAPTER_TYPE_B:{
  196. dma_free_coherent(&acb->pdev->dev,
  197. sizeof(struct MessageUnit_B),
  198. acb->pmuB, acb->dma_coherent_handle_hbb_mu);
  199. }
  200. }
  201. }
  202. static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
  203. {
  204. struct pci_dev *pdev = acb->pdev;
  205. switch (acb->adapter_type){
  206. case ACB_ADAPTER_TYPE_A:{
  207. acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
  208. if (!acb->pmuA) {
  209. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  210. return false;
  211. }
  212. break;
  213. }
  214. case ACB_ADAPTER_TYPE_B:{
  215. void __iomem *mem_base0, *mem_base1;
  216. mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  217. if (!mem_base0) {
  218. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  219. return false;
  220. }
  221. mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
  222. if (!mem_base1) {
  223. iounmap(mem_base0);
  224. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  225. return false;
  226. }
  227. acb->mem_base0 = mem_base0;
  228. acb->mem_base1 = mem_base1;
  229. break;
  230. }
  231. case ACB_ADAPTER_TYPE_C:{
  232. acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
  233. if (!acb->pmuC) {
  234. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  235. return false;
  236. }
  237. if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  238. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
  239. return true;
  240. }
  241. break;
  242. }
  243. }
  244. return true;
  245. }
  246. static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
  247. {
  248. switch (acb->adapter_type) {
  249. case ACB_ADAPTER_TYPE_A:{
  250. iounmap(acb->pmuA);
  251. }
  252. break;
  253. case ACB_ADAPTER_TYPE_B:{
  254. iounmap(acb->mem_base0);
  255. iounmap(acb->mem_base1);
  256. }
  257. break;
  258. case ACB_ADAPTER_TYPE_C:{
  259. iounmap(acb->pmuC);
  260. }
  261. }
  262. }
  263. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  264. {
  265. irqreturn_t handle_state;
  266. struct AdapterControlBlock *acb = dev_id;
  267. handle_state = arcmsr_interrupt(acb);
  268. return handle_state;
  269. }
  270. static int arcmsr_bios_param(struct scsi_device *sdev,
  271. struct block_device *bdev, sector_t capacity, int *geom)
  272. {
  273. int ret, heads, sectors, cylinders, total_capacity;
  274. unsigned char *buffer;/* return copy of block device's partition table */
  275. buffer = scsi_bios_ptable(bdev);
  276. if (buffer) {
  277. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  278. kfree(buffer);
  279. if (ret != -1)
  280. return ret;
  281. }
  282. total_capacity = capacity;
  283. heads = 64;
  284. sectors = 32;
  285. cylinders = total_capacity / (heads * sectors);
  286. if (cylinders > 1024) {
  287. heads = 255;
  288. sectors = 63;
  289. cylinders = total_capacity / (heads * sectors);
  290. }
  291. geom[0] = heads;
  292. geom[1] = sectors;
  293. geom[2] = cylinders;
  294. return 0;
  295. }
  296. static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
  297. {
  298. struct pci_dev *pdev = acb->pdev;
  299. u16 dev_id;
  300. pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
  301. acb->dev_id = dev_id;
  302. switch (dev_id) {
  303. case 0x1880: {
  304. acb->adapter_type = ACB_ADAPTER_TYPE_C;
  305. }
  306. break;
  307. case 0x1201: {
  308. acb->adapter_type = ACB_ADAPTER_TYPE_B;
  309. }
  310. break;
  311. default: acb->adapter_type = ACB_ADAPTER_TYPE_A;
  312. }
  313. }
  314. static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
  315. {
  316. struct MessageUnit_A __iomem *reg = acb->pmuA;
  317. uint32_t Index;
  318. uint8_t Retries = 0x00;
  319. do {
  320. for (Index = 0; Index < 100; Index++) {
  321. if (readl(&reg->outbound_intstatus) &
  322. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  323. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  324. &reg->outbound_intstatus);
  325. return true;
  326. }
  327. msleep(10);
  328. }/*max 1 seconds*/
  329. } while (Retries++ < 20);/*max 20 sec*/
  330. return false;
  331. }
  332. static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
  333. {
  334. struct MessageUnit_B *reg = acb->pmuB;
  335. uint32_t Index;
  336. uint8_t Retries = 0x00;
  337. do {
  338. for (Index = 0; Index < 100; Index++) {
  339. if (readl(reg->iop2drv_doorbell)
  340. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  341. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN
  342. , reg->iop2drv_doorbell);
  343. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  344. return true;
  345. }
  346. msleep(10);
  347. }/*max 1 seconds*/
  348. } while (Retries++ < 20);/*max 20 sec*/
  349. return false;
  350. }
  351. static uint8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *pACB)
  352. {
  353. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
  354. unsigned char Retries = 0x00;
  355. uint32_t Index;
  356. do {
  357. for (Index = 0; Index < 100; Index++) {
  358. if (readl(&phbcmu->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  359. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &phbcmu->outbound_doorbell_clear);/*clear interrupt*/
  360. return true;
  361. }
  362. /* one us delay */
  363. msleep(10);
  364. } /*max 1 seconds*/
  365. } while (Retries++ < 20); /*max 20 sec*/
  366. return false;
  367. }
  368. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
  369. {
  370. struct MessageUnit_A __iomem *reg = acb->pmuA;
  371. int retry_count = 30;
  372. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  373. do {
  374. if (arcmsr_hba_wait_msgint_ready(acb))
  375. break;
  376. else {
  377. retry_count--;
  378. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  379. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  380. }
  381. } while (retry_count != 0);
  382. }
  383. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
  384. {
  385. struct MessageUnit_B *reg = acb->pmuB;
  386. int retry_count = 30;
  387. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
  388. do {
  389. if (arcmsr_hbb_wait_msgint_ready(acb))
  390. break;
  391. else {
  392. retry_count--;
  393. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  394. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  395. }
  396. } while (retry_count != 0);
  397. }
  398. static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *pACB)
  399. {
  400. struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
  401. int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
  402. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  403. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  404. do {
  405. if (arcmsr_hbc_wait_msgint_ready(pACB)) {
  406. break;
  407. } else {
  408. retry_count--;
  409. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  410. timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
  411. }
  412. } while (retry_count != 0);
  413. return;
  414. }
  415. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  416. {
  417. switch (acb->adapter_type) {
  418. case ACB_ADAPTER_TYPE_A: {
  419. arcmsr_flush_hba_cache(acb);
  420. }
  421. break;
  422. case ACB_ADAPTER_TYPE_B: {
  423. arcmsr_flush_hbb_cache(acb);
  424. }
  425. break;
  426. case ACB_ADAPTER_TYPE_C: {
  427. arcmsr_flush_hbc_cache(acb);
  428. }
  429. }
  430. }
  431. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  432. {
  433. struct pci_dev *pdev = acb->pdev;
  434. void *dma_coherent;
  435. dma_addr_t dma_coherent_handle;
  436. struct CommandControlBlock *ccb_tmp;
  437. int i = 0, j = 0;
  438. dma_addr_t cdb_phyaddr;
  439. unsigned long roundup_ccbsize = 0, offset;
  440. unsigned long max_xfer_len;
  441. unsigned long max_sg_entrys;
  442. uint32_t firm_config_version;
  443. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  444. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  445. acb->devstate[i][j] = ARECA_RAID_GONE;
  446. max_xfer_len = ARCMSR_MAX_XFER_LEN;
  447. max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
  448. firm_config_version = acb->firm_cfg_version;
  449. if((firm_config_version & 0xFF) >= 3){
  450. max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
  451. max_sg_entrys = (max_xfer_len/4096);
  452. }
  453. acb->host->max_sectors = max_xfer_len/512;
  454. acb->host->sg_tablesize = max_sg_entrys;
  455. roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
  456. acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM + 32;
  457. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
  458. if(!dma_coherent){
  459. printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error \n", acb->host->host_no);
  460. return -ENOMEM;
  461. }
  462. acb->dma_coherent = dma_coherent;
  463. acb->dma_coherent_handle = dma_coherent_handle;
  464. memset(dma_coherent, 0, acb->uncache_size);
  465. offset = roundup((unsigned long)dma_coherent, 32) - (unsigned long)dma_coherent;
  466. dma_coherent_handle = dma_coherent_handle + offset;
  467. dma_coherent = (struct CommandControlBlock *)dma_coherent + offset;
  468. ccb_tmp = dma_coherent;
  469. acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
  470. for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
  471. cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
  472. ccb_tmp->cdb_phyaddr_pattern = ((acb->adapter_type == ACB_ADAPTER_TYPE_C) ? cdb_phyaddr : (cdb_phyaddr >> 5));
  473. acb->pccb_pool[i] = ccb_tmp;
  474. ccb_tmp->acb = acb;
  475. INIT_LIST_HEAD(&ccb_tmp->list);
  476. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  477. ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
  478. dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
  479. }
  480. return 0;
  481. }
  482. static void arcmsr_message_isr_bh_fn(struct work_struct *work)
  483. {
  484. struct AdapterControlBlock *acb = container_of(work,struct AdapterControlBlock, arcmsr_do_message_isr_bh);
  485. switch (acb->adapter_type) {
  486. case ACB_ADAPTER_TYPE_A: {
  487. struct MessageUnit_A __iomem *reg = acb->pmuA;
  488. char *acb_dev_map = (char *)acb->device_map;
  489. uint32_t __iomem *signature = (uint32_t __iomem*) (&reg->message_rwbuffer[0]);
  490. char __iomem *devicemap = (char __iomem*) (&reg->message_rwbuffer[21]);
  491. int target, lun;
  492. struct scsi_device *psdev;
  493. char diff;
  494. atomic_inc(&acb->rq_map_token);
  495. if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
  496. for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
  497. diff = (*acb_dev_map)^readb(devicemap);
  498. if (diff != 0) {
  499. char temp;
  500. *acb_dev_map = readb(devicemap);
  501. temp =*acb_dev_map;
  502. for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
  503. if((temp & 0x01)==1 && (diff & 0x01) == 1) {
  504. scsi_add_device(acb->host, 0, target, lun);
  505. }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
  506. psdev = scsi_device_lookup(acb->host, 0, target, lun);
  507. if (psdev != NULL ) {
  508. scsi_remove_device(psdev);
  509. scsi_device_put(psdev);
  510. }
  511. }
  512. temp >>= 1;
  513. diff >>= 1;
  514. }
  515. }
  516. devicemap++;
  517. acb_dev_map++;
  518. }
  519. }
  520. break;
  521. }
  522. case ACB_ADAPTER_TYPE_B: {
  523. struct MessageUnit_B *reg = acb->pmuB;
  524. char *acb_dev_map = (char *)acb->device_map;
  525. uint32_t __iomem *signature = (uint32_t __iomem*)(&reg->message_rwbuffer[0]);
  526. char __iomem *devicemap = (char __iomem*)(&reg->message_rwbuffer[21]);
  527. int target, lun;
  528. struct scsi_device *psdev;
  529. char diff;
  530. atomic_inc(&acb->rq_map_token);
  531. if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
  532. for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
  533. diff = (*acb_dev_map)^readb(devicemap);
  534. if (diff != 0) {
  535. char temp;
  536. *acb_dev_map = readb(devicemap);
  537. temp =*acb_dev_map;
  538. for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
  539. if((temp & 0x01)==1 && (diff & 0x01) == 1) {
  540. scsi_add_device(acb->host, 0, target, lun);
  541. }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
  542. psdev = scsi_device_lookup(acb->host, 0, target, lun);
  543. if (psdev != NULL ) {
  544. scsi_remove_device(psdev);
  545. scsi_device_put(psdev);
  546. }
  547. }
  548. temp >>= 1;
  549. diff >>= 1;
  550. }
  551. }
  552. devicemap++;
  553. acb_dev_map++;
  554. }
  555. }
  556. }
  557. break;
  558. case ACB_ADAPTER_TYPE_C: {
  559. struct MessageUnit_C *reg = acb->pmuC;
  560. char *acb_dev_map = (char *)acb->device_map;
  561. uint32_t __iomem *signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  562. char __iomem *devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  563. int target, lun;
  564. struct scsi_device *psdev;
  565. char diff;
  566. atomic_inc(&acb->rq_map_token);
  567. if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
  568. for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) {
  569. diff = (*acb_dev_map)^readb(devicemap);
  570. if (diff != 0) {
  571. char temp;
  572. *acb_dev_map = readb(devicemap);
  573. temp = *acb_dev_map;
  574. for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
  575. if ((temp & 0x01) == 1 && (diff & 0x01) == 1) {
  576. scsi_add_device(acb->host, 0, target, lun);
  577. } else if ((temp & 0x01) == 0 && (diff & 0x01) == 1) {
  578. psdev = scsi_device_lookup(acb->host, 0, target, lun);
  579. if (psdev != NULL) {
  580. scsi_remove_device(psdev);
  581. scsi_device_put(psdev);
  582. }
  583. }
  584. temp >>= 1;
  585. diff >>= 1;
  586. }
  587. }
  588. devicemap++;
  589. acb_dev_map++;
  590. }
  591. }
  592. }
  593. }
  594. }
  595. static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  596. {
  597. struct Scsi_Host *host;
  598. struct AdapterControlBlock *acb;
  599. uint8_t bus,dev_fun;
  600. int error;
  601. error = pci_enable_device(pdev);
  602. if(error){
  603. return -ENODEV;
  604. }
  605. host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
  606. if(!host){
  607. goto pci_disable_dev;
  608. }
  609. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  610. if(error){
  611. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  612. if(error){
  613. printk(KERN_WARNING
  614. "scsi%d: No suitable DMA mask available\n",
  615. host->host_no);
  616. goto scsi_host_release;
  617. }
  618. }
  619. init_waitqueue_head(&wait_q);
  620. bus = pdev->bus->number;
  621. dev_fun = pdev->devfn;
  622. acb = (struct AdapterControlBlock *) host->hostdata;
  623. memset(acb,0,sizeof(struct AdapterControlBlock));
  624. acb->pdev = pdev;
  625. acb->host = host;
  626. host->max_lun = ARCMSR_MAX_TARGETLUN;
  627. host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
  628. host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
  629. host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
  630. host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
  631. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  632. host->unique_id = (bus << 8) | dev_fun;
  633. pci_set_drvdata(pdev, host);
  634. pci_set_master(pdev);
  635. error = pci_request_regions(pdev, "arcmsr");
  636. if(error){
  637. goto scsi_host_release;
  638. }
  639. spin_lock_init(&acb->eh_lock);
  640. spin_lock_init(&acb->ccblist_lock);
  641. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  642. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  643. ACB_F_MESSAGE_WQBUFFER_READED);
  644. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  645. INIT_LIST_HEAD(&acb->ccb_free_list);
  646. arcmsr_define_adapter_type(acb);
  647. error = arcmsr_remap_pciregion(acb);
  648. if(!error){
  649. goto pci_release_regs;
  650. }
  651. error = arcmsr_get_firmware_spec(acb);
  652. if(!error){
  653. goto unmap_pci_region;
  654. }
  655. error = arcmsr_alloc_ccb_pool(acb);
  656. if(error){
  657. goto free_hbb_mu;
  658. }
  659. arcmsr_iop_init(acb);
  660. error = scsi_add_host(host, &pdev->dev);
  661. if(error){
  662. goto RAID_controller_stop;
  663. }
  664. error = request_irq(pdev->irq, arcmsr_do_interrupt, IRQF_SHARED, "arcmsr", acb);
  665. if(error){
  666. goto scsi_host_remove;
  667. }
  668. host->irq = pdev->irq;
  669. scsi_scan_host(host);
  670. INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
  671. atomic_set(&acb->rq_map_token, 16);
  672. atomic_set(&acb->ante_token_value, 16);
  673. acb->fw_flag = FW_NORMAL;
  674. init_timer(&acb->eternal_timer);
  675. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  676. acb->eternal_timer.data = (unsigned long) acb;
  677. acb->eternal_timer.function = &arcmsr_request_device_map;
  678. add_timer(&acb->eternal_timer);
  679. if(arcmsr_alloc_sysfs_attr(acb))
  680. goto out_free_sysfs;
  681. return 0;
  682. out_free_sysfs:
  683. scsi_host_remove:
  684. scsi_remove_host(host);
  685. RAID_controller_stop:
  686. arcmsr_stop_adapter_bgrb(acb);
  687. arcmsr_flush_adapter_cache(acb);
  688. arcmsr_free_ccb_pool(acb);
  689. free_hbb_mu:
  690. arcmsr_free_hbb_mu(acb);
  691. unmap_pci_region:
  692. arcmsr_unmap_pciregion(acb);
  693. pci_release_regs:
  694. pci_release_regions(pdev);
  695. scsi_host_release:
  696. scsi_host_put(host);
  697. pci_disable_dev:
  698. pci_disable_device(pdev);
  699. return -ENODEV;
  700. }
  701. static uint8_t arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
  702. {
  703. struct MessageUnit_A __iomem *reg = acb->pmuA;
  704. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  705. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  706. printk(KERN_NOTICE
  707. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  708. , acb->host->host_no);
  709. return false;
  710. }
  711. return true;
  712. }
  713. static uint8_t arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
  714. {
  715. struct MessageUnit_B *reg = acb->pmuB;
  716. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
  717. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  718. printk(KERN_NOTICE
  719. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  720. , acb->host->host_no);
  721. return false;
  722. }
  723. return true;
  724. }
  725. static uint8_t arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *pACB)
  726. {
  727. struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
  728. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  729. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  730. if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
  731. printk(KERN_NOTICE
  732. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  733. , pACB->host->host_no);
  734. return false;
  735. }
  736. return true;
  737. }
  738. static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  739. {
  740. uint8_t rtnval = 0;
  741. switch (acb->adapter_type) {
  742. case ACB_ADAPTER_TYPE_A: {
  743. rtnval = arcmsr_abort_hba_allcmd(acb);
  744. }
  745. break;
  746. case ACB_ADAPTER_TYPE_B: {
  747. rtnval = arcmsr_abort_hbb_allcmd(acb);
  748. }
  749. break;
  750. case ACB_ADAPTER_TYPE_C: {
  751. rtnval = arcmsr_abort_hbc_allcmd(acb);
  752. }
  753. }
  754. return rtnval;
  755. }
  756. static bool arcmsr_hbb_enable_driver_mode(struct AdapterControlBlock *pacb)
  757. {
  758. struct MessageUnit_B *reg = pacb->pmuB;
  759. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
  760. if (!arcmsr_hbb_wait_msgint_ready(pacb)) {
  761. printk(KERN_ERR "arcmsr%d: can't set driver mode. \n", pacb->host->host_no);
  762. return false;
  763. }
  764. return true;
  765. }
  766. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  767. {
  768. struct scsi_cmnd *pcmd = ccb->pcmd;
  769. scsi_dma_unmap(pcmd);
  770. }
  771. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
  772. {
  773. struct AdapterControlBlock *acb = ccb->acb;
  774. struct scsi_cmnd *pcmd = ccb->pcmd;
  775. unsigned long flags;
  776. atomic_dec(&acb->ccboutstandingcount);
  777. arcmsr_pci_unmap_dma(ccb);
  778. ccb->startdone = ARCMSR_CCB_DONE;
  779. spin_lock_irqsave(&acb->ccblist_lock, flags);
  780. list_add_tail(&ccb->list, &acb->ccb_free_list);
  781. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  782. pcmd->scsi_done(pcmd);
  783. }
  784. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  785. {
  786. struct scsi_cmnd *pcmd = ccb->pcmd;
  787. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  788. pcmd->result = DID_OK << 16;
  789. if (sensebuffer) {
  790. int sense_data_length =
  791. sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
  792. ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
  793. memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
  794. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  795. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  796. sensebuffer->Valid = 1;
  797. }
  798. }
  799. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  800. {
  801. u32 orig_mask = 0;
  802. switch (acb->adapter_type) {
  803. case ACB_ADAPTER_TYPE_A : {
  804. struct MessageUnit_A __iomem *reg = acb->pmuA;
  805. orig_mask = readl(&reg->outbound_intmask);
  806. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  807. &reg->outbound_intmask);
  808. }
  809. break;
  810. case ACB_ADAPTER_TYPE_B : {
  811. struct MessageUnit_B *reg = acb->pmuB;
  812. orig_mask = readl(reg->iop2drv_doorbell_mask);
  813. writel(0, reg->iop2drv_doorbell_mask);
  814. }
  815. break;
  816. case ACB_ADAPTER_TYPE_C:{
  817. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  818. /* disable all outbound interrupt */
  819. orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
  820. writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  821. }
  822. break;
  823. }
  824. return orig_mask;
  825. }
  826. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
  827. struct CommandControlBlock *ccb, bool error)
  828. {
  829. uint8_t id, lun;
  830. id = ccb->pcmd->device->id;
  831. lun = ccb->pcmd->device->lun;
  832. if (!error) {
  833. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  834. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  835. ccb->pcmd->result = DID_OK << 16;
  836. arcmsr_ccb_complete(ccb);
  837. }else{
  838. switch (ccb->arcmsr_cdb.DeviceStatus) {
  839. case ARCMSR_DEV_SELECT_TIMEOUT: {
  840. acb->devstate[id][lun] = ARECA_RAID_GONE;
  841. ccb->pcmd->result = DID_NO_CONNECT << 16;
  842. arcmsr_ccb_complete(ccb);
  843. }
  844. break;
  845. case ARCMSR_DEV_ABORTED:
  846. case ARCMSR_DEV_INIT_FAIL: {
  847. acb->devstate[id][lun] = ARECA_RAID_GONE;
  848. ccb->pcmd->result = DID_BAD_TARGET << 16;
  849. arcmsr_ccb_complete(ccb);
  850. }
  851. break;
  852. case ARCMSR_DEV_CHECK_CONDITION: {
  853. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  854. arcmsr_report_sense_info(ccb);
  855. arcmsr_ccb_complete(ccb);
  856. }
  857. break;
  858. default:
  859. printk(KERN_NOTICE
  860. "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
  861. but got unknown DeviceStatus = 0x%x \n"
  862. , acb->host->host_no
  863. , id
  864. , lun
  865. , ccb->arcmsr_cdb.DeviceStatus);
  866. acb->devstate[id][lun] = ARECA_RAID_GONE;
  867. ccb->pcmd->result = DID_NO_CONNECT << 16;
  868. arcmsr_ccb_complete(ccb);
  869. break;
  870. }
  871. }
  872. }
  873. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
  874. {
  875. int id, lun;
  876. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  877. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  878. struct scsi_cmnd *abortcmd = pCCB->pcmd;
  879. if (abortcmd) {
  880. id = abortcmd->device->id;
  881. lun = abortcmd->device->lun;
  882. abortcmd->result |= DID_ABORT << 16;
  883. arcmsr_ccb_complete(pCCB);
  884. printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
  885. acb->host->host_no, pCCB);
  886. }
  887. return;
  888. }
  889. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  890. done acb = '0x%p'"
  891. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  892. " ccboutstandingcount = %d \n"
  893. , acb->host->host_no
  894. , acb
  895. , pCCB
  896. , pCCB->acb
  897. , pCCB->startdone
  898. , atomic_read(&acb->ccboutstandingcount));
  899. return;
  900. }
  901. arcmsr_report_ccb_state(acb, pCCB, error);
  902. }
  903. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  904. {
  905. int i = 0;
  906. uint32_t flag_ccb;
  907. struct ARCMSR_CDB *pARCMSR_CDB;
  908. bool error;
  909. struct CommandControlBlock *pCCB;
  910. switch (acb->adapter_type) {
  911. case ACB_ADAPTER_TYPE_A: {
  912. struct MessageUnit_A __iomem *reg = acb->pmuA;
  913. uint32_t outbound_intstatus;
  914. outbound_intstatus = readl(&reg->outbound_intstatus) &
  915. acb->outbound_int_enable;
  916. /*clear and abort all outbound posted Q*/
  917. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  918. while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  919. && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  920. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  921. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  922. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  923. arcmsr_drain_donequeue(acb, pCCB, error);
  924. }
  925. }
  926. break;
  927. case ACB_ADAPTER_TYPE_B: {
  928. struct MessageUnit_B *reg = acb->pmuB;
  929. /*clear all outbound posted Q*/
  930. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
  931. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  932. if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
  933. writel(0, &reg->done_qbuffer[i]);
  934. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  935. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  936. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  937. arcmsr_drain_donequeue(acb, pCCB, error);
  938. }
  939. reg->post_qbuffer[i] = 0;
  940. }
  941. reg->doneq_index = 0;
  942. reg->postq_index = 0;
  943. }
  944. break;
  945. case ACB_ADAPTER_TYPE_C: {
  946. struct MessageUnit_C *reg = acb->pmuC;
  947. struct ARCMSR_CDB *pARCMSR_CDB;
  948. uint32_t flag_ccb, ccb_cdb_phy;
  949. bool error;
  950. struct CommandControlBlock *pCCB;
  951. while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  952. /*need to do*/
  953. flag_ccb = readl(&reg->outbound_queueport_low);
  954. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  955. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  956. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  957. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  958. arcmsr_drain_donequeue(acb, pCCB, error);
  959. }
  960. }
  961. }
  962. }
  963. static void arcmsr_remove(struct pci_dev *pdev)
  964. {
  965. struct Scsi_Host *host = pci_get_drvdata(pdev);
  966. struct AdapterControlBlock *acb =
  967. (struct AdapterControlBlock *) host->hostdata;
  968. int poll_count = 0;
  969. arcmsr_free_sysfs_attr(acb);
  970. scsi_remove_host(host);
  971. flush_work_sync(&acb->arcmsr_do_message_isr_bh);
  972. del_timer_sync(&acb->eternal_timer);
  973. arcmsr_disable_outbound_ints(acb);
  974. arcmsr_stop_adapter_bgrb(acb);
  975. arcmsr_flush_adapter_cache(acb);
  976. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  977. acb->acb_flags &= ~ACB_F_IOP_INITED;
  978. for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
  979. if (!atomic_read(&acb->ccboutstandingcount))
  980. break;
  981. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  982. msleep(25);
  983. }
  984. if (atomic_read(&acb->ccboutstandingcount)) {
  985. int i;
  986. arcmsr_abort_allcmd(acb);
  987. arcmsr_done4abort_postqueue(acb);
  988. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  989. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  990. if (ccb->startdone == ARCMSR_CCB_START) {
  991. ccb->startdone = ARCMSR_CCB_ABORTED;
  992. ccb->pcmd->result = DID_ABORT << 16;
  993. arcmsr_ccb_complete(ccb);
  994. }
  995. }
  996. }
  997. free_irq(pdev->irq, acb);
  998. arcmsr_free_ccb_pool(acb);
  999. arcmsr_free_hbb_mu(acb);
  1000. arcmsr_unmap_pciregion(acb);
  1001. pci_release_regions(pdev);
  1002. scsi_host_put(host);
  1003. pci_disable_device(pdev);
  1004. pci_set_drvdata(pdev, NULL);
  1005. }
  1006. static void arcmsr_shutdown(struct pci_dev *pdev)
  1007. {
  1008. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1009. struct AdapterControlBlock *acb =
  1010. (struct AdapterControlBlock *)host->hostdata;
  1011. del_timer_sync(&acb->eternal_timer);
  1012. arcmsr_disable_outbound_ints(acb);
  1013. flush_work_sync(&acb->arcmsr_do_message_isr_bh);
  1014. arcmsr_stop_adapter_bgrb(acb);
  1015. arcmsr_flush_adapter_cache(acb);
  1016. }
  1017. static int arcmsr_module_init(void)
  1018. {
  1019. int error = 0;
  1020. error = pci_register_driver(&arcmsr_pci_driver);
  1021. return error;
  1022. }
  1023. static void arcmsr_module_exit(void)
  1024. {
  1025. pci_unregister_driver(&arcmsr_pci_driver);
  1026. }
  1027. module_init(arcmsr_module_init);
  1028. module_exit(arcmsr_module_exit);
  1029. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  1030. u32 intmask_org)
  1031. {
  1032. u32 mask;
  1033. switch (acb->adapter_type) {
  1034. case ACB_ADAPTER_TYPE_A: {
  1035. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1036. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  1037. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
  1038. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
  1039. writel(mask, &reg->outbound_intmask);
  1040. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  1041. }
  1042. break;
  1043. case ACB_ADAPTER_TYPE_B: {
  1044. struct MessageUnit_B *reg = acb->pmuB;
  1045. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
  1046. ARCMSR_IOP2DRV_DATA_READ_OK |
  1047. ARCMSR_IOP2DRV_CDB_DONE |
  1048. ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  1049. writel(mask, reg->iop2drv_doorbell_mask);
  1050. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  1051. }
  1052. break;
  1053. case ACB_ADAPTER_TYPE_C: {
  1054. struct MessageUnit_C *reg = acb->pmuC;
  1055. mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
  1056. writel(intmask_org & mask, &reg->host_int_mask);
  1057. acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
  1058. }
  1059. }
  1060. }
  1061. static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
  1062. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  1063. {
  1064. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1065. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  1066. __le32 address_lo, address_hi;
  1067. int arccdbsize = 0x30;
  1068. __le32 length = 0;
  1069. int i;
  1070. struct scatterlist *sg;
  1071. int nseg;
  1072. ccb->pcmd = pcmd;
  1073. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  1074. arcmsr_cdb->TargetID = pcmd->device->id;
  1075. arcmsr_cdb->LUN = pcmd->device->lun;
  1076. arcmsr_cdb->Function = 1;
  1077. arcmsr_cdb->Context = 0;
  1078. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  1079. nseg = scsi_dma_map(pcmd);
  1080. if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
  1081. return FAILED;
  1082. scsi_for_each_sg(pcmd, sg, nseg, i) {
  1083. /* Get the physical address of the current data pointer */
  1084. length = cpu_to_le32(sg_dma_len(sg));
  1085. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  1086. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  1087. if (address_hi == 0) {
  1088. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  1089. pdma_sg->address = address_lo;
  1090. pdma_sg->length = length;
  1091. psge += sizeof (struct SG32ENTRY);
  1092. arccdbsize += sizeof (struct SG32ENTRY);
  1093. } else {
  1094. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  1095. pdma_sg->addresshigh = address_hi;
  1096. pdma_sg->address = address_lo;
  1097. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  1098. psge += sizeof (struct SG64ENTRY);
  1099. arccdbsize += sizeof (struct SG64ENTRY);
  1100. }
  1101. }
  1102. arcmsr_cdb->sgcount = (uint8_t)nseg;
  1103. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  1104. arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
  1105. if ( arccdbsize > 256)
  1106. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  1107. if (pcmd->sc_data_direction == DMA_TO_DEVICE)
  1108. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  1109. ccb->arc_cdb_size = arccdbsize;
  1110. return SUCCESS;
  1111. }
  1112. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  1113. {
  1114. uint32_t cdb_phyaddr_pattern = ccb->cdb_phyaddr_pattern;
  1115. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1116. atomic_inc(&acb->ccboutstandingcount);
  1117. ccb->startdone = ARCMSR_CCB_START;
  1118. switch (acb->adapter_type) {
  1119. case ACB_ADAPTER_TYPE_A: {
  1120. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1121. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  1122. writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  1123. &reg->inbound_queueport);
  1124. else {
  1125. writel(cdb_phyaddr_pattern, &reg->inbound_queueport);
  1126. }
  1127. }
  1128. break;
  1129. case ACB_ADAPTER_TYPE_B: {
  1130. struct MessageUnit_B *reg = acb->pmuB;
  1131. uint32_t ending_index, index = reg->postq_index;
  1132. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  1133. writel(0, &reg->post_qbuffer[ending_index]);
  1134. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  1135. writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
  1136. &reg->post_qbuffer[index]);
  1137. } else {
  1138. writel(cdb_phyaddr_pattern, &reg->post_qbuffer[index]);
  1139. }
  1140. index++;
  1141. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  1142. reg->postq_index = index;
  1143. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
  1144. }
  1145. break;
  1146. case ACB_ADAPTER_TYPE_C: {
  1147. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
  1148. uint32_t ccb_post_stamp, arc_cdb_size;
  1149. arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
  1150. ccb_post_stamp = (cdb_phyaddr_pattern | ((arc_cdb_size - 1) >> 6) | 1);
  1151. if (acb->cdb_phyaddr_hi32) {
  1152. writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
  1153. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1154. } else {
  1155. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1156. }
  1157. }
  1158. }
  1159. }
  1160. static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
  1161. {
  1162. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1163. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1164. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1165. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  1166. printk(KERN_NOTICE
  1167. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  1168. , acb->host->host_no);
  1169. }
  1170. }
  1171. static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
  1172. {
  1173. struct MessageUnit_B *reg = acb->pmuB;
  1174. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1175. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
  1176. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  1177. printk(KERN_NOTICE
  1178. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  1179. , acb->host->host_no);
  1180. }
  1181. }
  1182. static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *pACB)
  1183. {
  1184. struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
  1185. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1186. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1187. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  1188. if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
  1189. printk(KERN_NOTICE
  1190. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  1191. , pACB->host->host_no);
  1192. }
  1193. return;
  1194. }
  1195. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  1196. {
  1197. switch (acb->adapter_type) {
  1198. case ACB_ADAPTER_TYPE_A: {
  1199. arcmsr_stop_hba_bgrb(acb);
  1200. }
  1201. break;
  1202. case ACB_ADAPTER_TYPE_B: {
  1203. arcmsr_stop_hbb_bgrb(acb);
  1204. }
  1205. break;
  1206. case ACB_ADAPTER_TYPE_C: {
  1207. arcmsr_stop_hbc_bgrb(acb);
  1208. }
  1209. }
  1210. }
  1211. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  1212. {
  1213. dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
  1214. }
  1215. void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  1216. {
  1217. switch (acb->adapter_type) {
  1218. case ACB_ADAPTER_TYPE_A: {
  1219. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1220. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1221. }
  1222. break;
  1223. case ACB_ADAPTER_TYPE_B: {
  1224. struct MessageUnit_B *reg = acb->pmuB;
  1225. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  1226. }
  1227. break;
  1228. case ACB_ADAPTER_TYPE_C: {
  1229. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1230. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  1231. }
  1232. }
  1233. }
  1234. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  1235. {
  1236. switch (acb->adapter_type) {
  1237. case ACB_ADAPTER_TYPE_A: {
  1238. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1239. /*
  1240. ** push inbound doorbell tell iop, driver data write ok
  1241. ** and wait reply on next hwinterrupt for next Qbuffer post
  1242. */
  1243. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  1244. }
  1245. break;
  1246. case ACB_ADAPTER_TYPE_B: {
  1247. struct MessageUnit_B *reg = acb->pmuB;
  1248. /*
  1249. ** push inbound doorbell tell iop, driver data write ok
  1250. ** and wait reply on next hwinterrupt for next Qbuffer post
  1251. */
  1252. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
  1253. }
  1254. break;
  1255. case ACB_ADAPTER_TYPE_C: {
  1256. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1257. /*
  1258. ** push inbound doorbell tell iop, driver data write ok
  1259. ** and wait reply on next hwinterrupt for next Qbuffer post
  1260. */
  1261. writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
  1262. }
  1263. break;
  1264. }
  1265. }
  1266. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  1267. {
  1268. struct QBUFFER __iomem *qbuffer = NULL;
  1269. switch (acb->adapter_type) {
  1270. case ACB_ADAPTER_TYPE_A: {
  1271. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1272. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  1273. }
  1274. break;
  1275. case ACB_ADAPTER_TYPE_B: {
  1276. struct MessageUnit_B *reg = acb->pmuB;
  1277. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1278. }
  1279. break;
  1280. case ACB_ADAPTER_TYPE_C: {
  1281. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
  1282. qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
  1283. }
  1284. }
  1285. return qbuffer;
  1286. }
  1287. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  1288. {
  1289. struct QBUFFER __iomem *pqbuffer = NULL;
  1290. switch (acb->adapter_type) {
  1291. case ACB_ADAPTER_TYPE_A: {
  1292. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1293. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  1294. }
  1295. break;
  1296. case ACB_ADAPTER_TYPE_B: {
  1297. struct MessageUnit_B *reg = acb->pmuB;
  1298. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  1299. }
  1300. break;
  1301. case ACB_ADAPTER_TYPE_C: {
  1302. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  1303. pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
  1304. }
  1305. }
  1306. return pqbuffer;
  1307. }
  1308. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  1309. {
  1310. struct QBUFFER __iomem *prbuffer;
  1311. struct QBUFFER *pQbuffer;
  1312. uint8_t __iomem *iop_data;
  1313. int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
  1314. rqbuf_lastindex = acb->rqbuf_lastindex;
  1315. rqbuf_firstindex = acb->rqbuf_firstindex;
  1316. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1317. iop_data = (uint8_t __iomem *)prbuffer->data;
  1318. iop_len = prbuffer->data_len;
  1319. my_empty_len = (rqbuf_firstindex - rqbuf_lastindex - 1) & (ARCMSR_MAX_QBUFFER - 1);
  1320. if (my_empty_len >= iop_len)
  1321. {
  1322. while (iop_len > 0) {
  1323. pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
  1324. memcpy(pQbuffer, iop_data, 1);
  1325. rqbuf_lastindex++;
  1326. rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1327. iop_data++;
  1328. iop_len--;
  1329. }
  1330. acb->rqbuf_lastindex = rqbuf_lastindex;
  1331. arcmsr_iop_message_read(acb);
  1332. }
  1333. else {
  1334. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1335. }
  1336. }
  1337. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  1338. {
  1339. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  1340. if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
  1341. uint8_t *pQbuffer;
  1342. struct QBUFFER __iomem *pwbuffer;
  1343. uint8_t __iomem *iop_data;
  1344. int32_t allxfer_len = 0;
  1345. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1346. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1347. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1348. while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
  1349. (allxfer_len < 124)) {
  1350. pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
  1351. memcpy(iop_data, pQbuffer, 1);
  1352. acb->wqbuf_firstindex++;
  1353. acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1354. iop_data++;
  1355. allxfer_len++;
  1356. }
  1357. pwbuffer->data_len = allxfer_len;
  1358. arcmsr_iop_message_wrote(acb);
  1359. }
  1360. if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
  1361. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1362. }
  1363. }
  1364. static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
  1365. {
  1366. uint32_t outbound_doorbell;
  1367. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1368. outbound_doorbell = readl(&reg->outbound_doorbell);
  1369. writel(outbound_doorbell, &reg->outbound_doorbell);
  1370. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
  1371. arcmsr_iop2drv_data_wrote_handle(acb);
  1372. }
  1373. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
  1374. arcmsr_iop2drv_data_read_handle(acb);
  1375. }
  1376. }
  1377. static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *pACB)
  1378. {
  1379. uint32_t outbound_doorbell;
  1380. struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
  1381. /*
  1382. *******************************************************************
  1383. ** Maybe here we need to check wrqbuffer_lock is lock or not
  1384. ** DOORBELL: din! don!
  1385. ** check if there are any mail need to pack from firmware
  1386. *******************************************************************
  1387. */
  1388. outbound_doorbell = readl(&reg->outbound_doorbell);
  1389. writel(outbound_doorbell, &reg->outbound_doorbell_clear);/*clear interrupt*/
  1390. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
  1391. arcmsr_iop2drv_data_wrote_handle(pACB);
  1392. }
  1393. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
  1394. arcmsr_iop2drv_data_read_handle(pACB);
  1395. }
  1396. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  1397. arcmsr_hbc_message_isr(pACB); /* messenger of "driver to iop commands" */
  1398. }
  1399. return;
  1400. }
  1401. static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
  1402. {
  1403. uint32_t flag_ccb;
  1404. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1405. struct ARCMSR_CDB *pARCMSR_CDB;
  1406. struct CommandControlBlock *pCCB;
  1407. bool error;
  1408. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  1409. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1410. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1411. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1412. arcmsr_drain_donequeue(acb, pCCB, error);
  1413. }
  1414. }
  1415. static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
  1416. {
  1417. uint32_t index;
  1418. uint32_t flag_ccb;
  1419. struct MessageUnit_B *reg = acb->pmuB;
  1420. struct ARCMSR_CDB *pARCMSR_CDB;
  1421. struct CommandControlBlock *pCCB;
  1422. bool error;
  1423. index = reg->doneq_index;
  1424. while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
  1425. writel(0, &reg->done_qbuffer[index]);
  1426. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1427. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1428. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1429. arcmsr_drain_donequeue(acb, pCCB, error);
  1430. index++;
  1431. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1432. reg->doneq_index = index;
  1433. }
  1434. }
  1435. static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
  1436. {
  1437. struct MessageUnit_C *phbcmu;
  1438. struct ARCMSR_CDB *arcmsr_cdb;
  1439. struct CommandControlBlock *ccb;
  1440. uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
  1441. int error;
  1442. phbcmu = (struct MessageUnit_C *)acb->pmuC;
  1443. /* areca cdb command done */
  1444. /* Use correct offset and size for syncing */
  1445. while (readl(&phbcmu->host_int_status) &
  1446. ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR){
  1447. /* check if command done with no error*/
  1448. flag_ccb = readl(&phbcmu->outbound_queueport_low);
  1449. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);/*frame must be 32 bytes aligned*/
  1450. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
  1451. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  1452. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  1453. /* check if command done with no error */
  1454. arcmsr_drain_donequeue(acb, ccb, error);
  1455. if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
  1456. writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, &phbcmu->inbound_doorbell);
  1457. break;
  1458. }
  1459. throttling++;
  1460. }
  1461. }
  1462. /*
  1463. **********************************************************************************
  1464. ** Handle a message interrupt
  1465. **
  1466. ** The only message interrupt we expect is in response to a query for the current adapter config.
  1467. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  1468. **********************************************************************************
  1469. */
  1470. static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb)
  1471. {
  1472. struct MessageUnit_A *reg = acb->pmuA;
  1473. /*clear interrupt and message state*/
  1474. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
  1475. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1476. }
  1477. static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb)
  1478. {
  1479. struct MessageUnit_B *reg = acb->pmuB;
  1480. /*clear interrupt and message state*/
  1481. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  1482. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1483. }
  1484. /*
  1485. **********************************************************************************
  1486. ** Handle a message interrupt
  1487. **
  1488. ** The only message interrupt we expect is in response to a query for the
  1489. ** current adapter config.
  1490. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  1491. **********************************************************************************
  1492. */
  1493. static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb)
  1494. {
  1495. struct MessageUnit_C *reg = acb->pmuC;
  1496. /*clear interrupt and message state*/
  1497. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
  1498. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1499. }
  1500. static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
  1501. {
  1502. uint32_t outbound_intstatus;
  1503. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1504. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1505. acb->outbound_int_enable;
  1506. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
  1507. return 1;
  1508. }
  1509. writel(outbound_intstatus, &reg->outbound_intstatus);
  1510. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
  1511. arcmsr_hba_doorbell_isr(acb);
  1512. }
  1513. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
  1514. arcmsr_hba_postqueue_isr(acb);
  1515. }
  1516. if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  1517. /* messenger of "driver to iop commands" */
  1518. arcmsr_hba_message_isr(acb);
  1519. }
  1520. return 0;
  1521. }
  1522. static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
  1523. {
  1524. uint32_t outbound_doorbell;
  1525. struct MessageUnit_B *reg = acb->pmuB;
  1526. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  1527. acb->outbound_int_enable;
  1528. if (!outbound_doorbell)
  1529. return 1;
  1530. writel(~outbound_doorbell, reg->iop2drv_doorbell);
  1531. /*in case the last action of doorbell interrupt clearance is cached,
  1532. this action can push HW to write down the clear bit*/
  1533. readl(reg->iop2drv_doorbell);
  1534. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  1535. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
  1536. arcmsr_iop2drv_data_wrote_handle(acb);
  1537. }
  1538. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
  1539. arcmsr_iop2drv_data_read_handle(acb);
  1540. }
  1541. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
  1542. arcmsr_hbb_postqueue_isr(acb);
  1543. }
  1544. if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  1545. /* messenger of "driver to iop commands" */
  1546. arcmsr_hbb_message_isr(acb);
  1547. }
  1548. return 0;
  1549. }
  1550. static int arcmsr_handle_hbc_isr(struct AdapterControlBlock *pACB)
  1551. {
  1552. uint32_t host_interrupt_status;
  1553. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
  1554. /*
  1555. *********************************************
  1556. ** check outbound intstatus
  1557. *********************************************
  1558. */
  1559. host_interrupt_status = readl(&phbcmu->host_int_status);
  1560. if (!host_interrupt_status) {
  1561. /*it must be share irq*/
  1562. return 1;
  1563. }
  1564. /* MU ioctl transfer doorbell interrupts*/
  1565. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
  1566. arcmsr_hbc_doorbell_isr(pACB); /* messenger of "ioctl message read write" */
  1567. }
  1568. /* MU post queue interrupts*/
  1569. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
  1570. arcmsr_hbc_postqueue_isr(pACB); /* messenger of "scsi commands" */
  1571. }
  1572. return 0;
  1573. }
  1574. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  1575. {
  1576. switch (acb->adapter_type) {
  1577. case ACB_ADAPTER_TYPE_A: {
  1578. if (arcmsr_handle_hba_isr(acb)) {
  1579. return IRQ_NONE;
  1580. }
  1581. }
  1582. break;
  1583. case ACB_ADAPTER_TYPE_B: {
  1584. if (arcmsr_handle_hbb_isr(acb)) {
  1585. return IRQ_NONE;
  1586. }
  1587. }
  1588. break;
  1589. case ACB_ADAPTER_TYPE_C: {
  1590. if (arcmsr_handle_hbc_isr(acb)) {
  1591. return IRQ_NONE;
  1592. }
  1593. }
  1594. }
  1595. return IRQ_HANDLED;
  1596. }
  1597. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  1598. {
  1599. if (acb) {
  1600. /* stop adapter background rebuild */
  1601. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  1602. uint32_t intmask_org;
  1603. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1604. intmask_org = arcmsr_disable_outbound_ints(acb);
  1605. arcmsr_stop_adapter_bgrb(acb);
  1606. arcmsr_flush_adapter_cache(acb);
  1607. arcmsr_enable_outbound_ints(acb, intmask_org);
  1608. }
  1609. }
  1610. }
  1611. void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
  1612. {
  1613. int32_t wqbuf_firstindex, wqbuf_lastindex;
  1614. uint8_t *pQbuffer;
  1615. struct QBUFFER __iomem *pwbuffer;
  1616. uint8_t __iomem *iop_data;
  1617. int32_t allxfer_len = 0;
  1618. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1619. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1620. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1621. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1622. wqbuf_firstindex = acb->wqbuf_firstindex;
  1623. wqbuf_lastindex = acb->wqbuf_lastindex;
  1624. while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
  1625. pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
  1626. memcpy(iop_data, pQbuffer, 1);
  1627. wqbuf_firstindex++;
  1628. wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1629. iop_data++;
  1630. allxfer_len++;
  1631. }
  1632. acb->wqbuf_firstindex = wqbuf_firstindex;
  1633. pwbuffer->data_len = allxfer_len;
  1634. arcmsr_iop_message_wrote(acb);
  1635. }
  1636. }
  1637. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  1638. struct scsi_cmnd *cmd)
  1639. {
  1640. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  1641. int retvalue = 0, transfer_len = 0;
  1642. char *buffer;
  1643. struct scatterlist *sg;
  1644. uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
  1645. (uint32_t ) cmd->cmnd[6] << 16 |
  1646. (uint32_t ) cmd->cmnd[7] << 8 |
  1647. (uint32_t ) cmd->cmnd[8];
  1648. /* 4 bytes: Areca io control code */
  1649. sg = scsi_sglist(cmd);
  1650. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1651. if (scsi_sg_count(cmd) > 1) {
  1652. retvalue = ARCMSR_MESSAGE_FAIL;
  1653. goto message_out;
  1654. }
  1655. transfer_len += sg->length;
  1656. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  1657. retvalue = ARCMSR_MESSAGE_FAIL;
  1658. goto message_out;
  1659. }
  1660. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
  1661. switch(controlcode) {
  1662. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  1663. unsigned char *ver_addr;
  1664. uint8_t *pQbuffer, *ptmpQbuffer;
  1665. int32_t allxfer_len = 0;
  1666. ver_addr = kmalloc(1032, GFP_ATOMIC);
  1667. if (!ver_addr) {
  1668. retvalue = ARCMSR_MESSAGE_FAIL;
  1669. goto message_out;
  1670. }
  1671. ptmpQbuffer = ver_addr;
  1672. while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
  1673. && (allxfer_len < 1031)) {
  1674. pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
  1675. memcpy(ptmpQbuffer, pQbuffer, 1);
  1676. acb->rqbuf_firstindex++;
  1677. acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1678. ptmpQbuffer++;
  1679. allxfer_len++;
  1680. }
  1681. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1682. struct QBUFFER __iomem *prbuffer;
  1683. uint8_t __iomem *iop_data;
  1684. int32_t iop_len;
  1685. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1686. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1687. iop_data = prbuffer->data;
  1688. iop_len = readl(&prbuffer->data_len);
  1689. while (iop_len > 0) {
  1690. acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
  1691. acb->rqbuf_lastindex++;
  1692. acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1693. iop_data++;
  1694. iop_len--;
  1695. }
  1696. arcmsr_iop_message_read(acb);
  1697. }
  1698. memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, allxfer_len);
  1699. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  1700. if(acb->fw_flag == FW_DEADLOCK) {
  1701. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1702. }else{
  1703. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1704. }
  1705. kfree(ver_addr);
  1706. }
  1707. break;
  1708. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  1709. unsigned char *ver_addr;
  1710. int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
  1711. uint8_t *pQbuffer, *ptmpuserbuffer;
  1712. ver_addr = kmalloc(1032, GFP_ATOMIC);
  1713. if (!ver_addr) {
  1714. retvalue = ARCMSR_MESSAGE_FAIL;
  1715. goto message_out;
  1716. }
  1717. if(acb->fw_flag == FW_DEADLOCK) {
  1718. pcmdmessagefld->cmdmessage.ReturnCode =
  1719. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1720. }else{
  1721. pcmdmessagefld->cmdmessage.ReturnCode =
  1722. ARCMSR_MESSAGE_RETURNCODE_OK;
  1723. }
  1724. ptmpuserbuffer = ver_addr;
  1725. user_len = pcmdmessagefld->cmdmessage.Length;
  1726. memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
  1727. wqbuf_lastindex = acb->wqbuf_lastindex;
  1728. wqbuf_firstindex = acb->wqbuf_firstindex;
  1729. if (wqbuf_lastindex != wqbuf_firstindex) {
  1730. struct SENSE_DATA *sensebuffer =
  1731. (struct SENSE_DATA *)cmd->sense_buffer;
  1732. arcmsr_post_ioctldata2iop(acb);
  1733. /* has error report sensedata */
  1734. sensebuffer->ErrorCode = 0x70;
  1735. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1736. sensebuffer->AdditionalSenseLength = 0x0A;
  1737. sensebuffer->AdditionalSenseCode = 0x20;
  1738. sensebuffer->Valid = 1;
  1739. retvalue = ARCMSR_MESSAGE_FAIL;
  1740. } else {
  1741. my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
  1742. &(ARCMSR_MAX_QBUFFER - 1);
  1743. if (my_empty_len >= user_len) {
  1744. while (user_len > 0) {
  1745. pQbuffer =
  1746. &acb->wqbuffer[acb->wqbuf_lastindex];
  1747. memcpy(pQbuffer, ptmpuserbuffer, 1);
  1748. acb->wqbuf_lastindex++;
  1749. acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1750. ptmpuserbuffer++;
  1751. user_len--;
  1752. }
  1753. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  1754. acb->acb_flags &=
  1755. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1756. arcmsr_post_ioctldata2iop(acb);
  1757. }
  1758. } else {
  1759. /* has error report sensedata */
  1760. struct SENSE_DATA *sensebuffer =
  1761. (struct SENSE_DATA *)cmd->sense_buffer;
  1762. sensebuffer->ErrorCode = 0x70;
  1763. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1764. sensebuffer->AdditionalSenseLength = 0x0A;
  1765. sensebuffer->AdditionalSenseCode = 0x20;
  1766. sensebuffer->Valid = 1;
  1767. retvalue = ARCMSR_MESSAGE_FAIL;
  1768. }
  1769. }
  1770. kfree(ver_addr);
  1771. }
  1772. break;
  1773. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  1774. uint8_t *pQbuffer = acb->rqbuffer;
  1775. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1776. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1777. arcmsr_iop_message_read(acb);
  1778. }
  1779. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  1780. acb->rqbuf_firstindex = 0;
  1781. acb->rqbuf_lastindex = 0;
  1782. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1783. if(acb->fw_flag == FW_DEADLOCK) {
  1784. pcmdmessagefld->cmdmessage.ReturnCode =
  1785. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1786. }else{
  1787. pcmdmessagefld->cmdmessage.ReturnCode =
  1788. ARCMSR_MESSAGE_RETURNCODE_OK;
  1789. }
  1790. }
  1791. break;
  1792. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  1793. uint8_t *pQbuffer = acb->wqbuffer;
  1794. if(acb->fw_flag == FW_DEADLOCK) {
  1795. pcmdmessagefld->cmdmessage.ReturnCode =
  1796. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1797. }else{
  1798. pcmdmessagefld->cmdmessage.ReturnCode =
  1799. ARCMSR_MESSAGE_RETURNCODE_OK;
  1800. }
  1801. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1802. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1803. arcmsr_iop_message_read(acb);
  1804. }
  1805. acb->acb_flags |=
  1806. (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  1807. ACB_F_MESSAGE_WQBUFFER_READED);
  1808. acb->wqbuf_firstindex = 0;
  1809. acb->wqbuf_lastindex = 0;
  1810. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1811. }
  1812. break;
  1813. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  1814. uint8_t *pQbuffer;
  1815. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1816. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1817. arcmsr_iop_message_read(acb);
  1818. }
  1819. acb->acb_flags |=
  1820. (ACB_F_MESSAGE_WQBUFFER_CLEARED
  1821. | ACB_F_MESSAGE_RQBUFFER_CLEARED
  1822. | ACB_F_MESSAGE_WQBUFFER_READED);
  1823. acb->rqbuf_firstindex = 0;
  1824. acb->rqbuf_lastindex = 0;
  1825. acb->wqbuf_firstindex = 0;
  1826. acb->wqbuf_lastindex = 0;
  1827. pQbuffer = acb->rqbuffer;
  1828. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1829. pQbuffer = acb->wqbuffer;
  1830. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1831. if(acb->fw_flag == FW_DEADLOCK) {
  1832. pcmdmessagefld->cmdmessage.ReturnCode =
  1833. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1834. }else{
  1835. pcmdmessagefld->cmdmessage.ReturnCode =
  1836. ARCMSR_MESSAGE_RETURNCODE_OK;
  1837. }
  1838. }
  1839. break;
  1840. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  1841. if(acb->fw_flag == FW_DEADLOCK) {
  1842. pcmdmessagefld->cmdmessage.ReturnCode =
  1843. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1844. }else{
  1845. pcmdmessagefld->cmdmessage.ReturnCode =
  1846. ARCMSR_MESSAGE_RETURNCODE_3F;
  1847. }
  1848. break;
  1849. }
  1850. case ARCMSR_MESSAGE_SAY_HELLO: {
  1851. int8_t *hello_string = "Hello! I am ARCMSR";
  1852. if(acb->fw_flag == FW_DEADLOCK) {
  1853. pcmdmessagefld->cmdmessage.ReturnCode =
  1854. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1855. }else{
  1856. pcmdmessagefld->cmdmessage.ReturnCode =
  1857. ARCMSR_MESSAGE_RETURNCODE_OK;
  1858. }
  1859. memcpy(pcmdmessagefld->messagedatabuffer, hello_string
  1860. , (int16_t)strlen(hello_string));
  1861. }
  1862. break;
  1863. case ARCMSR_MESSAGE_SAY_GOODBYE:
  1864. if(acb->fw_flag == FW_DEADLOCK) {
  1865. pcmdmessagefld->cmdmessage.ReturnCode =
  1866. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1867. }
  1868. arcmsr_iop_parking(acb);
  1869. break;
  1870. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
  1871. if(acb->fw_flag == FW_DEADLOCK) {
  1872. pcmdmessagefld->cmdmessage.ReturnCode =
  1873. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  1874. }
  1875. arcmsr_flush_adapter_cache(acb);
  1876. break;
  1877. default:
  1878. retvalue = ARCMSR_MESSAGE_FAIL;
  1879. }
  1880. message_out:
  1881. sg = scsi_sglist(cmd);
  1882. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1883. return retvalue;
  1884. }
  1885. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  1886. {
  1887. struct list_head *head = &acb->ccb_free_list;
  1888. struct CommandControlBlock *ccb = NULL;
  1889. unsigned long flags;
  1890. spin_lock_irqsave(&acb->ccblist_lock, flags);
  1891. if (!list_empty(head)) {
  1892. ccb = list_entry(head->next, struct CommandControlBlock, list);
  1893. list_del_init(&ccb->list);
  1894. }else{
  1895. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  1896. return 0;
  1897. }
  1898. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  1899. return ccb;
  1900. }
  1901. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  1902. struct scsi_cmnd *cmd)
  1903. {
  1904. switch (cmd->cmnd[0]) {
  1905. case INQUIRY: {
  1906. unsigned char inqdata[36];
  1907. char *buffer;
  1908. struct scatterlist *sg;
  1909. if (cmd->device->lun) {
  1910. cmd->result = (DID_TIME_OUT << 16);
  1911. cmd->scsi_done(cmd);
  1912. return;
  1913. }
  1914. inqdata[0] = TYPE_PROCESSOR;
  1915. /* Periph Qualifier & Periph Dev Type */
  1916. inqdata[1] = 0;
  1917. /* rem media bit & Dev Type Modifier */
  1918. inqdata[2] = 0;
  1919. /* ISO, ECMA, & ANSI versions */
  1920. inqdata[4] = 31;
  1921. /* length of additional data */
  1922. strncpy(&inqdata[8], "Areca ", 8);
  1923. /* Vendor Identification */
  1924. strncpy(&inqdata[16], "RAID controller ", 16);
  1925. /* Product Identification */
  1926. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  1927. sg = scsi_sglist(cmd);
  1928. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1929. memcpy(buffer, inqdata, sizeof(inqdata));
  1930. sg = scsi_sglist(cmd);
  1931. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1932. cmd->scsi_done(cmd);
  1933. }
  1934. break;
  1935. case WRITE_BUFFER:
  1936. case READ_BUFFER: {
  1937. if (arcmsr_iop_message_xfer(acb, cmd))
  1938. cmd->result = (DID_ERROR << 16);
  1939. cmd->scsi_done(cmd);
  1940. }
  1941. break;
  1942. default:
  1943. cmd->scsi_done(cmd);
  1944. }
  1945. }
  1946. static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
  1947. void (* done)(struct scsi_cmnd *))
  1948. {
  1949. struct Scsi_Host *host = cmd->device->host;
  1950. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  1951. struct CommandControlBlock *ccb;
  1952. int target = cmd->device->id;
  1953. int lun = cmd->device->lun;
  1954. uint8_t scsicmd = cmd->cmnd[0];
  1955. cmd->scsi_done = done;
  1956. cmd->host_scribble = NULL;
  1957. cmd->result = 0;
  1958. if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
  1959. if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
  1960. cmd->result = (DID_NO_CONNECT << 16);
  1961. }
  1962. cmd->scsi_done(cmd);
  1963. return 0;
  1964. }
  1965. if (target == 16) {
  1966. /* virtual device for iop message transfer */
  1967. arcmsr_handle_virtual_command(acb, cmd);
  1968. return 0;
  1969. }
  1970. if (atomic_read(&acb->ccboutstandingcount) >=
  1971. ARCMSR_MAX_OUTSTANDING_CMD)
  1972. return SCSI_MLQUEUE_HOST_BUSY;
  1973. ccb = arcmsr_get_freeccb(acb);
  1974. if (!ccb)
  1975. return SCSI_MLQUEUE_HOST_BUSY;
  1976. if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
  1977. cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
  1978. cmd->scsi_done(cmd);
  1979. return 0;
  1980. }
  1981. arcmsr_post_ccb(acb, ccb);
  1982. return 0;
  1983. }
  1984. static DEF_SCSI_QCMD(arcmsr_queue_command)
  1985. static bool arcmsr_get_hba_config(struct AdapterControlBlock *acb)
  1986. {
  1987. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1988. char *acb_firm_model = acb->firm_model;
  1989. char *acb_firm_version = acb->firm_version;
  1990. char *acb_device_map = acb->device_map;
  1991. char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
  1992. char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
  1993. char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
  1994. int count;
  1995. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  1996. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  1997. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1998. miscellaneous data' timeout \n", acb->host->host_no);
  1999. return false;
  2000. }
  2001. count = 8;
  2002. while (count){
  2003. *acb_firm_model = readb(iop_firm_model);
  2004. acb_firm_model++;
  2005. iop_firm_model++;
  2006. count--;
  2007. }
  2008. count = 16;
  2009. while (count){
  2010. *acb_firm_version = readb(iop_firm_version);
  2011. acb_firm_version++;
  2012. iop_firm_version++;
  2013. count--;
  2014. }
  2015. count=16;
  2016. while(count){
  2017. *acb_device_map = readb(iop_device_map);
  2018. acb_device_map++;
  2019. iop_device_map++;
  2020. count--;
  2021. }
  2022. printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
  2023. acb->host->host_no,
  2024. acb->firm_version,
  2025. acb->firm_model);
  2026. acb->signature = readl(&reg->message_rwbuffer[0]);
  2027. acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
  2028. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
  2029. acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
  2030. acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
  2031. acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2032. return true;
  2033. }
  2034. static bool arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
  2035. {
  2036. struct MessageUnit_B *reg = acb->pmuB;
  2037. struct pci_dev *pdev = acb->pdev;
  2038. void *dma_coherent;
  2039. dma_addr_t dma_coherent_handle;
  2040. char *acb_firm_model = acb->firm_model;
  2041. char *acb_firm_version = acb->firm_version;
  2042. char *acb_device_map = acb->device_map;
  2043. char __iomem *iop_firm_model;
  2044. /*firm_model,15,60-67*/
  2045. char __iomem *iop_firm_version;
  2046. /*firm_version,17,68-83*/
  2047. char __iomem *iop_device_map;
  2048. /*firm_version,21,84-99*/
  2049. int count;
  2050. dma_coherent = dma_alloc_coherent(&pdev->dev, sizeof(struct MessageUnit_B), &dma_coherent_handle, GFP_KERNEL);
  2051. if (!dma_coherent){
  2052. printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error for hbb mu\n", acb->host->host_no);
  2053. return false;
  2054. }
  2055. acb->dma_coherent_handle_hbb_mu = dma_coherent_handle;
  2056. reg = (struct MessageUnit_B *)dma_coherent;
  2057. acb->pmuB = reg;
  2058. reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
  2059. reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
  2060. reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
  2061. reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
  2062. reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
  2063. reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
  2064. reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
  2065. iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
  2066. iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
  2067. iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
  2068. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  2069. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2070. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2071. miscellaneous data' timeout \n", acb->host->host_no);
  2072. return false;
  2073. }
  2074. count = 8;
  2075. while (count){
  2076. *acb_firm_model = readb(iop_firm_model);
  2077. acb_firm_model++;
  2078. iop_firm_model++;
  2079. count--;
  2080. }
  2081. count = 16;
  2082. while (count){
  2083. *acb_firm_version = readb(iop_firm_version);
  2084. acb_firm_version++;
  2085. iop_firm_version++;
  2086. count--;
  2087. }
  2088. count = 16;
  2089. while(count){
  2090. *acb_device_map = readb(iop_device_map);
  2091. acb_device_map++;
  2092. iop_device_map++;
  2093. count--;
  2094. }
  2095. printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
  2096. acb->host->host_no,
  2097. acb->firm_version,
  2098. acb->firm_model);
  2099. acb->signature = readl(&reg->message_rwbuffer[1]);
  2100. /*firm_signature,1,00-03*/
  2101. acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
  2102. /*firm_request_len,1,04-07*/
  2103. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
  2104. /*firm_numbers_queue,2,08-11*/
  2105. acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
  2106. /*firm_sdram_size,3,12-15*/
  2107. acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
  2108. /*firm_ide_channels,4,16-19*/
  2109. acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2110. /*firm_ide_channels,4,16-19*/
  2111. return true;
  2112. }
  2113. static bool arcmsr_get_hbc_config(struct AdapterControlBlock *pACB)
  2114. {
  2115. uint32_t intmask_org, Index, firmware_state = 0;
  2116. struct MessageUnit_C *reg = pACB->pmuC;
  2117. char *acb_firm_model = pACB->firm_model;
  2118. char *acb_firm_version = pACB->firm_version;
  2119. char *iop_firm_model = (char *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
  2120. char *iop_firm_version = (char *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
  2121. int count;
  2122. /* disable all outbound interrupt */
  2123. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  2124. writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  2125. /* wait firmware ready */
  2126. do {
  2127. firmware_state = readl(&reg->outbound_msgaddr1);
  2128. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  2129. /* post "get config" instruction */
  2130. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2131. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2132. /* wait message ready */
  2133. for (Index = 0; Index < 2000; Index++) {
  2134. if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  2135. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
  2136. break;
  2137. }
  2138. udelay(10);
  2139. } /*max 1 seconds*/
  2140. if (Index >= 2000) {
  2141. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2142. miscellaneous data' timeout \n", pACB->host->host_no);
  2143. return false;
  2144. }
  2145. count = 8;
  2146. while (count) {
  2147. *acb_firm_model = readb(iop_firm_model);
  2148. acb_firm_model++;
  2149. iop_firm_model++;
  2150. count--;
  2151. }
  2152. count = 16;
  2153. while (count) {
  2154. *acb_firm_version = readb(iop_firm_version);
  2155. acb_firm_version++;
  2156. iop_firm_version++;
  2157. count--;
  2158. }
  2159. printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
  2160. pACB->host->host_no,
  2161. pACB->firm_version,
  2162. pACB->firm_model);
  2163. pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
  2164. pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
  2165. pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
  2166. pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
  2167. pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2168. /*all interrupt service will be enable at arcmsr_iop_init*/
  2169. return true;
  2170. }
  2171. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  2172. {
  2173. if (acb->adapter_type == ACB_ADAPTER_TYPE_A)
  2174. return arcmsr_get_hba_config(acb);
  2175. else if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
  2176. return arcmsr_get_hbb_config(acb);
  2177. else
  2178. return arcmsr_get_hbc_config(acb);
  2179. }
  2180. static int arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
  2181. struct CommandControlBlock *poll_ccb)
  2182. {
  2183. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2184. struct CommandControlBlock *ccb;
  2185. struct ARCMSR_CDB *arcmsr_cdb;
  2186. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  2187. int rtn;
  2188. bool error;
  2189. polling_hba_ccb_retry:
  2190. poll_count++;
  2191. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  2192. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  2193. while (1) {
  2194. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  2195. if (poll_ccb_done){
  2196. rtn = SUCCESS;
  2197. break;
  2198. }else {
  2199. msleep(25);
  2200. if (poll_count > 100){
  2201. rtn = FAILED;
  2202. break;
  2203. }
  2204. goto polling_hba_ccb_retry;
  2205. }
  2206. }
  2207. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  2208. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2209. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  2210. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  2211. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  2212. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2213. " poll command abort successfully \n"
  2214. , acb->host->host_no
  2215. , ccb->pcmd->device->id
  2216. , ccb->pcmd->device->lun
  2217. , ccb);
  2218. ccb->pcmd->result = DID_ABORT << 16;
  2219. arcmsr_ccb_complete(ccb);
  2220. continue;
  2221. }
  2222. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2223. " command done ccb = '0x%p'"
  2224. "ccboutstandingcount = %d \n"
  2225. , acb->host->host_no
  2226. , ccb
  2227. , atomic_read(&acb->ccboutstandingcount));
  2228. continue;
  2229. }
  2230. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2231. arcmsr_report_ccb_state(acb, ccb, error);
  2232. }
  2233. return rtn;
  2234. }
  2235. static int arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb,
  2236. struct CommandControlBlock *poll_ccb)
  2237. {
  2238. struct MessageUnit_B *reg = acb->pmuB;
  2239. struct ARCMSR_CDB *arcmsr_cdb;
  2240. struct CommandControlBlock *ccb;
  2241. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  2242. int index, rtn;
  2243. bool error;
  2244. polling_hbb_ccb_retry:
  2245. poll_count++;
  2246. /* clear doorbell interrupt */
  2247. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  2248. while(1){
  2249. index = reg->doneq_index;
  2250. if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
  2251. if (poll_ccb_done){
  2252. rtn = SUCCESS;
  2253. break;
  2254. }else {
  2255. msleep(25);
  2256. if (poll_count > 100){
  2257. rtn = FAILED;
  2258. break;
  2259. }
  2260. goto polling_hbb_ccb_retry;
  2261. }
  2262. }
  2263. writel(0, &reg->done_qbuffer[index]);
  2264. index++;
  2265. /*if last index number set it to 0 */
  2266. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  2267. reg->doneq_index = index;
  2268. /* check if command done with no error*/
  2269. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  2270. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2271. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  2272. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  2273. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  2274. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2275. " poll command abort successfully \n"
  2276. ,acb->host->host_no
  2277. ,ccb->pcmd->device->id
  2278. ,ccb->pcmd->device->lun
  2279. ,ccb);
  2280. ccb->pcmd->result = DID_ABORT << 16;
  2281. arcmsr_ccb_complete(ccb);
  2282. continue;
  2283. }
  2284. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2285. " command done ccb = '0x%p'"
  2286. "ccboutstandingcount = %d \n"
  2287. , acb->host->host_no
  2288. , ccb
  2289. , atomic_read(&acb->ccboutstandingcount));
  2290. continue;
  2291. }
  2292. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2293. arcmsr_report_ccb_state(acb, ccb, error);
  2294. }
  2295. return rtn;
  2296. }
  2297. static int arcmsr_polling_hbc_ccbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_ccb)
  2298. {
  2299. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  2300. uint32_t flag_ccb, ccb_cdb_phy;
  2301. struct ARCMSR_CDB *arcmsr_cdb;
  2302. bool error;
  2303. struct CommandControlBlock *pCCB;
  2304. uint32_t poll_ccb_done = 0, poll_count = 0;
  2305. int rtn;
  2306. polling_hbc_ccb_retry:
  2307. poll_count++;
  2308. while (1) {
  2309. if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
  2310. if (poll_ccb_done) {
  2311. rtn = SUCCESS;
  2312. break;
  2313. } else {
  2314. msleep(25);
  2315. if (poll_count > 100) {
  2316. rtn = FAILED;
  2317. break;
  2318. }
  2319. goto polling_hbc_ccb_retry;
  2320. }
  2321. }
  2322. flag_ccb = readl(&reg->outbound_queueport_low);
  2323. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  2324. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  2325. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2326. poll_ccb_done = (pCCB == poll_ccb) ? 1 : 0;
  2327. /* check ifcommand done with no error*/
  2328. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  2329. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  2330. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2331. " poll command abort successfully \n"
  2332. , acb->host->host_no
  2333. , pCCB->pcmd->device->id
  2334. , pCCB->pcmd->device->lun
  2335. , pCCB);
  2336. pCCB->pcmd->result = DID_ABORT << 16;
  2337. arcmsr_ccb_complete(pCCB);
  2338. continue;
  2339. }
  2340. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2341. " command done ccb = '0x%p'"
  2342. "ccboutstandingcount = %d \n"
  2343. , acb->host->host_no
  2344. , pCCB
  2345. , atomic_read(&acb->ccboutstandingcount));
  2346. continue;
  2347. }
  2348. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  2349. arcmsr_report_ccb_state(acb, pCCB, error);
  2350. }
  2351. return rtn;
  2352. }
  2353. static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
  2354. struct CommandControlBlock *poll_ccb)
  2355. {
  2356. int rtn = 0;
  2357. switch (acb->adapter_type) {
  2358. case ACB_ADAPTER_TYPE_A: {
  2359. rtn = arcmsr_polling_hba_ccbdone(acb, poll_ccb);
  2360. }
  2361. break;
  2362. case ACB_ADAPTER_TYPE_B: {
  2363. rtn = arcmsr_polling_hbb_ccbdone(acb, poll_ccb);
  2364. }
  2365. break;
  2366. case ACB_ADAPTER_TYPE_C: {
  2367. rtn = arcmsr_polling_hbc_ccbdone(acb, poll_ccb);
  2368. }
  2369. }
  2370. return rtn;
  2371. }
  2372. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  2373. {
  2374. uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
  2375. dma_addr_t dma_coherent_handle;
  2376. /*
  2377. ********************************************************************
  2378. ** here we need to tell iop 331 our freeccb.HighPart
  2379. ** if freeccb.HighPart is not zero
  2380. ********************************************************************
  2381. */
  2382. dma_coherent_handle = acb->dma_coherent_handle;
  2383. cdb_phyaddr = (uint32_t)(dma_coherent_handle);
  2384. cdb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
  2385. acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
  2386. /*
  2387. ***********************************************************************
  2388. ** if adapter type B, set window of "post command Q"
  2389. ***********************************************************************
  2390. */
  2391. switch (acb->adapter_type) {
  2392. case ACB_ADAPTER_TYPE_A: {
  2393. if (cdb_phyaddr_hi32 != 0) {
  2394. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2395. uint32_t intmask_org;
  2396. intmask_org = arcmsr_disable_outbound_ints(acb);
  2397. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  2398. &reg->message_rwbuffer[0]);
  2399. writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  2400. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  2401. &reg->inbound_msgaddr0);
  2402. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  2403. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  2404. part physical address timeout\n",
  2405. acb->host->host_no);
  2406. return 1;
  2407. }
  2408. arcmsr_enable_outbound_ints(acb, intmask_org);
  2409. }
  2410. }
  2411. break;
  2412. case ACB_ADAPTER_TYPE_B: {
  2413. unsigned long post_queue_phyaddr;
  2414. uint32_t __iomem *rwbuffer;
  2415. struct MessageUnit_B *reg = acb->pmuB;
  2416. uint32_t intmask_org;
  2417. intmask_org = arcmsr_disable_outbound_ints(acb);
  2418. reg->postq_index = 0;
  2419. reg->doneq_index = 0;
  2420. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
  2421. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2422. printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
  2423. acb->host->host_no);
  2424. return 1;
  2425. }
  2426. post_queue_phyaddr = acb->dma_coherent_handle_hbb_mu;
  2427. rwbuffer = reg->message_rwbuffer;
  2428. /* driver "set config" signature */
  2429. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  2430. /* normal should be zero */
  2431. writel(cdb_phyaddr_hi32, rwbuffer++);
  2432. /* postQ size (256 + 8)*4 */
  2433. writel(post_queue_phyaddr, rwbuffer++);
  2434. /* doneQ size (256 + 8)*4 */
  2435. writel(post_queue_phyaddr + 1056, rwbuffer++);
  2436. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  2437. writel(1056, rwbuffer);
  2438. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
  2439. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2440. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  2441. timeout \n",acb->host->host_no);
  2442. return 1;
  2443. }
  2444. arcmsr_hbb_enable_driver_mode(acb);
  2445. arcmsr_enable_outbound_ints(acb, intmask_org);
  2446. }
  2447. break;
  2448. case ACB_ADAPTER_TYPE_C: {
  2449. if (cdb_phyaddr_hi32 != 0) {
  2450. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  2451. if (cdb_phyaddr_hi32 != 0) {
  2452. unsigned char Retries = 0x00;
  2453. do {
  2454. printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x \n", acb->adapter_index, cdb_phyaddr_hi32);
  2455. } while (Retries++ < 100);
  2456. }
  2457. writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
  2458. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
  2459. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  2460. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2461. if (!arcmsr_hbc_wait_msgint_ready(acb)) {
  2462. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  2463. timeout \n", acb->host->host_no);
  2464. return 1;
  2465. }
  2466. }
  2467. }
  2468. }
  2469. return 0;
  2470. }
  2471. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  2472. {
  2473. uint32_t firmware_state = 0;
  2474. switch (acb->adapter_type) {
  2475. case ACB_ADAPTER_TYPE_A: {
  2476. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2477. do {
  2478. firmware_state = readl(&reg->outbound_msgaddr1);
  2479. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  2480. }
  2481. break;
  2482. case ACB_ADAPTER_TYPE_B: {
  2483. struct MessageUnit_B *reg = acb->pmuB;
  2484. do {
  2485. firmware_state = readl(reg->iop2drv_doorbell);
  2486. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  2487. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  2488. }
  2489. break;
  2490. case ACB_ADAPTER_TYPE_C: {
  2491. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  2492. do {
  2493. firmware_state = readl(&reg->outbound_msgaddr1);
  2494. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  2495. }
  2496. }
  2497. }
  2498. static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb)
  2499. {
  2500. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2501. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
  2502. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2503. return;
  2504. } else {
  2505. acb->fw_flag = FW_NORMAL;
  2506. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
  2507. atomic_set(&acb->rq_map_token, 16);
  2508. }
  2509. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  2510. if (atomic_dec_and_test(&acb->rq_map_token)) {
  2511. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2512. return;
  2513. }
  2514. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2515. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2516. }
  2517. return;
  2518. }
  2519. static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb)
  2520. {
  2521. struct MessageUnit_B __iomem *reg = acb->pmuB;
  2522. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
  2523. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2524. return;
  2525. } else {
  2526. acb->fw_flag = FW_NORMAL;
  2527. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
  2528. atomic_set(&acb->rq_map_token, 16);
  2529. }
  2530. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  2531. if (atomic_dec_and_test(&acb->rq_map_token)) {
  2532. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2533. return;
  2534. }
  2535. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  2536. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2537. }
  2538. return;
  2539. }
  2540. static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb)
  2541. {
  2542. struct MessageUnit_C __iomem *reg = acb->pmuC;
  2543. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
  2544. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2545. return;
  2546. } else {
  2547. acb->fw_flag = FW_NORMAL;
  2548. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
  2549. atomic_set(&acb->rq_map_token, 16);
  2550. }
  2551. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  2552. if (atomic_dec_and_test(&acb->rq_map_token)) {
  2553. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2554. return;
  2555. }
  2556. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2557. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2558. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2559. }
  2560. return;
  2561. }
  2562. static void arcmsr_request_device_map(unsigned long pacb)
  2563. {
  2564. struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
  2565. switch (acb->adapter_type) {
  2566. case ACB_ADAPTER_TYPE_A: {
  2567. arcmsr_request_hba_device_map(acb);
  2568. }
  2569. break;
  2570. case ACB_ADAPTER_TYPE_B: {
  2571. arcmsr_request_hbb_device_map(acb);
  2572. }
  2573. break;
  2574. case ACB_ADAPTER_TYPE_C: {
  2575. arcmsr_request_hbc_device_map(acb);
  2576. }
  2577. }
  2578. }
  2579. static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
  2580. {
  2581. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2582. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  2583. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  2584. if (!arcmsr_hba_wait_msgint_ready(acb)) {
  2585. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  2586. rebulid' timeout \n", acb->host->host_no);
  2587. }
  2588. }
  2589. static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
  2590. {
  2591. struct MessageUnit_B *reg = acb->pmuB;
  2592. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  2593. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
  2594. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2595. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  2596. rebulid' timeout \n",acb->host->host_no);
  2597. }
  2598. }
  2599. static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *pACB)
  2600. {
  2601. struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
  2602. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  2603. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
  2604. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
  2605. if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
  2606. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  2607. rebulid' timeout \n", pACB->host->host_no);
  2608. }
  2609. return;
  2610. }
  2611. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  2612. {
  2613. switch (acb->adapter_type) {
  2614. case ACB_ADAPTER_TYPE_A:
  2615. arcmsr_start_hba_bgrb(acb);
  2616. break;
  2617. case ACB_ADAPTER_TYPE_B:
  2618. arcmsr_start_hbb_bgrb(acb);
  2619. break;
  2620. case ACB_ADAPTER_TYPE_C:
  2621. arcmsr_start_hbc_bgrb(acb);
  2622. }
  2623. }
  2624. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  2625. {
  2626. switch (acb->adapter_type) {
  2627. case ACB_ADAPTER_TYPE_A: {
  2628. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2629. uint32_t outbound_doorbell;
  2630. /* empty doorbell Qbuffer if door bell ringed */
  2631. outbound_doorbell = readl(&reg->outbound_doorbell);
  2632. /*clear doorbell interrupt */
  2633. writel(outbound_doorbell, &reg->outbound_doorbell);
  2634. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  2635. }
  2636. break;
  2637. case ACB_ADAPTER_TYPE_B: {
  2638. struct MessageUnit_B *reg = acb->pmuB;
  2639. /*clear interrupt and message state*/
  2640. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  2641. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  2642. /* let IOP know data has been read */
  2643. }
  2644. break;
  2645. case ACB_ADAPTER_TYPE_C: {
  2646. struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
  2647. uint32_t outbound_doorbell;
  2648. /* empty doorbell Qbuffer if door bell ringed */
  2649. outbound_doorbell = readl(&reg->outbound_doorbell);
  2650. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  2651. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  2652. }
  2653. }
  2654. }
  2655. static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
  2656. {
  2657. switch (acb->adapter_type) {
  2658. case ACB_ADAPTER_TYPE_A:
  2659. return;
  2660. case ACB_ADAPTER_TYPE_B:
  2661. {
  2662. struct MessageUnit_B *reg = acb->pmuB;
  2663. writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
  2664. if (!arcmsr_hbb_wait_msgint_ready(acb)) {
  2665. printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
  2666. return;
  2667. }
  2668. }
  2669. break;
  2670. case ACB_ADAPTER_TYPE_C:
  2671. return;
  2672. }
  2673. return;
  2674. }
  2675. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
  2676. {
  2677. uint8_t value[64];
  2678. int i, count = 0;
  2679. struct MessageUnit_A __iomem *pmuA = acb->pmuA;
  2680. struct MessageUnit_C __iomem *pmuC = acb->pmuC;
  2681. u32 temp = 0;
  2682. /* backup pci config data */
  2683. printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
  2684. for (i = 0; i < 64; i++) {
  2685. pci_read_config_byte(acb->pdev, i, &value[i]);
  2686. }
  2687. /* hardware reset signal */
  2688. if ((acb->dev_id == 0x1680)) {
  2689. writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
  2690. } else if ((acb->dev_id == 0x1880)) {
  2691. do {
  2692. count++;
  2693. writel(0xF, &pmuC->write_sequence);
  2694. writel(0x4, &pmuC->write_sequence);
  2695. writel(0xB, &pmuC->write_sequence);
  2696. writel(0x2, &pmuC->write_sequence);
  2697. writel(0x7, &pmuC->write_sequence);
  2698. writel(0xD, &pmuC->write_sequence);
  2699. } while ((((temp = readl(&pmuC->host_diagnostic)) | ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
  2700. writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
  2701. } else {
  2702. pci_write_config_byte(acb->pdev, 0x84, 0x20);
  2703. }
  2704. msleep(2000);
  2705. /* write back pci config data */
  2706. for (i = 0; i < 64; i++) {
  2707. pci_write_config_byte(acb->pdev, i, value[i]);
  2708. }
  2709. msleep(1000);
  2710. return;
  2711. }
  2712. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  2713. {
  2714. uint32_t intmask_org;
  2715. /* disable all outbound interrupt */
  2716. intmask_org = arcmsr_disable_outbound_ints(acb);
  2717. arcmsr_wait_firmware_ready(acb);
  2718. arcmsr_iop_confirm(acb);
  2719. /*start background rebuild*/
  2720. arcmsr_start_adapter_bgrb(acb);
  2721. /* empty doorbell Qbuffer if door bell ringed */
  2722. arcmsr_clear_doorbell_queue_buffer(acb);
  2723. arcmsr_enable_eoi_mode(acb);
  2724. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2725. arcmsr_enable_outbound_ints(acb, intmask_org);
  2726. acb->acb_flags |= ACB_F_IOP_INITED;
  2727. }
  2728. static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
  2729. {
  2730. struct CommandControlBlock *ccb;
  2731. uint32_t intmask_org;
  2732. uint8_t rtnval = 0x00;
  2733. int i = 0;
  2734. unsigned long flags;
  2735. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  2736. /* disable all outbound interrupt */
  2737. intmask_org = arcmsr_disable_outbound_ints(acb);
  2738. /* talk to iop 331 outstanding command aborted */
  2739. rtnval = arcmsr_abort_allcmd(acb);
  2740. /* clear all outbound posted Q */
  2741. arcmsr_done4abort_postqueue(acb);
  2742. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  2743. ccb = acb->pccb_pool[i];
  2744. if (ccb->startdone == ARCMSR_CCB_START) {
  2745. scsi_dma_unmap(ccb->pcmd);
  2746. ccb->startdone = ARCMSR_CCB_DONE;
  2747. ccb->ccb_flags = 0;
  2748. spin_lock_irqsave(&acb->ccblist_lock, flags);
  2749. list_add_tail(&ccb->list, &acb->ccb_free_list);
  2750. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2751. }
  2752. }
  2753. atomic_set(&acb->ccboutstandingcount, 0);
  2754. /* enable all outbound interrupt */
  2755. arcmsr_enable_outbound_ints(acb, intmask_org);
  2756. return rtnval;
  2757. }
  2758. return rtnval;
  2759. }
  2760. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  2761. {
  2762. struct AdapterControlBlock *acb;
  2763. uint32_t intmask_org, outbound_doorbell;
  2764. int retry_count = 0;
  2765. int rtn = FAILED;
  2766. acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
  2767. printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
  2768. acb->num_resets++;
  2769. switch(acb->adapter_type){
  2770. case ACB_ADAPTER_TYPE_A:{
  2771. if (acb->acb_flags & ACB_F_BUS_RESET){
  2772. long timeout;
  2773. printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
  2774. timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
  2775. if (timeout) {
  2776. return SUCCESS;
  2777. }
  2778. }
  2779. acb->acb_flags |= ACB_F_BUS_RESET;
  2780. if (!arcmsr_iop_reset(acb)) {
  2781. struct MessageUnit_A __iomem *reg;
  2782. reg = acb->pmuA;
  2783. arcmsr_hardware_reset(acb);
  2784. acb->acb_flags &= ~ACB_F_IOP_INITED;
  2785. sleep_again:
  2786. arcmsr_sleep_for_bus_reset(cmd);
  2787. if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
  2788. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d \n", acb->host->host_no, retry_count);
  2789. if (retry_count > retrycount) {
  2790. acb->fw_flag = FW_DEADLOCK;
  2791. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!! \n", acb->host->host_no);
  2792. return FAILED;
  2793. }
  2794. retry_count++;
  2795. goto sleep_again;
  2796. }
  2797. acb->acb_flags |= ACB_F_IOP_INITED;
  2798. /* disable all outbound interrupt */
  2799. intmask_org = arcmsr_disable_outbound_ints(acb);
  2800. arcmsr_get_firmware_spec(acb);
  2801. arcmsr_start_adapter_bgrb(acb);
  2802. /* clear Qbuffer if door bell ringed */
  2803. outbound_doorbell = readl(&reg->outbound_doorbell);
  2804. writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
  2805. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  2806. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2807. arcmsr_enable_outbound_ints(acb, intmask_org);
  2808. atomic_set(&acb->rq_map_token, 16);
  2809. atomic_set(&acb->ante_token_value, 16);
  2810. acb->fw_flag = FW_NORMAL;
  2811. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2812. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2813. rtn = SUCCESS;
  2814. printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
  2815. } else {
  2816. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2817. atomic_set(&acb->rq_map_token, 16);
  2818. atomic_set(&acb->ante_token_value, 16);
  2819. acb->fw_flag = FW_NORMAL;
  2820. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  2821. rtn = SUCCESS;
  2822. }
  2823. break;
  2824. }
  2825. case ACB_ADAPTER_TYPE_B:{
  2826. acb->acb_flags |= ACB_F_BUS_RESET;
  2827. if (!arcmsr_iop_reset(acb)) {
  2828. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2829. rtn = FAILED;
  2830. } else {
  2831. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2832. atomic_set(&acb->rq_map_token, 16);
  2833. atomic_set(&acb->ante_token_value, 16);
  2834. acb->fw_flag = FW_NORMAL;
  2835. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2836. rtn = SUCCESS;
  2837. }
  2838. break;
  2839. }
  2840. case ACB_ADAPTER_TYPE_C:{
  2841. if (acb->acb_flags & ACB_F_BUS_RESET) {
  2842. long timeout;
  2843. printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
  2844. timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
  2845. if (timeout) {
  2846. return SUCCESS;
  2847. }
  2848. }
  2849. acb->acb_flags |= ACB_F_BUS_RESET;
  2850. if (!arcmsr_iop_reset(acb)) {
  2851. struct MessageUnit_C __iomem *reg;
  2852. reg = acb->pmuC;
  2853. arcmsr_hardware_reset(acb);
  2854. acb->acb_flags &= ~ACB_F_IOP_INITED;
  2855. sleep:
  2856. arcmsr_sleep_for_bus_reset(cmd);
  2857. if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
  2858. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d \n", acb->host->host_no, retry_count);
  2859. if (retry_count > retrycount) {
  2860. acb->fw_flag = FW_DEADLOCK;
  2861. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!! \n", acb->host->host_no);
  2862. return FAILED;
  2863. }
  2864. retry_count++;
  2865. goto sleep;
  2866. }
  2867. acb->acb_flags |= ACB_F_IOP_INITED;
  2868. /* disable all outbound interrupt */
  2869. intmask_org = arcmsr_disable_outbound_ints(acb);
  2870. arcmsr_get_firmware_spec(acb);
  2871. arcmsr_start_adapter_bgrb(acb);
  2872. /* clear Qbuffer if door bell ringed */
  2873. outbound_doorbell = readl(&reg->outbound_doorbell);
  2874. writel(outbound_doorbell, &reg->outbound_doorbell_clear); /*clear interrupt */
  2875. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  2876. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2877. arcmsr_enable_outbound_ints(acb, intmask_org);
  2878. atomic_set(&acb->rq_map_token, 16);
  2879. atomic_set(&acb->ante_token_value, 16);
  2880. acb->fw_flag = FW_NORMAL;
  2881. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  2882. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2883. rtn = SUCCESS;
  2884. printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
  2885. } else {
  2886. acb->acb_flags &= ~ACB_F_BUS_RESET;
  2887. atomic_set(&acb->rq_map_token, 16);
  2888. atomic_set(&acb->ante_token_value, 16);
  2889. acb->fw_flag = FW_NORMAL;
  2890. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  2891. rtn = SUCCESS;
  2892. }
  2893. break;
  2894. }
  2895. }
  2896. return rtn;
  2897. }
  2898. static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  2899. struct CommandControlBlock *ccb)
  2900. {
  2901. int rtn;
  2902. rtn = arcmsr_polling_ccbdone(acb, ccb);
  2903. return rtn;
  2904. }
  2905. static int arcmsr_abort(struct scsi_cmnd *cmd)
  2906. {
  2907. struct AdapterControlBlock *acb =
  2908. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  2909. int i = 0;
  2910. int rtn = FAILED;
  2911. printk(KERN_NOTICE
  2912. "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
  2913. acb->host->host_no, cmd->device->id, cmd->device->lun);
  2914. acb->acb_flags |= ACB_F_ABORT;
  2915. acb->num_aborts++;
  2916. /*
  2917. ************************************************
  2918. ** the all interrupt service routine is locked
  2919. ** we need to handle it as soon as possible and exit
  2920. ************************************************
  2921. */
  2922. if (!atomic_read(&acb->ccboutstandingcount))
  2923. return rtn;
  2924. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  2925. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  2926. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  2927. ccb->startdone = ARCMSR_CCB_ABORTED;
  2928. rtn = arcmsr_abort_one_cmd(acb, ccb);
  2929. break;
  2930. }
  2931. }
  2932. acb->acb_flags &= ~ACB_F_ABORT;
  2933. return rtn;
  2934. }
  2935. static const char *arcmsr_info(struct Scsi_Host *host)
  2936. {
  2937. struct AdapterControlBlock *acb =
  2938. (struct AdapterControlBlock *) host->hostdata;
  2939. static char buf[256];
  2940. char *type;
  2941. int raid6 = 1;
  2942. switch (acb->pdev->device) {
  2943. case PCI_DEVICE_ID_ARECA_1110:
  2944. case PCI_DEVICE_ID_ARECA_1200:
  2945. case PCI_DEVICE_ID_ARECA_1202:
  2946. case PCI_DEVICE_ID_ARECA_1210:
  2947. raid6 = 0;
  2948. /*FALLTHRU*/
  2949. case PCI_DEVICE_ID_ARECA_1120:
  2950. case PCI_DEVICE_ID_ARECA_1130:
  2951. case PCI_DEVICE_ID_ARECA_1160:
  2952. case PCI_DEVICE_ID_ARECA_1170:
  2953. case PCI_DEVICE_ID_ARECA_1201:
  2954. case PCI_DEVICE_ID_ARECA_1220:
  2955. case PCI_DEVICE_ID_ARECA_1230:
  2956. case PCI_DEVICE_ID_ARECA_1260:
  2957. case PCI_DEVICE_ID_ARECA_1270:
  2958. case PCI_DEVICE_ID_ARECA_1280:
  2959. type = "SATA";
  2960. break;
  2961. case PCI_DEVICE_ID_ARECA_1380:
  2962. case PCI_DEVICE_ID_ARECA_1381:
  2963. case PCI_DEVICE_ID_ARECA_1680:
  2964. case PCI_DEVICE_ID_ARECA_1681:
  2965. case PCI_DEVICE_ID_ARECA_1880:
  2966. type = "SAS";
  2967. break;
  2968. default:
  2969. type = "X-TYPE";
  2970. break;
  2971. }
  2972. sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
  2973. type, raid6 ? "( RAID6 capable)" : "",
  2974. ARCMSR_DRIVER_VERSION);
  2975. return buf;
  2976. }