main.c 58 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  61. pending = !list_empty(&txq->txq_fifo_pending);
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. spin_unlock(&common->cc_lock);
  94. }
  95. unlock:
  96. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  97. }
  98. void ath9k_ps_restore(struct ath_softc *sc)
  99. {
  100. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  101. unsigned long flags;
  102. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  103. if (--sc->ps_usecount != 0)
  104. goto unlock;
  105. spin_lock(&common->cc_lock);
  106. ath_hw_cycle_counters_update(common);
  107. spin_unlock(&common->cc_lock);
  108. if (sc->ps_idle)
  109. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  110. else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK)))
  115. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  116. unlock:
  117. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  118. }
  119. static void ath_start_ani(struct ath_common *common)
  120. {
  121. struct ath_hw *ah = common->ah;
  122. unsigned long timestamp = jiffies_to_msecs(jiffies);
  123. struct ath_softc *sc = (struct ath_softc *) common->priv;
  124. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  125. return;
  126. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  127. return;
  128. common->ani.longcal_timer = timestamp;
  129. common->ani.shortcal_timer = timestamp;
  130. common->ani.checkani_timer = timestamp;
  131. mod_timer(&common->ani.timer,
  132. jiffies +
  133. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  134. }
  135. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  136. {
  137. struct ath_hw *ah = sc->sc_ah;
  138. struct ath9k_channel *chan = &ah->channels[channel];
  139. struct survey_info *survey = &sc->survey[channel];
  140. if (chan->noisefloor) {
  141. survey->filled |= SURVEY_INFO_NOISE_DBM;
  142. survey->noise = chan->noisefloor;
  143. }
  144. }
  145. /*
  146. * Updates the survey statistics and returns the busy time since last
  147. * update in %, if the measurement duration was long enough for the
  148. * result to be useful, -1 otherwise.
  149. */
  150. static int ath_update_survey_stats(struct ath_softc *sc)
  151. {
  152. struct ath_hw *ah = sc->sc_ah;
  153. struct ath_common *common = ath9k_hw_common(ah);
  154. int pos = ah->curchan - &ah->channels[0];
  155. struct survey_info *survey = &sc->survey[pos];
  156. struct ath_cycle_counters *cc = &common->cc_survey;
  157. unsigned int div = common->clockrate * 1000;
  158. int ret = 0;
  159. if (!ah->curchan)
  160. return -1;
  161. if (ah->power_mode == ATH9K_PM_AWAKE)
  162. ath_hw_cycle_counters_update(common);
  163. if (cc->cycles > 0) {
  164. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  165. SURVEY_INFO_CHANNEL_TIME_BUSY |
  166. SURVEY_INFO_CHANNEL_TIME_RX |
  167. SURVEY_INFO_CHANNEL_TIME_TX;
  168. survey->channel_time += cc->cycles / div;
  169. survey->channel_time_busy += cc->rx_busy / div;
  170. survey->channel_time_rx += cc->rx_frame / div;
  171. survey->channel_time_tx += cc->tx_frame / div;
  172. }
  173. if (cc->cycles < div)
  174. return -1;
  175. if (cc->cycles > 0)
  176. ret = cc->rx_busy * 100 / cc->cycles;
  177. memset(cc, 0, sizeof(*cc));
  178. ath_update_survey_nf(sc, pos);
  179. return ret;
  180. }
  181. /*
  182. * Set/change channels. If the channel is really being changed, it's done
  183. * by reseting the chip. To accomplish this we must first cleanup any pending
  184. * DMA, then restart stuff.
  185. */
  186. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  187. struct ath9k_channel *hchan)
  188. {
  189. struct ath_hw *ah = sc->sc_ah;
  190. struct ath_common *common = ath9k_hw_common(ah);
  191. struct ieee80211_conf *conf = &common->hw->conf;
  192. bool fastcc = true, stopped;
  193. struct ieee80211_channel *channel = hw->conf.channel;
  194. struct ath9k_hw_cal_data *caldata = NULL;
  195. int r;
  196. if (sc->sc_flags & SC_OP_INVALID)
  197. return -EIO;
  198. sc->hw_busy_count = 0;
  199. del_timer_sync(&common->ani.timer);
  200. cancel_work_sync(&sc->paprd_work);
  201. cancel_work_sync(&sc->hw_check_work);
  202. cancel_delayed_work_sync(&sc->tx_complete_work);
  203. cancel_delayed_work_sync(&sc->hw_pll_work);
  204. ath9k_ps_wakeup(sc);
  205. spin_lock_bh(&sc->sc_pcu_lock);
  206. /*
  207. * This is only performed if the channel settings have
  208. * actually changed.
  209. *
  210. * To switch channels clear any pending DMA operations;
  211. * wait long enough for the RX fifo to drain, reset the
  212. * hardware at the new frequency, and then re-enable
  213. * the relevant bits of the h/w.
  214. */
  215. ath9k_hw_disable_interrupts(ah);
  216. stopped = ath_drain_all_txq(sc, false);
  217. if (!ath_stoprecv(sc))
  218. stopped = false;
  219. if (!ath9k_hw_check_alive(ah))
  220. stopped = false;
  221. /* XXX: do not flush receive queue here. We don't want
  222. * to flush data frames already in queue because of
  223. * changing channel. */
  224. if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
  225. fastcc = false;
  226. if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
  227. caldata = &sc->caldata;
  228. ath_dbg(common, ATH_DBG_CONFIG,
  229. "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
  230. sc->sc_ah->curchan->channel,
  231. channel->center_freq, conf_is_ht40(conf),
  232. fastcc);
  233. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  234. if (r) {
  235. ath_err(common,
  236. "Unable to reset channel (%u MHz), reset status %d\n",
  237. channel->center_freq, r);
  238. goto ps_restore;
  239. }
  240. if (ath_startrecv(sc) != 0) {
  241. ath_err(common, "Unable to restart recv logic\n");
  242. r = -EIO;
  243. goto ps_restore;
  244. }
  245. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  246. sc->config.txpowlimit, &sc->curtxpow);
  247. ath9k_hw_set_interrupts(ah, ah->imask);
  248. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
  249. if (sc->sc_flags & SC_OP_BEACONS)
  250. ath_set_beacon(sc);
  251. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  252. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
  253. ath_start_ani(common);
  254. }
  255. ps_restore:
  256. ieee80211_wake_queues(hw);
  257. spin_unlock_bh(&sc->sc_pcu_lock);
  258. ath9k_ps_restore(sc);
  259. return r;
  260. }
  261. static void ath_paprd_activate(struct ath_softc *sc)
  262. {
  263. struct ath_hw *ah = sc->sc_ah;
  264. struct ath9k_hw_cal_data *caldata = ah->caldata;
  265. struct ath_common *common = ath9k_hw_common(ah);
  266. int chain;
  267. if (!caldata || !caldata->paprd_done)
  268. return;
  269. ath9k_ps_wakeup(sc);
  270. ar9003_paprd_enable(ah, false);
  271. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  272. if (!(common->tx_chainmask & BIT(chain)))
  273. continue;
  274. ar9003_paprd_populate_single_table(ah, caldata, chain);
  275. }
  276. ar9003_paprd_enable(ah, true);
  277. ath9k_ps_restore(sc);
  278. }
  279. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  280. {
  281. struct ieee80211_hw *hw = sc->hw;
  282. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  283. struct ath_hw *ah = sc->sc_ah;
  284. struct ath_common *common = ath9k_hw_common(ah);
  285. struct ath_tx_control txctl;
  286. int time_left;
  287. memset(&txctl, 0, sizeof(txctl));
  288. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  289. memset(tx_info, 0, sizeof(*tx_info));
  290. tx_info->band = hw->conf.channel->band;
  291. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  292. tx_info->control.rates[0].idx = 0;
  293. tx_info->control.rates[0].count = 1;
  294. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  295. tx_info->control.rates[1].idx = -1;
  296. init_completion(&sc->paprd_complete);
  297. txctl.paprd = BIT(chain);
  298. if (ath_tx_start(hw, skb, &txctl) != 0) {
  299. ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
  300. dev_kfree_skb_any(skb);
  301. return false;
  302. }
  303. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  304. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  305. if (!time_left)
  306. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
  307. "Timeout waiting for paprd training on TX chain %d\n",
  308. chain);
  309. return !!time_left;
  310. }
  311. void ath_paprd_calibrate(struct work_struct *work)
  312. {
  313. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  314. struct ieee80211_hw *hw = sc->hw;
  315. struct ath_hw *ah = sc->sc_ah;
  316. struct ieee80211_hdr *hdr;
  317. struct sk_buff *skb = NULL;
  318. struct ath9k_hw_cal_data *caldata = ah->caldata;
  319. struct ath_common *common = ath9k_hw_common(ah);
  320. int ftype;
  321. int chain_ok = 0;
  322. int chain;
  323. int len = 1800;
  324. if (!caldata)
  325. return;
  326. if (ar9003_paprd_init_table(ah) < 0)
  327. return;
  328. skb = alloc_skb(len, GFP_KERNEL);
  329. if (!skb)
  330. return;
  331. skb_put(skb, len);
  332. memset(skb->data, 0, len);
  333. hdr = (struct ieee80211_hdr *)skb->data;
  334. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  335. hdr->frame_control = cpu_to_le16(ftype);
  336. hdr->duration_id = cpu_to_le16(10);
  337. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  338. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  339. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  340. ath9k_ps_wakeup(sc);
  341. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  342. if (!(common->tx_chainmask & BIT(chain)))
  343. continue;
  344. chain_ok = 0;
  345. ath_dbg(common, ATH_DBG_CALIBRATE,
  346. "Sending PAPRD frame for thermal measurement "
  347. "on chain %d\n", chain);
  348. if (!ath_paprd_send_frame(sc, skb, chain))
  349. goto fail_paprd;
  350. ar9003_paprd_setup_gain_table(ah, chain);
  351. ath_dbg(common, ATH_DBG_CALIBRATE,
  352. "Sending PAPRD training frame on chain %d\n", chain);
  353. if (!ath_paprd_send_frame(sc, skb, chain))
  354. goto fail_paprd;
  355. if (!ar9003_paprd_is_done(ah))
  356. break;
  357. if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
  358. break;
  359. chain_ok = 1;
  360. }
  361. kfree_skb(skb);
  362. if (chain_ok) {
  363. caldata->paprd_done = true;
  364. ath_paprd_activate(sc);
  365. }
  366. fail_paprd:
  367. ath9k_ps_restore(sc);
  368. }
  369. /*
  370. * This routine performs the periodic noise floor calibration function
  371. * that is used to adjust and optimize the chip performance. This
  372. * takes environmental changes (location, temperature) into account.
  373. * When the task is complete, it reschedules itself depending on the
  374. * appropriate interval that was calculated.
  375. */
  376. void ath_ani_calibrate(unsigned long data)
  377. {
  378. struct ath_softc *sc = (struct ath_softc *)data;
  379. struct ath_hw *ah = sc->sc_ah;
  380. struct ath_common *common = ath9k_hw_common(ah);
  381. bool longcal = false;
  382. bool shortcal = false;
  383. bool aniflag = false;
  384. unsigned int timestamp = jiffies_to_msecs(jiffies);
  385. u32 cal_interval, short_cal_interval, long_cal_interval;
  386. unsigned long flags;
  387. if (ah->caldata && ah->caldata->nfcal_interference)
  388. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  389. else
  390. long_cal_interval = ATH_LONG_CALINTERVAL;
  391. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  392. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  393. /* Only calibrate if awake */
  394. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  395. goto set_timer;
  396. ath9k_ps_wakeup(sc);
  397. /* Long calibration runs independently of short calibration. */
  398. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  399. longcal = true;
  400. ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  401. common->ani.longcal_timer = timestamp;
  402. }
  403. /* Short calibration applies only while caldone is false */
  404. if (!common->ani.caldone) {
  405. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  406. shortcal = true;
  407. ath_dbg(common, ATH_DBG_ANI,
  408. "shortcal @%lu\n", jiffies);
  409. common->ani.shortcal_timer = timestamp;
  410. common->ani.resetcal_timer = timestamp;
  411. }
  412. } else {
  413. if ((timestamp - common->ani.resetcal_timer) >=
  414. ATH_RESTART_CALINTERVAL) {
  415. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  416. if (common->ani.caldone)
  417. common->ani.resetcal_timer = timestamp;
  418. }
  419. }
  420. /* Verify whether we must check ANI */
  421. if ((timestamp - common->ani.checkani_timer) >=
  422. ah->config.ani_poll_interval) {
  423. aniflag = true;
  424. common->ani.checkani_timer = timestamp;
  425. }
  426. /* Skip all processing if there's nothing to do. */
  427. if (longcal || shortcal || aniflag) {
  428. /* Call ANI routine if necessary */
  429. if (aniflag) {
  430. spin_lock_irqsave(&common->cc_lock, flags);
  431. ath9k_hw_ani_monitor(ah, ah->curchan);
  432. ath_update_survey_stats(sc);
  433. spin_unlock_irqrestore(&common->cc_lock, flags);
  434. }
  435. /* Perform calibration if necessary */
  436. if (longcal || shortcal) {
  437. common->ani.caldone =
  438. ath9k_hw_calibrate(ah,
  439. ah->curchan,
  440. common->rx_chainmask,
  441. longcal);
  442. }
  443. }
  444. ath9k_ps_restore(sc);
  445. set_timer:
  446. /*
  447. * Set timer interval based on previous results.
  448. * The interval must be the shortest necessary to satisfy ANI,
  449. * short calibration and long calibration.
  450. */
  451. cal_interval = ATH_LONG_CALINTERVAL;
  452. if (sc->sc_ah->config.enable_ani)
  453. cal_interval = min(cal_interval,
  454. (u32)ah->config.ani_poll_interval);
  455. if (!common->ani.caldone)
  456. cal_interval = min(cal_interval, (u32)short_cal_interval);
  457. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  458. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  459. if (!ah->caldata->paprd_done)
  460. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  461. else if (!ah->paprd_table_write_done)
  462. ath_paprd_activate(sc);
  463. }
  464. }
  465. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  466. {
  467. struct ath_node *an;
  468. struct ath_hw *ah = sc->sc_ah;
  469. an = (struct ath_node *)sta->drv_priv;
  470. #ifdef CONFIG_ATH9K_DEBUGFS
  471. spin_lock(&sc->nodes_lock);
  472. list_add(&an->list, &sc->nodes);
  473. spin_unlock(&sc->nodes_lock);
  474. an->sta = sta;
  475. #endif
  476. if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
  477. sc->sc_flags |= SC_OP_ENABLE_APM;
  478. if (sc->sc_flags & SC_OP_TXAGGR) {
  479. ath_tx_node_init(sc, an);
  480. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  481. sta->ht_cap.ampdu_factor);
  482. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  483. }
  484. }
  485. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  486. {
  487. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  488. #ifdef CONFIG_ATH9K_DEBUGFS
  489. spin_lock(&sc->nodes_lock);
  490. list_del(&an->list);
  491. spin_unlock(&sc->nodes_lock);
  492. an->sta = NULL;
  493. #endif
  494. if (sc->sc_flags & SC_OP_TXAGGR)
  495. ath_tx_node_cleanup(sc, an);
  496. }
  497. void ath_hw_check(struct work_struct *work)
  498. {
  499. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  500. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  501. unsigned long flags;
  502. int busy;
  503. ath9k_ps_wakeup(sc);
  504. if (ath9k_hw_check_alive(sc->sc_ah))
  505. goto out;
  506. spin_lock_irqsave(&common->cc_lock, flags);
  507. busy = ath_update_survey_stats(sc);
  508. spin_unlock_irqrestore(&common->cc_lock, flags);
  509. ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
  510. "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
  511. if (busy >= 99) {
  512. if (++sc->hw_busy_count >= 3)
  513. ath_reset(sc, true);
  514. } else if (busy >= 0)
  515. sc->hw_busy_count = 0;
  516. out:
  517. ath9k_ps_restore(sc);
  518. }
  519. static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
  520. {
  521. static int count;
  522. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  523. if (pll_sqsum >= 0x40000) {
  524. count++;
  525. if (count == 3) {
  526. /* Rx is hung for more than 500ms. Reset it */
  527. ath_dbg(common, ATH_DBG_RESET,
  528. "Possible RX hang, resetting");
  529. ath_reset(sc, true);
  530. count = 0;
  531. }
  532. } else
  533. count = 0;
  534. }
  535. void ath_hw_pll_work(struct work_struct *work)
  536. {
  537. struct ath_softc *sc = container_of(work, struct ath_softc,
  538. hw_pll_work.work);
  539. u32 pll_sqsum;
  540. if (AR_SREV_9485(sc->sc_ah)) {
  541. ath9k_ps_wakeup(sc);
  542. pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
  543. ath9k_ps_restore(sc);
  544. ath_hw_pll_rx_hang_check(sc, pll_sqsum);
  545. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
  546. }
  547. }
  548. void ath9k_tasklet(unsigned long data)
  549. {
  550. struct ath_softc *sc = (struct ath_softc *)data;
  551. struct ath_hw *ah = sc->sc_ah;
  552. struct ath_common *common = ath9k_hw_common(ah);
  553. u32 status = sc->intrstatus;
  554. u32 rxmask;
  555. if (status & ATH9K_INT_FATAL) {
  556. ath_reset(sc, true);
  557. return;
  558. }
  559. ath9k_ps_wakeup(sc);
  560. spin_lock(&sc->sc_pcu_lock);
  561. /*
  562. * Only run the baseband hang check if beacons stop working in AP or
  563. * IBSS mode, because it has a high false positive rate. For station
  564. * mode it should not be necessary, since the upper layers will detect
  565. * this through a beacon miss automatically and the following channel
  566. * change will trigger a hardware reset anyway
  567. */
  568. if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
  569. !ath9k_hw_check_alive(ah))
  570. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  571. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  572. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  573. ATH9K_INT_RXORN);
  574. else
  575. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  576. if (status & rxmask) {
  577. /* Check for high priority Rx first */
  578. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  579. (status & ATH9K_INT_RXHP))
  580. ath_rx_tasklet(sc, 0, true);
  581. ath_rx_tasklet(sc, 0, false);
  582. }
  583. if (status & ATH9K_INT_TX) {
  584. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  585. ath_tx_edma_tasklet(sc);
  586. else
  587. ath_tx_tasklet(sc);
  588. }
  589. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  590. /*
  591. * TSF sync does not look correct; remain awake to sync with
  592. * the next Beacon.
  593. */
  594. ath_dbg(common, ATH_DBG_PS,
  595. "TSFOOR - Sync with next Beacon\n");
  596. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  597. }
  598. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  599. if (status & ATH9K_INT_GENTIMER)
  600. ath_gen_timer_isr(sc->sc_ah);
  601. /* re-enable hardware interrupt */
  602. ath9k_hw_enable_interrupts(ah);
  603. spin_unlock(&sc->sc_pcu_lock);
  604. ath9k_ps_restore(sc);
  605. }
  606. irqreturn_t ath_isr(int irq, void *dev)
  607. {
  608. #define SCHED_INTR ( \
  609. ATH9K_INT_FATAL | \
  610. ATH9K_INT_RXORN | \
  611. ATH9K_INT_RXEOL | \
  612. ATH9K_INT_RX | \
  613. ATH9K_INT_RXLP | \
  614. ATH9K_INT_RXHP | \
  615. ATH9K_INT_TX | \
  616. ATH9K_INT_BMISS | \
  617. ATH9K_INT_CST | \
  618. ATH9K_INT_TSFOOR | \
  619. ATH9K_INT_GENTIMER)
  620. struct ath_softc *sc = dev;
  621. struct ath_hw *ah = sc->sc_ah;
  622. struct ath_common *common = ath9k_hw_common(ah);
  623. enum ath9k_int status;
  624. bool sched = false;
  625. /*
  626. * The hardware is not ready/present, don't
  627. * touch anything. Note this can happen early
  628. * on if the IRQ is shared.
  629. */
  630. if (sc->sc_flags & SC_OP_INVALID)
  631. return IRQ_NONE;
  632. /* shared irq, not for us */
  633. if (!ath9k_hw_intrpend(ah))
  634. return IRQ_NONE;
  635. /*
  636. * Figure out the reason(s) for the interrupt. Note
  637. * that the hal returns a pseudo-ISR that may include
  638. * bits we haven't explicitly enabled so we mask the
  639. * value to insure we only process bits we requested.
  640. */
  641. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  642. status &= ah->imask; /* discard unasked-for bits */
  643. /*
  644. * If there are no status bits set, then this interrupt was not
  645. * for me (should have been caught above).
  646. */
  647. if (!status)
  648. return IRQ_NONE;
  649. /* Cache the status */
  650. sc->intrstatus = status;
  651. if (status & SCHED_INTR)
  652. sched = true;
  653. /*
  654. * If a FATAL or RXORN interrupt is received, we have to reset the
  655. * chip immediately.
  656. */
  657. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  658. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  659. goto chip_reset;
  660. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  661. (status & ATH9K_INT_BB_WATCHDOG)) {
  662. spin_lock(&common->cc_lock);
  663. ath_hw_cycle_counters_update(common);
  664. ar9003_hw_bb_watchdog_dbg_info(ah);
  665. spin_unlock(&common->cc_lock);
  666. goto chip_reset;
  667. }
  668. if (status & ATH9K_INT_SWBA)
  669. tasklet_schedule(&sc->bcon_tasklet);
  670. if (status & ATH9K_INT_TXURN)
  671. ath9k_hw_updatetxtriglevel(ah, true);
  672. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  673. if (status & ATH9K_INT_RXEOL) {
  674. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  675. ath9k_hw_set_interrupts(ah, ah->imask);
  676. }
  677. }
  678. if (status & ATH9K_INT_MIB) {
  679. /*
  680. * Disable interrupts until we service the MIB
  681. * interrupt; otherwise it will continue to
  682. * fire.
  683. */
  684. ath9k_hw_disable_interrupts(ah);
  685. /*
  686. * Let the hal handle the event. We assume
  687. * it will clear whatever condition caused
  688. * the interrupt.
  689. */
  690. spin_lock(&common->cc_lock);
  691. ath9k_hw_proc_mib_event(ah);
  692. spin_unlock(&common->cc_lock);
  693. ath9k_hw_enable_interrupts(ah);
  694. }
  695. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  696. if (status & ATH9K_INT_TIM_TIMER) {
  697. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  698. goto chip_reset;
  699. /* Clear RxAbort bit so that we can
  700. * receive frames */
  701. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  702. ath9k_hw_setrxabort(sc->sc_ah, 0);
  703. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  704. }
  705. chip_reset:
  706. ath_debug_stat_interrupt(sc, status);
  707. if (sched) {
  708. /* turn off every interrupt */
  709. ath9k_hw_disable_interrupts(ah);
  710. tasklet_schedule(&sc->intr_tq);
  711. }
  712. return IRQ_HANDLED;
  713. #undef SCHED_INTR
  714. }
  715. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  716. {
  717. struct ath_hw *ah = sc->sc_ah;
  718. struct ath_common *common = ath9k_hw_common(ah);
  719. struct ieee80211_channel *channel = hw->conf.channel;
  720. int r;
  721. ath9k_ps_wakeup(sc);
  722. spin_lock_bh(&sc->sc_pcu_lock);
  723. ath9k_hw_configpcipowersave(ah, 0, 0);
  724. if (!ah->curchan)
  725. ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
  726. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  727. if (r) {
  728. ath_err(common,
  729. "Unable to reset channel (%u MHz), reset status %d\n",
  730. channel->center_freq, r);
  731. }
  732. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  733. sc->config.txpowlimit, &sc->curtxpow);
  734. if (ath_startrecv(sc) != 0) {
  735. ath_err(common, "Unable to restart recv logic\n");
  736. goto out;
  737. }
  738. if (sc->sc_flags & SC_OP_BEACONS)
  739. ath_set_beacon(sc); /* restart beacons */
  740. /* Re-Enable interrupts */
  741. ath9k_hw_set_interrupts(ah, ah->imask);
  742. /* Enable LED */
  743. ath9k_hw_cfg_output(ah, ah->led_pin,
  744. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  745. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  746. ieee80211_wake_queues(hw);
  747. ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
  748. out:
  749. spin_unlock_bh(&sc->sc_pcu_lock);
  750. ath9k_ps_restore(sc);
  751. }
  752. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  753. {
  754. struct ath_hw *ah = sc->sc_ah;
  755. struct ieee80211_channel *channel = hw->conf.channel;
  756. int r;
  757. ath9k_ps_wakeup(sc);
  758. cancel_delayed_work_sync(&sc->hw_pll_work);
  759. spin_lock_bh(&sc->sc_pcu_lock);
  760. ieee80211_stop_queues(hw);
  761. /*
  762. * Keep the LED on when the radio is disabled
  763. * during idle unassociated state.
  764. */
  765. if (!sc->ps_idle) {
  766. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  767. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  768. }
  769. /* Disable interrupts */
  770. ath9k_hw_disable_interrupts(ah);
  771. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  772. ath_stoprecv(sc); /* turn off frame recv */
  773. ath_flushrecv(sc); /* flush recv queue */
  774. if (!ah->curchan)
  775. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  776. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  777. if (r) {
  778. ath_err(ath9k_hw_common(sc->sc_ah),
  779. "Unable to reset channel (%u MHz), reset status %d\n",
  780. channel->center_freq, r);
  781. }
  782. ath9k_hw_phy_disable(ah);
  783. ath9k_hw_configpcipowersave(ah, 1, 1);
  784. spin_unlock_bh(&sc->sc_pcu_lock);
  785. ath9k_ps_restore(sc);
  786. }
  787. int ath_reset(struct ath_softc *sc, bool retry_tx)
  788. {
  789. struct ath_hw *ah = sc->sc_ah;
  790. struct ath_common *common = ath9k_hw_common(ah);
  791. struct ieee80211_hw *hw = sc->hw;
  792. int r;
  793. sc->hw_busy_count = 0;
  794. /* Stop ANI */
  795. del_timer_sync(&common->ani.timer);
  796. ath9k_ps_wakeup(sc);
  797. spin_lock_bh(&sc->sc_pcu_lock);
  798. ieee80211_stop_queues(hw);
  799. ath9k_hw_disable_interrupts(ah);
  800. ath_drain_all_txq(sc, retry_tx);
  801. ath_stoprecv(sc);
  802. ath_flushrecv(sc);
  803. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
  804. if (r)
  805. ath_err(common,
  806. "Unable to reset hardware; reset status %d\n", r);
  807. if (ath_startrecv(sc) != 0)
  808. ath_err(common, "Unable to start recv logic\n");
  809. /*
  810. * We may be doing a reset in response to a request
  811. * that changes the channel so update any state that
  812. * might change as a result.
  813. */
  814. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  815. sc->config.txpowlimit, &sc->curtxpow);
  816. if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
  817. ath_set_beacon(sc); /* restart beacons */
  818. ath9k_hw_set_interrupts(ah, ah->imask);
  819. if (retry_tx) {
  820. int i;
  821. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  822. if (ATH_TXQ_SETUP(sc, i)) {
  823. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  824. ath_txq_schedule(sc, &sc->tx.txq[i]);
  825. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  826. }
  827. }
  828. }
  829. ieee80211_wake_queues(hw);
  830. spin_unlock_bh(&sc->sc_pcu_lock);
  831. /* Start ANI */
  832. ath_start_ani(common);
  833. ath9k_ps_restore(sc);
  834. return r;
  835. }
  836. /**********************/
  837. /* mac80211 callbacks */
  838. /**********************/
  839. static int ath9k_start(struct ieee80211_hw *hw)
  840. {
  841. struct ath_softc *sc = hw->priv;
  842. struct ath_hw *ah = sc->sc_ah;
  843. struct ath_common *common = ath9k_hw_common(ah);
  844. struct ieee80211_channel *curchan = hw->conf.channel;
  845. struct ath9k_channel *init_channel;
  846. int r;
  847. ath_dbg(common, ATH_DBG_CONFIG,
  848. "Starting driver with initial channel: %d MHz\n",
  849. curchan->center_freq);
  850. ath9k_ps_wakeup(sc);
  851. mutex_lock(&sc->mutex);
  852. /* setup initial channel */
  853. sc->chan_idx = curchan->hw_value;
  854. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  855. /* Reset SERDES registers */
  856. ath9k_hw_configpcipowersave(ah, 0, 0);
  857. /*
  858. * The basic interface to setting the hardware in a good
  859. * state is ``reset''. On return the hardware is known to
  860. * be powered up and with interrupts disabled. This must
  861. * be followed by initialization of the appropriate bits
  862. * and then setup of the interrupt mask.
  863. */
  864. spin_lock_bh(&sc->sc_pcu_lock);
  865. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  866. if (r) {
  867. ath_err(common,
  868. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  869. r, curchan->center_freq);
  870. spin_unlock_bh(&sc->sc_pcu_lock);
  871. goto mutex_unlock;
  872. }
  873. /*
  874. * This is needed only to setup initial state
  875. * but it's best done after a reset.
  876. */
  877. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  878. sc->config.txpowlimit, &sc->curtxpow);
  879. /*
  880. * Setup the hardware after reset:
  881. * The receive engine is set going.
  882. * Frame transmit is handled entirely
  883. * in the frame output path; there's nothing to do
  884. * here except setup the interrupt mask.
  885. */
  886. if (ath_startrecv(sc) != 0) {
  887. ath_err(common, "Unable to start recv logic\n");
  888. r = -EIO;
  889. spin_unlock_bh(&sc->sc_pcu_lock);
  890. goto mutex_unlock;
  891. }
  892. spin_unlock_bh(&sc->sc_pcu_lock);
  893. /* Setup our intr mask. */
  894. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  895. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  896. ATH9K_INT_GLOBAL;
  897. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  898. ah->imask |= ATH9K_INT_RXHP |
  899. ATH9K_INT_RXLP |
  900. ATH9K_INT_BB_WATCHDOG;
  901. else
  902. ah->imask |= ATH9K_INT_RX;
  903. ah->imask |= ATH9K_INT_GTT;
  904. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  905. ah->imask |= ATH9K_INT_CST;
  906. sc->sc_flags &= ~SC_OP_INVALID;
  907. sc->sc_ah->is_monitoring = false;
  908. /* Disable BMISS interrupt when we're not associated */
  909. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  910. ath9k_hw_set_interrupts(ah, ah->imask);
  911. ieee80211_wake_queues(hw);
  912. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  913. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  914. !ah->btcoex_hw.enabled) {
  915. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  916. AR_STOMP_LOW_WLAN_WGHT);
  917. ath9k_hw_btcoex_enable(ah);
  918. if (common->bus_ops->bt_coex_prep)
  919. common->bus_ops->bt_coex_prep(common);
  920. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  921. ath9k_btcoex_timer_resume(sc);
  922. }
  923. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  924. common->bus_ops->extn_synch_en(common);
  925. mutex_unlock:
  926. mutex_unlock(&sc->mutex);
  927. ath9k_ps_restore(sc);
  928. return r;
  929. }
  930. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  931. {
  932. struct ath_softc *sc = hw->priv;
  933. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  934. struct ath_tx_control txctl;
  935. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  936. if (sc->ps_enabled) {
  937. /*
  938. * mac80211 does not set PM field for normal data frames, so we
  939. * need to update that based on the current PS mode.
  940. */
  941. if (ieee80211_is_data(hdr->frame_control) &&
  942. !ieee80211_is_nullfunc(hdr->frame_control) &&
  943. !ieee80211_has_pm(hdr->frame_control)) {
  944. ath_dbg(common, ATH_DBG_PS,
  945. "Add PM=1 for a TX frame while in PS mode\n");
  946. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  947. }
  948. }
  949. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  950. /*
  951. * We are using PS-Poll and mac80211 can request TX while in
  952. * power save mode. Need to wake up hardware for the TX to be
  953. * completed and if needed, also for RX of buffered frames.
  954. */
  955. ath9k_ps_wakeup(sc);
  956. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  957. ath9k_hw_setrxabort(sc->sc_ah, 0);
  958. if (ieee80211_is_pspoll(hdr->frame_control)) {
  959. ath_dbg(common, ATH_DBG_PS,
  960. "Sending PS-Poll to pick a buffered frame\n");
  961. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  962. } else {
  963. ath_dbg(common, ATH_DBG_PS,
  964. "Wake up to complete TX\n");
  965. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  966. }
  967. /*
  968. * The actual restore operation will happen only after
  969. * the sc_flags bit is cleared. We are just dropping
  970. * the ps_usecount here.
  971. */
  972. ath9k_ps_restore(sc);
  973. }
  974. memset(&txctl, 0, sizeof(struct ath_tx_control));
  975. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  976. ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  977. if (ath_tx_start(hw, skb, &txctl) != 0) {
  978. ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
  979. goto exit;
  980. }
  981. return;
  982. exit:
  983. dev_kfree_skb_any(skb);
  984. }
  985. static void ath9k_stop(struct ieee80211_hw *hw)
  986. {
  987. struct ath_softc *sc = hw->priv;
  988. struct ath_hw *ah = sc->sc_ah;
  989. struct ath_common *common = ath9k_hw_common(ah);
  990. mutex_lock(&sc->mutex);
  991. cancel_delayed_work_sync(&sc->tx_complete_work);
  992. cancel_delayed_work_sync(&sc->hw_pll_work);
  993. cancel_work_sync(&sc->paprd_work);
  994. cancel_work_sync(&sc->hw_check_work);
  995. if (sc->sc_flags & SC_OP_INVALID) {
  996. ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
  997. mutex_unlock(&sc->mutex);
  998. return;
  999. }
  1000. /* Ensure HW is awake when we try to shut it down. */
  1001. ath9k_ps_wakeup(sc);
  1002. if (ah->btcoex_hw.enabled) {
  1003. ath9k_hw_btcoex_disable(ah);
  1004. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1005. ath9k_btcoex_timer_pause(sc);
  1006. }
  1007. spin_lock_bh(&sc->sc_pcu_lock);
  1008. /* prevent tasklets to enable interrupts once we disable them */
  1009. ah->imask &= ~ATH9K_INT_GLOBAL;
  1010. /* make sure h/w will not generate any interrupt
  1011. * before setting the invalid flag. */
  1012. ath9k_hw_disable_interrupts(ah);
  1013. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1014. ath_drain_all_txq(sc, false);
  1015. ath_stoprecv(sc);
  1016. ath9k_hw_phy_disable(ah);
  1017. } else
  1018. sc->rx.rxlink = NULL;
  1019. if (sc->rx.frag) {
  1020. dev_kfree_skb_any(sc->rx.frag);
  1021. sc->rx.frag = NULL;
  1022. }
  1023. /* disable HAL and put h/w to sleep */
  1024. ath9k_hw_disable(ah);
  1025. ath9k_hw_configpcipowersave(ah, 1, 1);
  1026. spin_unlock_bh(&sc->sc_pcu_lock);
  1027. /* we can now sync irq and kill any running tasklets, since we already
  1028. * disabled interrupts and not holding a spin lock */
  1029. synchronize_irq(sc->irq);
  1030. tasklet_kill(&sc->intr_tq);
  1031. tasklet_kill(&sc->bcon_tasklet);
  1032. ath9k_ps_restore(sc);
  1033. sc->ps_idle = true;
  1034. ath_radio_disable(sc, hw);
  1035. sc->sc_flags |= SC_OP_INVALID;
  1036. mutex_unlock(&sc->mutex);
  1037. ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
  1038. }
  1039. bool ath9k_uses_beacons(int type)
  1040. {
  1041. switch (type) {
  1042. case NL80211_IFTYPE_AP:
  1043. case NL80211_IFTYPE_ADHOC:
  1044. case NL80211_IFTYPE_MESH_POINT:
  1045. return true;
  1046. default:
  1047. return false;
  1048. }
  1049. }
  1050. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1051. struct ieee80211_vif *vif)
  1052. {
  1053. struct ath_vif *avp = (void *)vif->drv_priv;
  1054. ath9k_set_beaconing_status(sc, false);
  1055. ath_beacon_return(sc, avp);
  1056. ath9k_set_beaconing_status(sc, true);
  1057. sc->sc_flags &= ~SC_OP_BEACONS;
  1058. }
  1059. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1060. {
  1061. struct ath9k_vif_iter_data *iter_data = data;
  1062. int i;
  1063. if (iter_data->hw_macaddr)
  1064. for (i = 0; i < ETH_ALEN; i++)
  1065. iter_data->mask[i] &=
  1066. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1067. switch (vif->type) {
  1068. case NL80211_IFTYPE_AP:
  1069. iter_data->naps++;
  1070. break;
  1071. case NL80211_IFTYPE_STATION:
  1072. iter_data->nstations++;
  1073. break;
  1074. case NL80211_IFTYPE_ADHOC:
  1075. iter_data->nadhocs++;
  1076. break;
  1077. case NL80211_IFTYPE_MESH_POINT:
  1078. iter_data->nmeshes++;
  1079. break;
  1080. case NL80211_IFTYPE_WDS:
  1081. iter_data->nwds++;
  1082. break;
  1083. default:
  1084. iter_data->nothers++;
  1085. break;
  1086. }
  1087. }
  1088. /* Called with sc->mutex held. */
  1089. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1090. struct ieee80211_vif *vif,
  1091. struct ath9k_vif_iter_data *iter_data)
  1092. {
  1093. struct ath_softc *sc = hw->priv;
  1094. struct ath_hw *ah = sc->sc_ah;
  1095. struct ath_common *common = ath9k_hw_common(ah);
  1096. /*
  1097. * Use the hardware MAC address as reference, the hardware uses it
  1098. * together with the BSSID mask when matching addresses.
  1099. */
  1100. memset(iter_data, 0, sizeof(*iter_data));
  1101. iter_data->hw_macaddr = common->macaddr;
  1102. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1103. if (vif)
  1104. ath9k_vif_iter(iter_data, vif->addr, vif);
  1105. /* Get list of all active MAC addresses */
  1106. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1107. iter_data);
  1108. }
  1109. /* Called with sc->mutex held. */
  1110. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1111. struct ieee80211_vif *vif)
  1112. {
  1113. struct ath_softc *sc = hw->priv;
  1114. struct ath_hw *ah = sc->sc_ah;
  1115. struct ath_common *common = ath9k_hw_common(ah);
  1116. struct ath9k_vif_iter_data iter_data;
  1117. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1118. /* Set BSSID mask. */
  1119. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1120. ath_hw_setbssidmask(common);
  1121. /* Set op-mode & TSF */
  1122. if (iter_data.naps > 0) {
  1123. ath9k_hw_set_tsfadjust(ah, 1);
  1124. sc->sc_flags |= SC_OP_TSF_RESET;
  1125. ah->opmode = NL80211_IFTYPE_AP;
  1126. } else {
  1127. ath9k_hw_set_tsfadjust(ah, 0);
  1128. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1129. if (iter_data.nwds + iter_data.nmeshes)
  1130. ah->opmode = NL80211_IFTYPE_AP;
  1131. else if (iter_data.nadhocs)
  1132. ah->opmode = NL80211_IFTYPE_ADHOC;
  1133. else
  1134. ah->opmode = NL80211_IFTYPE_STATION;
  1135. }
  1136. /*
  1137. * Enable MIB interrupts when there are hardware phy counters.
  1138. */
  1139. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1140. if (ah->config.enable_ani)
  1141. ah->imask |= ATH9K_INT_MIB;
  1142. ah->imask |= ATH9K_INT_TSFOOR;
  1143. } else {
  1144. ah->imask &= ~ATH9K_INT_MIB;
  1145. ah->imask &= ~ATH9K_INT_TSFOOR;
  1146. }
  1147. ath9k_hw_set_interrupts(ah, ah->imask);
  1148. /* Set up ANI */
  1149. if ((iter_data.naps + iter_data.nadhocs) > 0) {
  1150. sc->sc_flags |= SC_OP_ANI_RUN;
  1151. ath_start_ani(common);
  1152. } else {
  1153. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1154. del_timer_sync(&common->ani.timer);
  1155. }
  1156. }
  1157. /* Called with sc->mutex held, vif counts set up properly. */
  1158. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1159. struct ieee80211_vif *vif)
  1160. {
  1161. struct ath_softc *sc = hw->priv;
  1162. ath9k_calculate_summary_state(hw, vif);
  1163. if (ath9k_uses_beacons(vif->type)) {
  1164. int error;
  1165. /* This may fail because upper levels do not have beacons
  1166. * properly configured yet. That's OK, we assume it
  1167. * will be properly configured and then we will be notified
  1168. * in the info_changed method and set up beacons properly
  1169. * there.
  1170. */
  1171. ath9k_set_beaconing_status(sc, false);
  1172. error = ath_beacon_alloc(sc, vif);
  1173. if (!error)
  1174. ath_beacon_config(sc, vif);
  1175. ath9k_set_beaconing_status(sc, true);
  1176. }
  1177. }
  1178. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1179. struct ieee80211_vif *vif)
  1180. {
  1181. struct ath_softc *sc = hw->priv;
  1182. struct ath_hw *ah = sc->sc_ah;
  1183. struct ath_common *common = ath9k_hw_common(ah);
  1184. int ret = 0;
  1185. ath9k_ps_wakeup(sc);
  1186. mutex_lock(&sc->mutex);
  1187. switch (vif->type) {
  1188. case NL80211_IFTYPE_STATION:
  1189. case NL80211_IFTYPE_WDS:
  1190. case NL80211_IFTYPE_ADHOC:
  1191. case NL80211_IFTYPE_AP:
  1192. case NL80211_IFTYPE_MESH_POINT:
  1193. break;
  1194. default:
  1195. ath_err(common, "Interface type %d not yet supported\n",
  1196. vif->type);
  1197. ret = -EOPNOTSUPP;
  1198. goto out;
  1199. }
  1200. if (ath9k_uses_beacons(vif->type)) {
  1201. if (sc->nbcnvifs >= ATH_BCBUF) {
  1202. ath_err(common, "Not enough beacon buffers when adding"
  1203. " new interface of type: %i\n",
  1204. vif->type);
  1205. ret = -ENOBUFS;
  1206. goto out;
  1207. }
  1208. }
  1209. if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1210. ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1211. sc->nvifs > 0)) {
  1212. ath_err(common, "Cannot create ADHOC interface when other"
  1213. " interfaces already exist.\n");
  1214. ret = -EINVAL;
  1215. goto out;
  1216. }
  1217. ath_dbg(common, ATH_DBG_CONFIG,
  1218. "Attach a VIF of type: %d\n", vif->type);
  1219. sc->nvifs++;
  1220. ath9k_do_vif_add_setup(hw, vif);
  1221. out:
  1222. mutex_unlock(&sc->mutex);
  1223. ath9k_ps_restore(sc);
  1224. return ret;
  1225. }
  1226. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1227. struct ieee80211_vif *vif,
  1228. enum nl80211_iftype new_type,
  1229. bool p2p)
  1230. {
  1231. struct ath_softc *sc = hw->priv;
  1232. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1233. int ret = 0;
  1234. ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
  1235. mutex_lock(&sc->mutex);
  1236. ath9k_ps_wakeup(sc);
  1237. /* See if new interface type is valid. */
  1238. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1239. (sc->nvifs > 1)) {
  1240. ath_err(common, "When using ADHOC, it must be the only"
  1241. " interface.\n");
  1242. ret = -EINVAL;
  1243. goto out;
  1244. }
  1245. if (ath9k_uses_beacons(new_type) &&
  1246. !ath9k_uses_beacons(vif->type)) {
  1247. if (sc->nbcnvifs >= ATH_BCBUF) {
  1248. ath_err(common, "No beacon slot available\n");
  1249. ret = -ENOBUFS;
  1250. goto out;
  1251. }
  1252. }
  1253. /* Clean up old vif stuff */
  1254. if (ath9k_uses_beacons(vif->type))
  1255. ath9k_reclaim_beacon(sc, vif);
  1256. /* Add new settings */
  1257. vif->type = new_type;
  1258. vif->p2p = p2p;
  1259. ath9k_do_vif_add_setup(hw, vif);
  1260. out:
  1261. ath9k_ps_restore(sc);
  1262. mutex_unlock(&sc->mutex);
  1263. return ret;
  1264. }
  1265. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1266. struct ieee80211_vif *vif)
  1267. {
  1268. struct ath_softc *sc = hw->priv;
  1269. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1270. ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1271. ath9k_ps_wakeup(sc);
  1272. mutex_lock(&sc->mutex);
  1273. sc->nvifs--;
  1274. /* Reclaim beacon resources */
  1275. if (ath9k_uses_beacons(vif->type))
  1276. ath9k_reclaim_beacon(sc, vif);
  1277. ath9k_calculate_summary_state(hw, NULL);
  1278. mutex_unlock(&sc->mutex);
  1279. ath9k_ps_restore(sc);
  1280. }
  1281. static void ath9k_enable_ps(struct ath_softc *sc)
  1282. {
  1283. struct ath_hw *ah = sc->sc_ah;
  1284. sc->ps_enabled = true;
  1285. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1286. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1287. ah->imask |= ATH9K_INT_TIM_TIMER;
  1288. ath9k_hw_set_interrupts(ah, ah->imask);
  1289. }
  1290. ath9k_hw_setrxabort(ah, 1);
  1291. }
  1292. }
  1293. static void ath9k_disable_ps(struct ath_softc *sc)
  1294. {
  1295. struct ath_hw *ah = sc->sc_ah;
  1296. sc->ps_enabled = false;
  1297. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1298. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1299. ath9k_hw_setrxabort(ah, 0);
  1300. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1301. PS_WAIT_FOR_CAB |
  1302. PS_WAIT_FOR_PSPOLL_DATA |
  1303. PS_WAIT_FOR_TX_ACK);
  1304. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1305. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1306. ath9k_hw_set_interrupts(ah, ah->imask);
  1307. }
  1308. }
  1309. }
  1310. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1311. {
  1312. struct ath_softc *sc = hw->priv;
  1313. struct ath_hw *ah = sc->sc_ah;
  1314. struct ath_common *common = ath9k_hw_common(ah);
  1315. struct ieee80211_conf *conf = &hw->conf;
  1316. bool disable_radio = false;
  1317. mutex_lock(&sc->mutex);
  1318. /*
  1319. * Leave this as the first check because we need to turn on the
  1320. * radio if it was disabled before prior to processing the rest
  1321. * of the changes. Likewise we must only disable the radio towards
  1322. * the end.
  1323. */
  1324. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1325. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1326. if (!sc->ps_idle) {
  1327. ath_radio_enable(sc, hw);
  1328. ath_dbg(common, ATH_DBG_CONFIG,
  1329. "not-idle: enabling radio\n");
  1330. } else {
  1331. disable_radio = true;
  1332. }
  1333. }
  1334. /*
  1335. * We just prepare to enable PS. We have to wait until our AP has
  1336. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1337. * those ACKs and end up retransmitting the same null data frames.
  1338. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1339. */
  1340. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1341. unsigned long flags;
  1342. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1343. if (conf->flags & IEEE80211_CONF_PS)
  1344. ath9k_enable_ps(sc);
  1345. else
  1346. ath9k_disable_ps(sc);
  1347. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1348. }
  1349. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1350. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1351. ath_dbg(common, ATH_DBG_CONFIG,
  1352. "Monitor mode is enabled\n");
  1353. sc->sc_ah->is_monitoring = true;
  1354. } else {
  1355. ath_dbg(common, ATH_DBG_CONFIG,
  1356. "Monitor mode is disabled\n");
  1357. sc->sc_ah->is_monitoring = false;
  1358. }
  1359. }
  1360. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1361. struct ieee80211_channel *curchan = hw->conf.channel;
  1362. int pos = curchan->hw_value;
  1363. int old_pos = -1;
  1364. unsigned long flags;
  1365. if (ah->curchan)
  1366. old_pos = ah->curchan - &ah->channels[0];
  1367. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1368. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1369. else
  1370. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1371. ath_dbg(common, ATH_DBG_CONFIG,
  1372. "Set channel: %d MHz type: %d\n",
  1373. curchan->center_freq, conf->channel_type);
  1374. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1375. curchan, conf->channel_type);
  1376. /* update survey stats for the old channel before switching */
  1377. spin_lock_irqsave(&common->cc_lock, flags);
  1378. ath_update_survey_stats(sc);
  1379. spin_unlock_irqrestore(&common->cc_lock, flags);
  1380. /*
  1381. * If the operating channel changes, change the survey in-use flags
  1382. * along with it.
  1383. * Reset the survey data for the new channel, unless we're switching
  1384. * back to the operating channel from an off-channel operation.
  1385. */
  1386. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1387. sc->cur_survey != &sc->survey[pos]) {
  1388. if (sc->cur_survey)
  1389. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1390. sc->cur_survey = &sc->survey[pos];
  1391. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1392. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1393. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1394. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1395. }
  1396. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1397. ath_err(common, "Unable to set channel\n");
  1398. mutex_unlock(&sc->mutex);
  1399. return -EINVAL;
  1400. }
  1401. /*
  1402. * The most recent snapshot of channel->noisefloor for the old
  1403. * channel is only available after the hardware reset. Copy it to
  1404. * the survey stats now.
  1405. */
  1406. if (old_pos >= 0)
  1407. ath_update_survey_nf(sc, old_pos);
  1408. }
  1409. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1410. ath_dbg(common, ATH_DBG_CONFIG,
  1411. "Set power: %d\n", conf->power_level);
  1412. sc->config.txpowlimit = 2 * conf->power_level;
  1413. ath9k_ps_wakeup(sc);
  1414. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1415. sc->config.txpowlimit, &sc->curtxpow);
  1416. ath9k_ps_restore(sc);
  1417. }
  1418. if (disable_radio) {
  1419. ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1420. ath_radio_disable(sc, hw);
  1421. }
  1422. mutex_unlock(&sc->mutex);
  1423. return 0;
  1424. }
  1425. #define SUPPORTED_FILTERS \
  1426. (FIF_PROMISC_IN_BSS | \
  1427. FIF_ALLMULTI | \
  1428. FIF_CONTROL | \
  1429. FIF_PSPOLL | \
  1430. FIF_OTHER_BSS | \
  1431. FIF_BCN_PRBRESP_PROMISC | \
  1432. FIF_PROBE_REQ | \
  1433. FIF_FCSFAIL)
  1434. /* FIXME: sc->sc_full_reset ? */
  1435. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1436. unsigned int changed_flags,
  1437. unsigned int *total_flags,
  1438. u64 multicast)
  1439. {
  1440. struct ath_softc *sc = hw->priv;
  1441. u32 rfilt;
  1442. changed_flags &= SUPPORTED_FILTERS;
  1443. *total_flags &= SUPPORTED_FILTERS;
  1444. sc->rx.rxfilter = *total_flags;
  1445. ath9k_ps_wakeup(sc);
  1446. rfilt = ath_calcrxfilter(sc);
  1447. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1448. ath9k_ps_restore(sc);
  1449. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1450. "Set HW RX filter: 0x%x\n", rfilt);
  1451. }
  1452. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1453. struct ieee80211_vif *vif,
  1454. struct ieee80211_sta *sta)
  1455. {
  1456. struct ath_softc *sc = hw->priv;
  1457. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1458. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1459. struct ieee80211_key_conf ps_key = { };
  1460. ath_node_attach(sc, sta);
  1461. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1462. return 0;
  1463. }
  1464. static void ath9k_del_ps_key(struct ath_softc *sc,
  1465. struct ieee80211_vif *vif,
  1466. struct ieee80211_sta *sta)
  1467. {
  1468. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1469. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1470. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1471. if (!an->ps_key)
  1472. return;
  1473. ath_key_delete(common, &ps_key);
  1474. }
  1475. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1476. struct ieee80211_vif *vif,
  1477. struct ieee80211_sta *sta)
  1478. {
  1479. struct ath_softc *sc = hw->priv;
  1480. ath9k_del_ps_key(sc, vif, sta);
  1481. ath_node_detach(sc, sta);
  1482. return 0;
  1483. }
  1484. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1485. struct ieee80211_vif *vif,
  1486. enum sta_notify_cmd cmd,
  1487. struct ieee80211_sta *sta)
  1488. {
  1489. struct ath_softc *sc = hw->priv;
  1490. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1491. switch (cmd) {
  1492. case STA_NOTIFY_SLEEP:
  1493. an->sleeping = true;
  1494. if (ath_tx_aggr_sleep(sc, an))
  1495. ieee80211_sta_set_tim(sta);
  1496. break;
  1497. case STA_NOTIFY_AWAKE:
  1498. an->sleeping = false;
  1499. ath_tx_aggr_wakeup(sc, an);
  1500. break;
  1501. }
  1502. }
  1503. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1504. const struct ieee80211_tx_queue_params *params)
  1505. {
  1506. struct ath_softc *sc = hw->priv;
  1507. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1508. struct ath_txq *txq;
  1509. struct ath9k_tx_queue_info qi;
  1510. int ret = 0;
  1511. if (queue >= WME_NUM_AC)
  1512. return 0;
  1513. txq = sc->tx.txq_map[queue];
  1514. ath9k_ps_wakeup(sc);
  1515. mutex_lock(&sc->mutex);
  1516. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1517. qi.tqi_aifs = params->aifs;
  1518. qi.tqi_cwmin = params->cw_min;
  1519. qi.tqi_cwmax = params->cw_max;
  1520. qi.tqi_burstTime = params->txop;
  1521. ath_dbg(common, ATH_DBG_CONFIG,
  1522. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1523. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1524. params->cw_max, params->txop);
  1525. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1526. if (ret)
  1527. ath_err(common, "TXQ Update failed\n");
  1528. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1529. if (queue == WME_AC_BE && !ret)
  1530. ath_beaconq_config(sc);
  1531. mutex_unlock(&sc->mutex);
  1532. ath9k_ps_restore(sc);
  1533. return ret;
  1534. }
  1535. static int ath9k_set_key(struct ieee80211_hw *hw,
  1536. enum set_key_cmd cmd,
  1537. struct ieee80211_vif *vif,
  1538. struct ieee80211_sta *sta,
  1539. struct ieee80211_key_conf *key)
  1540. {
  1541. struct ath_softc *sc = hw->priv;
  1542. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1543. int ret = 0;
  1544. if (ath9k_modparam_nohwcrypt)
  1545. return -ENOSPC;
  1546. if (vif->type == NL80211_IFTYPE_ADHOC &&
  1547. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1548. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1549. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1550. /*
  1551. * For now, disable hw crypto for the RSN IBSS group keys. This
  1552. * could be optimized in the future to use a modified key cache
  1553. * design to support per-STA RX GTK, but until that gets
  1554. * implemented, use of software crypto for group addressed
  1555. * frames is a acceptable to allow RSN IBSS to be used.
  1556. */
  1557. return -EOPNOTSUPP;
  1558. }
  1559. mutex_lock(&sc->mutex);
  1560. ath9k_ps_wakeup(sc);
  1561. ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1562. switch (cmd) {
  1563. case SET_KEY:
  1564. if (sta)
  1565. ath9k_del_ps_key(sc, vif, sta);
  1566. ret = ath_key_config(common, vif, sta, key);
  1567. if (ret >= 0) {
  1568. key->hw_key_idx = ret;
  1569. /* push IV and Michael MIC generation to stack */
  1570. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1571. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1572. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1573. if (sc->sc_ah->sw_mgmt_crypto &&
  1574. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1575. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1576. ret = 0;
  1577. }
  1578. break;
  1579. case DISABLE_KEY:
  1580. ath_key_delete(common, key);
  1581. break;
  1582. default:
  1583. ret = -EINVAL;
  1584. }
  1585. ath9k_ps_restore(sc);
  1586. mutex_unlock(&sc->mutex);
  1587. return ret;
  1588. }
  1589. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1590. {
  1591. struct ath_softc *sc = data;
  1592. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1593. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1594. struct ath_vif *avp = (void *)vif->drv_priv;
  1595. switch (sc->sc_ah->opmode) {
  1596. case NL80211_IFTYPE_ADHOC:
  1597. /* There can be only one vif available */
  1598. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1599. common->curaid = bss_conf->aid;
  1600. ath9k_hw_write_associd(sc->sc_ah);
  1601. /* configure beacon */
  1602. if (bss_conf->enable_beacon)
  1603. ath_beacon_config(sc, vif);
  1604. break;
  1605. case NL80211_IFTYPE_STATION:
  1606. /*
  1607. * Skip iteration if primary station vif's bss info
  1608. * was not changed
  1609. */
  1610. if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
  1611. break;
  1612. if (bss_conf->assoc) {
  1613. sc->sc_flags |= SC_OP_PRIM_STA_VIF;
  1614. avp->primary_sta_vif = true;
  1615. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1616. common->curaid = bss_conf->aid;
  1617. ath9k_hw_write_associd(sc->sc_ah);
  1618. ath_dbg(common, ATH_DBG_CONFIG,
  1619. "Bss Info ASSOC %d, bssid: %pM\n",
  1620. bss_conf->aid, common->curbssid);
  1621. ath_beacon_config(sc, vif);
  1622. /*
  1623. * Request a re-configuration of Beacon related timers
  1624. * on the receipt of the first Beacon frame (i.e.,
  1625. * after time sync with the AP).
  1626. */
  1627. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1628. /* Reset rssi stats */
  1629. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1630. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1631. sc->sc_flags |= SC_OP_ANI_RUN;
  1632. ath_start_ani(common);
  1633. }
  1634. break;
  1635. default:
  1636. break;
  1637. }
  1638. }
  1639. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1640. {
  1641. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1642. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1643. struct ath_vif *avp = (void *)vif->drv_priv;
  1644. /* Reconfigure bss info */
  1645. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1646. ath_dbg(common, ATH_DBG_CONFIG,
  1647. "Bss Info DISASSOC %d, bssid %pM\n",
  1648. common->curaid, common->curbssid);
  1649. sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
  1650. avp->primary_sta_vif = false;
  1651. memset(common->curbssid, 0, ETH_ALEN);
  1652. common->curaid = 0;
  1653. }
  1654. ieee80211_iterate_active_interfaces_atomic(
  1655. sc->hw, ath9k_bss_iter, sc);
  1656. /*
  1657. * None of station vifs are associated.
  1658. * Clear bssid & aid
  1659. */
  1660. if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
  1661. !(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
  1662. ath9k_hw_write_associd(sc->sc_ah);
  1663. /* Stop ANI */
  1664. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1665. del_timer_sync(&common->ani.timer);
  1666. }
  1667. }
  1668. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1669. struct ieee80211_vif *vif,
  1670. struct ieee80211_bss_conf *bss_conf,
  1671. u32 changed)
  1672. {
  1673. struct ath_softc *sc = hw->priv;
  1674. struct ath_hw *ah = sc->sc_ah;
  1675. struct ath_common *common = ath9k_hw_common(ah);
  1676. struct ath_vif *avp = (void *)vif->drv_priv;
  1677. int slottime;
  1678. int error;
  1679. ath9k_ps_wakeup(sc);
  1680. mutex_lock(&sc->mutex);
  1681. if (changed & BSS_CHANGED_BSSID) {
  1682. ath9k_config_bss(sc, vif);
  1683. /* Set aggregation protection mode parameters */
  1684. sc->config.ath_aggr_prot = 0;
  1685. ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
  1686. common->curbssid, common->curaid);
  1687. }
  1688. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1689. if ((changed & BSS_CHANGED_BEACON) ||
  1690. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1691. ath9k_set_beaconing_status(sc, false);
  1692. error = ath_beacon_alloc(sc, vif);
  1693. if (!error)
  1694. ath_beacon_config(sc, vif);
  1695. ath9k_set_beaconing_status(sc, true);
  1696. }
  1697. if (changed & BSS_CHANGED_ERP_SLOT) {
  1698. if (bss_conf->use_short_slot)
  1699. slottime = 9;
  1700. else
  1701. slottime = 20;
  1702. if (vif->type == NL80211_IFTYPE_AP) {
  1703. /*
  1704. * Defer update, so that connected stations can adjust
  1705. * their settings at the same time.
  1706. * See beacon.c for more details
  1707. */
  1708. sc->beacon.slottime = slottime;
  1709. sc->beacon.updateslot = UPDATE;
  1710. } else {
  1711. ah->slottime = slottime;
  1712. ath9k_hw_init_global_settings(ah);
  1713. }
  1714. }
  1715. /* Disable transmission of beacons */
  1716. if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
  1717. !bss_conf->enable_beacon) {
  1718. ath9k_set_beaconing_status(sc, false);
  1719. avp->is_bslot_active = false;
  1720. ath9k_set_beaconing_status(sc, true);
  1721. }
  1722. if (changed & BSS_CHANGED_BEACON_INT) {
  1723. /*
  1724. * In case of AP mode, the HW TSF has to be reset
  1725. * when the beacon interval changes.
  1726. */
  1727. if (vif->type == NL80211_IFTYPE_AP) {
  1728. sc->sc_flags |= SC_OP_TSF_RESET;
  1729. ath9k_set_beaconing_status(sc, false);
  1730. error = ath_beacon_alloc(sc, vif);
  1731. if (!error)
  1732. ath_beacon_config(sc, vif);
  1733. ath9k_set_beaconing_status(sc, true);
  1734. } else
  1735. ath_beacon_config(sc, vif);
  1736. }
  1737. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1738. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1739. bss_conf->use_short_preamble);
  1740. if (bss_conf->use_short_preamble)
  1741. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1742. else
  1743. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1744. }
  1745. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1746. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1747. bss_conf->use_cts_prot);
  1748. if (bss_conf->use_cts_prot &&
  1749. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1750. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1751. else
  1752. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1753. }
  1754. mutex_unlock(&sc->mutex);
  1755. ath9k_ps_restore(sc);
  1756. }
  1757. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1758. {
  1759. struct ath_softc *sc = hw->priv;
  1760. u64 tsf;
  1761. mutex_lock(&sc->mutex);
  1762. ath9k_ps_wakeup(sc);
  1763. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1764. ath9k_ps_restore(sc);
  1765. mutex_unlock(&sc->mutex);
  1766. return tsf;
  1767. }
  1768. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1769. {
  1770. struct ath_softc *sc = hw->priv;
  1771. mutex_lock(&sc->mutex);
  1772. ath9k_ps_wakeup(sc);
  1773. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1774. ath9k_ps_restore(sc);
  1775. mutex_unlock(&sc->mutex);
  1776. }
  1777. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1778. {
  1779. struct ath_softc *sc = hw->priv;
  1780. mutex_lock(&sc->mutex);
  1781. ath9k_ps_wakeup(sc);
  1782. ath9k_hw_reset_tsf(sc->sc_ah);
  1783. ath9k_ps_restore(sc);
  1784. mutex_unlock(&sc->mutex);
  1785. }
  1786. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1787. struct ieee80211_vif *vif,
  1788. enum ieee80211_ampdu_mlme_action action,
  1789. struct ieee80211_sta *sta,
  1790. u16 tid, u16 *ssn, u8 buf_size)
  1791. {
  1792. struct ath_softc *sc = hw->priv;
  1793. int ret = 0;
  1794. local_bh_disable();
  1795. switch (action) {
  1796. case IEEE80211_AMPDU_RX_START:
  1797. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1798. ret = -ENOTSUPP;
  1799. break;
  1800. case IEEE80211_AMPDU_RX_STOP:
  1801. break;
  1802. case IEEE80211_AMPDU_TX_START:
  1803. if (!(sc->sc_flags & SC_OP_TXAGGR))
  1804. return -EOPNOTSUPP;
  1805. ath9k_ps_wakeup(sc);
  1806. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1807. if (!ret)
  1808. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1809. ath9k_ps_restore(sc);
  1810. break;
  1811. case IEEE80211_AMPDU_TX_STOP:
  1812. ath9k_ps_wakeup(sc);
  1813. ath_tx_aggr_stop(sc, sta, tid);
  1814. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1815. ath9k_ps_restore(sc);
  1816. break;
  1817. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1818. ath9k_ps_wakeup(sc);
  1819. ath_tx_aggr_resume(sc, sta, tid);
  1820. ath9k_ps_restore(sc);
  1821. break;
  1822. default:
  1823. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1824. }
  1825. local_bh_enable();
  1826. return ret;
  1827. }
  1828. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1829. struct survey_info *survey)
  1830. {
  1831. struct ath_softc *sc = hw->priv;
  1832. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1833. struct ieee80211_supported_band *sband;
  1834. struct ieee80211_channel *chan;
  1835. unsigned long flags;
  1836. int pos;
  1837. spin_lock_irqsave(&common->cc_lock, flags);
  1838. if (idx == 0)
  1839. ath_update_survey_stats(sc);
  1840. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1841. if (sband && idx >= sband->n_channels) {
  1842. idx -= sband->n_channels;
  1843. sband = NULL;
  1844. }
  1845. if (!sband)
  1846. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1847. if (!sband || idx >= sband->n_channels) {
  1848. spin_unlock_irqrestore(&common->cc_lock, flags);
  1849. return -ENOENT;
  1850. }
  1851. chan = &sband->channels[idx];
  1852. pos = chan->hw_value;
  1853. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1854. survey->channel = chan;
  1855. spin_unlock_irqrestore(&common->cc_lock, flags);
  1856. return 0;
  1857. }
  1858. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1859. {
  1860. struct ath_softc *sc = hw->priv;
  1861. struct ath_hw *ah = sc->sc_ah;
  1862. mutex_lock(&sc->mutex);
  1863. ah->coverage_class = coverage_class;
  1864. ath9k_hw_init_global_settings(ah);
  1865. mutex_unlock(&sc->mutex);
  1866. }
  1867. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1868. {
  1869. struct ath_softc *sc = hw->priv;
  1870. int timeout = 200; /* ms */
  1871. int i, j;
  1872. mutex_lock(&sc->mutex);
  1873. cancel_delayed_work_sync(&sc->tx_complete_work);
  1874. if (drop)
  1875. timeout = 1;
  1876. for (j = 0; j < timeout; j++) {
  1877. int npend = 0;
  1878. if (j)
  1879. usleep_range(1000, 2000);
  1880. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1881. if (!ATH_TXQ_SETUP(sc, i))
  1882. continue;
  1883. npend += ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1884. }
  1885. if (!npend)
  1886. goto out;
  1887. }
  1888. ath9k_ps_wakeup(sc);
  1889. if (!ath_drain_all_txq(sc, false))
  1890. ath_reset(sc, false);
  1891. ath9k_ps_restore(sc);
  1892. ieee80211_wake_queues(hw);
  1893. out:
  1894. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1895. mutex_unlock(&sc->mutex);
  1896. }
  1897. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1898. {
  1899. struct ath_softc *sc = hw->priv;
  1900. int i;
  1901. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1902. if (!ATH_TXQ_SETUP(sc, i))
  1903. continue;
  1904. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1905. return true;
  1906. }
  1907. return false;
  1908. }
  1909. struct ieee80211_ops ath9k_ops = {
  1910. .tx = ath9k_tx,
  1911. .start = ath9k_start,
  1912. .stop = ath9k_stop,
  1913. .add_interface = ath9k_add_interface,
  1914. .change_interface = ath9k_change_interface,
  1915. .remove_interface = ath9k_remove_interface,
  1916. .config = ath9k_config,
  1917. .configure_filter = ath9k_configure_filter,
  1918. .sta_add = ath9k_sta_add,
  1919. .sta_remove = ath9k_sta_remove,
  1920. .sta_notify = ath9k_sta_notify,
  1921. .conf_tx = ath9k_conf_tx,
  1922. .bss_info_changed = ath9k_bss_info_changed,
  1923. .set_key = ath9k_set_key,
  1924. .get_tsf = ath9k_get_tsf,
  1925. .set_tsf = ath9k_set_tsf,
  1926. .reset_tsf = ath9k_reset_tsf,
  1927. .ampdu_action = ath9k_ampdu_action,
  1928. .get_survey = ath9k_get_survey,
  1929. .rfkill_poll = ath9k_rfkill_poll_state,
  1930. .set_coverage_class = ath9k_set_coverage_class,
  1931. .flush = ath9k_flush,
  1932. .tx_frames_pending = ath9k_tx_frames_pending,
  1933. };