ab8500-core.c 19 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com>
  7. * Author: Mattias Wallin <mattias.wallin@stericsson.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/init.h>
  12. #include <linux/irq.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/mfd/core.h>
  18. #include <linux/mfd/abx500.h>
  19. #include <linux/mfd/ab8500.h>
  20. #include <linux/regulator/ab8500.h>
  21. /*
  22. * Interrupt register offsets
  23. * Bank : 0x0E
  24. */
  25. #define AB8500_IT_SOURCE1_REG 0x00
  26. #define AB8500_IT_SOURCE2_REG 0x01
  27. #define AB8500_IT_SOURCE3_REG 0x02
  28. #define AB8500_IT_SOURCE4_REG 0x03
  29. #define AB8500_IT_SOURCE5_REG 0x04
  30. #define AB8500_IT_SOURCE6_REG 0x05
  31. #define AB8500_IT_SOURCE7_REG 0x06
  32. #define AB8500_IT_SOURCE8_REG 0x07
  33. #define AB8500_IT_SOURCE19_REG 0x12
  34. #define AB8500_IT_SOURCE20_REG 0x13
  35. #define AB8500_IT_SOURCE21_REG 0x14
  36. #define AB8500_IT_SOURCE22_REG 0x15
  37. #define AB8500_IT_SOURCE23_REG 0x16
  38. #define AB8500_IT_SOURCE24_REG 0x17
  39. /*
  40. * latch registers
  41. */
  42. #define AB8500_IT_LATCH1_REG 0x20
  43. #define AB8500_IT_LATCH2_REG 0x21
  44. #define AB8500_IT_LATCH3_REG 0x22
  45. #define AB8500_IT_LATCH4_REG 0x23
  46. #define AB8500_IT_LATCH5_REG 0x24
  47. #define AB8500_IT_LATCH6_REG 0x25
  48. #define AB8500_IT_LATCH7_REG 0x26
  49. #define AB8500_IT_LATCH8_REG 0x27
  50. #define AB8500_IT_LATCH9_REG 0x28
  51. #define AB8500_IT_LATCH10_REG 0x29
  52. #define AB8500_IT_LATCH12_REG 0x2B
  53. #define AB8500_IT_LATCH19_REG 0x32
  54. #define AB8500_IT_LATCH20_REG 0x33
  55. #define AB8500_IT_LATCH21_REG 0x34
  56. #define AB8500_IT_LATCH22_REG 0x35
  57. #define AB8500_IT_LATCH23_REG 0x36
  58. #define AB8500_IT_LATCH24_REG 0x37
  59. /*
  60. * mask registers
  61. */
  62. #define AB8500_IT_MASK1_REG 0x40
  63. #define AB8500_IT_MASK2_REG 0x41
  64. #define AB8500_IT_MASK3_REG 0x42
  65. #define AB8500_IT_MASK4_REG 0x43
  66. #define AB8500_IT_MASK5_REG 0x44
  67. #define AB8500_IT_MASK6_REG 0x45
  68. #define AB8500_IT_MASK7_REG 0x46
  69. #define AB8500_IT_MASK8_REG 0x47
  70. #define AB8500_IT_MASK9_REG 0x48
  71. #define AB8500_IT_MASK10_REG 0x49
  72. #define AB8500_IT_MASK11_REG 0x4A
  73. #define AB8500_IT_MASK12_REG 0x4B
  74. #define AB8500_IT_MASK13_REG 0x4C
  75. #define AB8500_IT_MASK14_REG 0x4D
  76. #define AB8500_IT_MASK15_REG 0x4E
  77. #define AB8500_IT_MASK16_REG 0x4F
  78. #define AB8500_IT_MASK17_REG 0x50
  79. #define AB8500_IT_MASK18_REG 0x51
  80. #define AB8500_IT_MASK19_REG 0x52
  81. #define AB8500_IT_MASK20_REG 0x53
  82. #define AB8500_IT_MASK21_REG 0x54
  83. #define AB8500_IT_MASK22_REG 0x55
  84. #define AB8500_IT_MASK23_REG 0x56
  85. #define AB8500_IT_MASK24_REG 0x57
  86. #define AB8500_REV_REG 0x80
  87. #define AB8500_SWITCH_OFF_STATUS 0x00
  88. /*
  89. * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
  90. * numbers are indexed into this array with (num / 8).
  91. *
  92. * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
  93. * offset 0.
  94. */
  95. static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
  96. 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
  97. };
  98. static int ab8500_get_chip_id(struct device *dev)
  99. {
  100. struct ab8500 *ab8500;
  101. if (!dev)
  102. return -EINVAL;
  103. ab8500 = dev_get_drvdata(dev->parent);
  104. return ab8500 ? (int)ab8500->chip_id : -EINVAL;
  105. }
  106. static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  107. u8 reg, u8 data)
  108. {
  109. int ret;
  110. /*
  111. * Put the u8 bank and u8 register together into a an u16.
  112. * The bank on higher 8 bits and register in lower 8 bits.
  113. * */
  114. u16 addr = ((u16)bank) << 8 | reg;
  115. dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
  116. ret = mutex_lock_interruptible(&ab8500->lock);
  117. if (ret)
  118. return ret;
  119. ret = ab8500->write(ab8500, addr, data);
  120. if (ret < 0)
  121. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  122. addr, ret);
  123. mutex_unlock(&ab8500->lock);
  124. return ret;
  125. }
  126. static int ab8500_set_register(struct device *dev, u8 bank,
  127. u8 reg, u8 value)
  128. {
  129. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  130. return set_register_interruptible(ab8500, bank, reg, value);
  131. }
  132. static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
  133. u8 reg, u8 *value)
  134. {
  135. int ret;
  136. /* put the u8 bank and u8 reg together into a an u16.
  137. * bank on higher 8 bits and reg in lower */
  138. u16 addr = ((u16)bank) << 8 | reg;
  139. ret = mutex_lock_interruptible(&ab8500->lock);
  140. if (ret)
  141. return ret;
  142. ret = ab8500->read(ab8500, addr);
  143. if (ret < 0)
  144. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  145. addr, ret);
  146. else
  147. *value = ret;
  148. mutex_unlock(&ab8500->lock);
  149. dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
  150. return ret;
  151. }
  152. static int ab8500_get_register(struct device *dev, u8 bank,
  153. u8 reg, u8 *value)
  154. {
  155. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  156. return get_register_interruptible(ab8500, bank, reg, value);
  157. }
  158. static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  159. u8 reg, u8 bitmask, u8 bitvalues)
  160. {
  161. int ret;
  162. u8 data;
  163. /* put the u8 bank and u8 reg together into a an u16.
  164. * bank on higher 8 bits and reg in lower */
  165. u16 addr = ((u16)bank) << 8 | reg;
  166. ret = mutex_lock_interruptible(&ab8500->lock);
  167. if (ret)
  168. return ret;
  169. ret = ab8500->read(ab8500, addr);
  170. if (ret < 0) {
  171. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  172. addr, ret);
  173. goto out;
  174. }
  175. data = (u8)ret;
  176. data = (~bitmask & data) | (bitmask & bitvalues);
  177. ret = ab8500->write(ab8500, addr, data);
  178. if (ret < 0)
  179. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  180. addr, ret);
  181. dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr, data);
  182. out:
  183. mutex_unlock(&ab8500->lock);
  184. return ret;
  185. }
  186. static int ab8500_mask_and_set_register(struct device *dev,
  187. u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
  188. {
  189. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  190. return mask_and_set_register_interruptible(ab8500, bank, reg,
  191. bitmask, bitvalues);
  192. }
  193. static struct abx500_ops ab8500_ops = {
  194. .get_chip_id = ab8500_get_chip_id,
  195. .get_register = ab8500_get_register,
  196. .set_register = ab8500_set_register,
  197. .get_register_page = NULL,
  198. .set_register_page = NULL,
  199. .mask_and_set_register = ab8500_mask_and_set_register,
  200. .event_registers_startup_state_get = NULL,
  201. .startup_irq_enabled = NULL,
  202. };
  203. static void ab8500_irq_lock(struct irq_data *data)
  204. {
  205. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  206. mutex_lock(&ab8500->irq_lock);
  207. }
  208. static void ab8500_irq_sync_unlock(struct irq_data *data)
  209. {
  210. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  211. int i;
  212. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  213. u8 old = ab8500->oldmask[i];
  214. u8 new = ab8500->mask[i];
  215. int reg;
  216. if (new == old)
  217. continue;
  218. /* Interrupt register 12 does'nt exist prior to version 0x20 */
  219. if (ab8500_irq_regoffset[i] == 11 && ab8500->chip_id < 0x20)
  220. continue;
  221. ab8500->oldmask[i] = new;
  222. reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i];
  223. set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
  224. }
  225. mutex_unlock(&ab8500->irq_lock);
  226. }
  227. static void ab8500_irq_mask(struct irq_data *data)
  228. {
  229. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  230. int offset = data->irq - ab8500->irq_base;
  231. int index = offset / 8;
  232. int mask = 1 << (offset % 8);
  233. ab8500->mask[index] |= mask;
  234. }
  235. static void ab8500_irq_unmask(struct irq_data *data)
  236. {
  237. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  238. int offset = data->irq - ab8500->irq_base;
  239. int index = offset / 8;
  240. int mask = 1 << (offset % 8);
  241. ab8500->mask[index] &= ~mask;
  242. }
  243. static struct irq_chip ab8500_irq_chip = {
  244. .name = "ab8500",
  245. .irq_bus_lock = ab8500_irq_lock,
  246. .irq_bus_sync_unlock = ab8500_irq_sync_unlock,
  247. .irq_mask = ab8500_irq_mask,
  248. .irq_unmask = ab8500_irq_unmask,
  249. };
  250. static irqreturn_t ab8500_irq(int irq, void *dev)
  251. {
  252. struct ab8500 *ab8500 = dev;
  253. int i;
  254. dev_vdbg(ab8500->dev, "interrupt\n");
  255. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  256. int regoffset = ab8500_irq_regoffset[i];
  257. int status;
  258. u8 value;
  259. /* Interrupt register 12 does'nt exist prior to version 0x20 */
  260. if (regoffset == 11 && ab8500->chip_id < 0x20)
  261. continue;
  262. status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
  263. AB8500_IT_LATCH1_REG + regoffset, &value);
  264. if (status < 0 || value == 0)
  265. continue;
  266. do {
  267. int bit = __ffs(value);
  268. int line = i * 8 + bit;
  269. handle_nested_irq(ab8500->irq_base + line);
  270. value &= ~(1 << bit);
  271. } while (value);
  272. }
  273. return IRQ_HANDLED;
  274. }
  275. static int ab8500_irq_init(struct ab8500 *ab8500)
  276. {
  277. int base = ab8500->irq_base;
  278. int irq;
  279. for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
  280. irq_set_chip_data(irq, ab8500);
  281. irq_set_chip_and_handler(irq, &ab8500_irq_chip,
  282. handle_simple_irq);
  283. irq_set_nested_thread(irq, 1);
  284. #ifdef CONFIG_ARM
  285. set_irq_flags(irq, IRQF_VALID);
  286. #else
  287. irq_set_noprobe(irq);
  288. #endif
  289. }
  290. return 0;
  291. }
  292. static void ab8500_irq_remove(struct ab8500 *ab8500)
  293. {
  294. int base = ab8500->irq_base;
  295. int irq;
  296. for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
  297. #ifdef CONFIG_ARM
  298. set_irq_flags(irq, 0);
  299. #endif
  300. irq_set_chip_and_handler(irq, NULL, NULL);
  301. irq_set_chip_data(irq, NULL);
  302. }
  303. }
  304. static struct resource ab8500_gpio_resources[] = {
  305. {
  306. .name = "GPIO_INT6",
  307. .start = AB8500_INT_GPIO6R,
  308. .end = AB8500_INT_GPIO41F,
  309. .flags = IORESOURCE_IRQ,
  310. }
  311. };
  312. static struct resource ab8500_gpadc_resources[] = {
  313. {
  314. .name = "HW_CONV_END",
  315. .start = AB8500_INT_GP_HW_ADC_CONV_END,
  316. .end = AB8500_INT_GP_HW_ADC_CONV_END,
  317. .flags = IORESOURCE_IRQ,
  318. },
  319. {
  320. .name = "SW_CONV_END",
  321. .start = AB8500_INT_GP_SW_ADC_CONV_END,
  322. .end = AB8500_INT_GP_SW_ADC_CONV_END,
  323. .flags = IORESOURCE_IRQ,
  324. },
  325. };
  326. static struct resource ab8500_rtc_resources[] = {
  327. {
  328. .name = "60S",
  329. .start = AB8500_INT_RTC_60S,
  330. .end = AB8500_INT_RTC_60S,
  331. .flags = IORESOURCE_IRQ,
  332. },
  333. {
  334. .name = "ALARM",
  335. .start = AB8500_INT_RTC_ALARM,
  336. .end = AB8500_INT_RTC_ALARM,
  337. .flags = IORESOURCE_IRQ,
  338. },
  339. };
  340. static struct resource ab8500_poweronkey_db_resources[] = {
  341. {
  342. .name = "ONKEY_DBF",
  343. .start = AB8500_INT_PON_KEY1DB_F,
  344. .end = AB8500_INT_PON_KEY1DB_F,
  345. .flags = IORESOURCE_IRQ,
  346. },
  347. {
  348. .name = "ONKEY_DBR",
  349. .start = AB8500_INT_PON_KEY1DB_R,
  350. .end = AB8500_INT_PON_KEY1DB_R,
  351. .flags = IORESOURCE_IRQ,
  352. },
  353. };
  354. static struct resource ab8500_bm_resources[] = {
  355. {
  356. .name = "MAIN_EXT_CH_NOT_OK",
  357. .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  358. .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  359. .flags = IORESOURCE_IRQ,
  360. },
  361. {
  362. .name = "BATT_OVV",
  363. .start = AB8500_INT_BATT_OVV,
  364. .end = AB8500_INT_BATT_OVV,
  365. .flags = IORESOURCE_IRQ,
  366. },
  367. {
  368. .name = "MAIN_CH_UNPLUG_DET",
  369. .start = AB8500_INT_MAIN_CH_UNPLUG_DET,
  370. .end = AB8500_INT_MAIN_CH_UNPLUG_DET,
  371. .flags = IORESOURCE_IRQ,
  372. },
  373. {
  374. .name = "MAIN_CHARGE_PLUG_DET",
  375. .start = AB8500_INT_MAIN_CH_PLUG_DET,
  376. .end = AB8500_INT_MAIN_CH_PLUG_DET,
  377. .flags = IORESOURCE_IRQ,
  378. },
  379. {
  380. .name = "VBUS_DET_F",
  381. .start = AB8500_INT_VBUS_DET_F,
  382. .end = AB8500_INT_VBUS_DET_F,
  383. .flags = IORESOURCE_IRQ,
  384. },
  385. {
  386. .name = "VBUS_DET_R",
  387. .start = AB8500_INT_VBUS_DET_R,
  388. .end = AB8500_INT_VBUS_DET_R,
  389. .flags = IORESOURCE_IRQ,
  390. },
  391. {
  392. .name = "BAT_CTRL_INDB",
  393. .start = AB8500_INT_BAT_CTRL_INDB,
  394. .end = AB8500_INT_BAT_CTRL_INDB,
  395. .flags = IORESOURCE_IRQ,
  396. },
  397. {
  398. .name = "CH_WD_EXP",
  399. .start = AB8500_INT_CH_WD_EXP,
  400. .end = AB8500_INT_CH_WD_EXP,
  401. .flags = IORESOURCE_IRQ,
  402. },
  403. {
  404. .name = "VBUS_OVV",
  405. .start = AB8500_INT_VBUS_OVV,
  406. .end = AB8500_INT_VBUS_OVV,
  407. .flags = IORESOURCE_IRQ,
  408. },
  409. {
  410. .name = "NCONV_ACCU",
  411. .start = AB8500_INT_CCN_CONV_ACC,
  412. .end = AB8500_INT_CCN_CONV_ACC,
  413. .flags = IORESOURCE_IRQ,
  414. },
  415. {
  416. .name = "LOW_BAT_F",
  417. .start = AB8500_INT_LOW_BAT_F,
  418. .end = AB8500_INT_LOW_BAT_F,
  419. .flags = IORESOURCE_IRQ,
  420. },
  421. {
  422. .name = "LOW_BAT_R",
  423. .start = AB8500_INT_LOW_BAT_R,
  424. .end = AB8500_INT_LOW_BAT_R,
  425. .flags = IORESOURCE_IRQ,
  426. },
  427. {
  428. .name = "BTEMP_LOW",
  429. .start = AB8500_INT_BTEMP_LOW,
  430. .end = AB8500_INT_BTEMP_LOW,
  431. .flags = IORESOURCE_IRQ,
  432. },
  433. {
  434. .name = "BTEMP_HIGH",
  435. .start = AB8500_INT_BTEMP_HIGH,
  436. .end = AB8500_INT_BTEMP_HIGH,
  437. .flags = IORESOURCE_IRQ,
  438. },
  439. {
  440. .name = "USB_CHARGER_NOT_OKR",
  441. .start = AB8500_INT_USB_CHARGER_NOT_OK,
  442. .end = AB8500_INT_USB_CHARGER_NOT_OK,
  443. .flags = IORESOURCE_IRQ,
  444. },
  445. {
  446. .name = "USB_CHARGE_DET_DONE",
  447. .start = AB8500_INT_USB_CHG_DET_DONE,
  448. .end = AB8500_INT_USB_CHG_DET_DONE,
  449. .flags = IORESOURCE_IRQ,
  450. },
  451. {
  452. .name = "USB_CH_TH_PROT_R",
  453. .start = AB8500_INT_USB_CH_TH_PROT_R,
  454. .end = AB8500_INT_USB_CH_TH_PROT_R,
  455. .flags = IORESOURCE_IRQ,
  456. },
  457. {
  458. .name = "MAIN_CH_TH_PROT_R",
  459. .start = AB8500_INT_MAIN_CH_TH_PROT_R,
  460. .end = AB8500_INT_MAIN_CH_TH_PROT_R,
  461. .flags = IORESOURCE_IRQ,
  462. },
  463. {
  464. .name = "USB_CHARGER_NOT_OKF",
  465. .start = AB8500_INT_USB_CHARGER_NOT_OKF,
  466. .end = AB8500_INT_USB_CHARGER_NOT_OKF,
  467. .flags = IORESOURCE_IRQ,
  468. },
  469. };
  470. static struct resource ab8500_debug_resources[] = {
  471. {
  472. .name = "IRQ_FIRST",
  473. .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  474. .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  475. .flags = IORESOURCE_IRQ,
  476. },
  477. {
  478. .name = "IRQ_LAST",
  479. .start = AB8500_INT_USB_CHARGER_NOT_OKF,
  480. .end = AB8500_INT_USB_CHARGER_NOT_OKF,
  481. .flags = IORESOURCE_IRQ,
  482. },
  483. };
  484. static struct resource ab8500_usb_resources[] = {
  485. {
  486. .name = "ID_WAKEUP_R",
  487. .start = AB8500_INT_ID_WAKEUP_R,
  488. .end = AB8500_INT_ID_WAKEUP_R,
  489. .flags = IORESOURCE_IRQ,
  490. },
  491. {
  492. .name = "ID_WAKEUP_F",
  493. .start = AB8500_INT_ID_WAKEUP_F,
  494. .end = AB8500_INT_ID_WAKEUP_F,
  495. .flags = IORESOURCE_IRQ,
  496. },
  497. {
  498. .name = "VBUS_DET_F",
  499. .start = AB8500_INT_VBUS_DET_F,
  500. .end = AB8500_INT_VBUS_DET_F,
  501. .flags = IORESOURCE_IRQ,
  502. },
  503. {
  504. .name = "VBUS_DET_R",
  505. .start = AB8500_INT_VBUS_DET_R,
  506. .end = AB8500_INT_VBUS_DET_R,
  507. .flags = IORESOURCE_IRQ,
  508. },
  509. {
  510. .name = "USB_LINK_STATUS",
  511. .start = AB8500_INT_USB_LINK_STATUS,
  512. .end = AB8500_INT_USB_LINK_STATUS,
  513. .flags = IORESOURCE_IRQ,
  514. },
  515. };
  516. static struct resource ab8500_temp_resources[] = {
  517. {
  518. .name = "AB8500_TEMP_WARM",
  519. .start = AB8500_INT_TEMP_WARM,
  520. .end = AB8500_INT_TEMP_WARM,
  521. .flags = IORESOURCE_IRQ,
  522. },
  523. };
  524. static struct mfd_cell ab8500_devs[] = {
  525. #ifdef CONFIG_DEBUG_FS
  526. {
  527. .name = "ab8500-debug",
  528. .num_resources = ARRAY_SIZE(ab8500_debug_resources),
  529. .resources = ab8500_debug_resources,
  530. },
  531. #endif
  532. {
  533. .name = "ab8500-sysctrl",
  534. },
  535. {
  536. .name = "ab8500-regulator",
  537. },
  538. {
  539. .name = "ab8500-gpio",
  540. .num_resources = ARRAY_SIZE(ab8500_gpio_resources),
  541. .resources = ab8500_gpio_resources,
  542. },
  543. {
  544. .name = "ab8500-gpadc",
  545. .num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
  546. .resources = ab8500_gpadc_resources,
  547. },
  548. {
  549. .name = "ab8500-rtc",
  550. .num_resources = ARRAY_SIZE(ab8500_rtc_resources),
  551. .resources = ab8500_rtc_resources,
  552. },
  553. {
  554. .name = "ab8500-bm",
  555. .num_resources = ARRAY_SIZE(ab8500_bm_resources),
  556. .resources = ab8500_bm_resources,
  557. },
  558. { .name = "ab8500-codec", },
  559. {
  560. .name = "ab8500-usb",
  561. .num_resources = ARRAY_SIZE(ab8500_usb_resources),
  562. .resources = ab8500_usb_resources,
  563. },
  564. {
  565. .name = "ab8500-poweron-key",
  566. .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
  567. .resources = ab8500_poweronkey_db_resources,
  568. },
  569. {
  570. .name = "ab8500-pwm",
  571. .id = 1,
  572. },
  573. {
  574. .name = "ab8500-pwm",
  575. .id = 2,
  576. },
  577. {
  578. .name = "ab8500-pwm",
  579. .id = 3,
  580. },
  581. { .name = "ab8500-leds", },
  582. {
  583. .name = "ab8500-denc",
  584. },
  585. {
  586. .name = "ab8500-temp",
  587. .num_resources = ARRAY_SIZE(ab8500_temp_resources),
  588. .resources = ab8500_temp_resources,
  589. },
  590. };
  591. static ssize_t show_chip_id(struct device *dev,
  592. struct device_attribute *attr, char *buf)
  593. {
  594. struct ab8500 *ab8500;
  595. ab8500 = dev_get_drvdata(dev);
  596. return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
  597. }
  598. /*
  599. * ab8500 has switched off due to (SWITCH_OFF_STATUS):
  600. * 0x01 Swoff bit programming
  601. * 0x02 Thermal protection activation
  602. * 0x04 Vbat lower then BattOk falling threshold
  603. * 0x08 Watchdog expired
  604. * 0x10 Non presence of 32kHz clock
  605. * 0x20 Battery level lower than power on reset threshold
  606. * 0x40 Power on key 1 pressed longer than 10 seconds
  607. * 0x80 DB8500 thermal shutdown
  608. */
  609. static ssize_t show_switch_off_status(struct device *dev,
  610. struct device_attribute *attr, char *buf)
  611. {
  612. int ret;
  613. u8 value;
  614. struct ab8500 *ab8500;
  615. ab8500 = dev_get_drvdata(dev);
  616. ret = get_register_interruptible(ab8500, AB8500_RTC,
  617. AB8500_SWITCH_OFF_STATUS, &value);
  618. if (ret < 0)
  619. return ret;
  620. return sprintf(buf, "%#x\n", value);
  621. }
  622. static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
  623. static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
  624. static struct attribute *ab8500_sysfs_entries[] = {
  625. &dev_attr_chip_id.attr,
  626. &dev_attr_switch_off_status.attr,
  627. NULL,
  628. };
  629. static struct attribute_group ab8500_attr_group = {
  630. .attrs = ab8500_sysfs_entries,
  631. };
  632. int __devinit ab8500_init(struct ab8500 *ab8500)
  633. {
  634. struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
  635. int ret;
  636. int i;
  637. u8 value;
  638. if (plat)
  639. ab8500->irq_base = plat->irq_base;
  640. mutex_init(&ab8500->lock);
  641. mutex_init(&ab8500->irq_lock);
  642. ret = get_register_interruptible(ab8500, AB8500_MISC,
  643. AB8500_REV_REG, &value);
  644. if (ret < 0)
  645. return ret;
  646. /*
  647. * 0x0 - Early Drop
  648. * 0x10 - Cut 1.0
  649. * 0x11 - Cut 1.1
  650. * 0x20 - Cut 2.0
  651. * 0x30 - Cut 3.0
  652. */
  653. if (value == 0x0 || value == 0x10 || value == 0x11 || value == 0x20 ||
  654. value == 0x30) {
  655. dev_info(ab8500->dev, "detected chip, revision: %#x\n", value);
  656. } else {
  657. dev_err(ab8500->dev, "unknown chip, revision: %#x\n", value);
  658. return -EINVAL;
  659. }
  660. ab8500->chip_id = value;
  661. /*
  662. * ab8500 has switched off due to (SWITCH_OFF_STATUS):
  663. * 0x01 Swoff bit programming
  664. * 0x02 Thermal protection activation
  665. * 0x04 Vbat lower then BattOk falling threshold
  666. * 0x08 Watchdog expired
  667. * 0x10 Non presence of 32kHz clock
  668. * 0x20 Battery level lower than power on reset threshold
  669. * 0x40 Power on key 1 pressed longer than 10 seconds
  670. * 0x80 DB8500 thermal shutdown
  671. */
  672. ret = get_register_interruptible(ab8500, AB8500_RTC,
  673. AB8500_SWITCH_OFF_STATUS, &value);
  674. if (ret < 0)
  675. return ret;
  676. dev_info(ab8500->dev, "switch off status: %#x", value);
  677. if (plat && plat->init)
  678. plat->init(ab8500);
  679. /* Clear and mask all interrupts */
  680. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  681. /* Interrupt register 12 does'nt exist prior to version 0x20 */
  682. if (ab8500_irq_regoffset[i] == 11 && ab8500->chip_id < 0x20)
  683. continue;
  684. get_register_interruptible(ab8500, AB8500_INTERRUPT,
  685. AB8500_IT_LATCH1_REG + ab8500_irq_regoffset[i],
  686. &value);
  687. set_register_interruptible(ab8500, AB8500_INTERRUPT,
  688. AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i], 0xff);
  689. }
  690. ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
  691. if (ret)
  692. return ret;
  693. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++)
  694. ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
  695. if (ab8500->irq_base) {
  696. ret = ab8500_irq_init(ab8500);
  697. if (ret)
  698. return ret;
  699. ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq,
  700. IRQF_ONESHOT | IRQF_NO_SUSPEND,
  701. "ab8500", ab8500);
  702. if (ret)
  703. goto out_removeirq;
  704. }
  705. ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
  706. ARRAY_SIZE(ab8500_devs), NULL,
  707. ab8500->irq_base);
  708. if (ret)
  709. goto out_freeirq;
  710. ret = sysfs_create_group(&ab8500->dev->kobj, &ab8500_attr_group);
  711. if (ret)
  712. dev_err(ab8500->dev, "error creating sysfs entries\n");
  713. return ret;
  714. out_freeirq:
  715. if (ab8500->irq_base) {
  716. free_irq(ab8500->irq, ab8500);
  717. out_removeirq:
  718. ab8500_irq_remove(ab8500);
  719. }
  720. return ret;
  721. }
  722. int __devexit ab8500_exit(struct ab8500 *ab8500)
  723. {
  724. sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
  725. mfd_remove_devices(ab8500->dev);
  726. if (ab8500->irq_base) {
  727. free_irq(ab8500->irq, ab8500);
  728. ab8500_irq_remove(ab8500);
  729. }
  730. return 0;
  731. }
  732. MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent");
  733. MODULE_DESCRIPTION("AB8500 MFD core");
  734. MODULE_LICENSE("GPL v2");