pt1.c 24 KB

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  1. /*
  2. * driver for Earthsoft PT1/PT2
  3. *
  4. * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
  5. *
  6. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  7. * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/pci.h>
  28. #include <linux/kthread.h>
  29. #include <linux/freezer.h>
  30. #include "dvbdev.h"
  31. #include "dvb_demux.h"
  32. #include "dmxdev.h"
  33. #include "dvb_net.h"
  34. #include "dvb_frontend.h"
  35. #include "va1j5jf8007t.h"
  36. #include "va1j5jf8007s.h"
  37. #define DRIVER_NAME "earth-pt1"
  38. #define PT1_PAGE_SHIFT 12
  39. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  40. #define PT1_NR_UPACKETS 1024
  41. #define PT1_NR_BUFS 511
  42. struct pt1_buffer_page {
  43. __le32 upackets[PT1_NR_UPACKETS];
  44. };
  45. struct pt1_table_page {
  46. __le32 next_pfn;
  47. __le32 buf_pfns[PT1_NR_BUFS];
  48. };
  49. struct pt1_buffer {
  50. struct pt1_buffer_page *page;
  51. dma_addr_t addr;
  52. };
  53. struct pt1_table {
  54. struct pt1_table_page *page;
  55. dma_addr_t addr;
  56. struct pt1_buffer bufs[PT1_NR_BUFS];
  57. };
  58. #define PT1_NR_ADAPS 4
  59. struct pt1_adapter;
  60. struct pt1 {
  61. struct pci_dev *pdev;
  62. void __iomem *regs;
  63. struct i2c_adapter i2c_adap;
  64. int i2c_running;
  65. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  66. struct pt1_table *tables;
  67. struct task_struct *kthread;
  68. struct mutex lock;
  69. int power;
  70. int reset;
  71. };
  72. struct pt1_adapter {
  73. struct pt1 *pt1;
  74. int index;
  75. u8 *buf;
  76. int upacket_count;
  77. int packet_count;
  78. struct dvb_adapter adap;
  79. struct dvb_demux demux;
  80. int users;
  81. struct dmxdev dmxdev;
  82. struct dvb_net net;
  83. struct dvb_frontend *fe;
  84. int (*orig_set_voltage)(struct dvb_frontend *fe,
  85. fe_sec_voltage_t voltage);
  86. int (*orig_sleep)(struct dvb_frontend *fe);
  87. int (*orig_init)(struct dvb_frontend *fe);
  88. fe_sec_voltage_t voltage;
  89. int sleep;
  90. };
  91. #define pt1_printk(level, pt1, format, arg...) \
  92. dev_printk(level, &(pt1)->pdev->dev, format, ##arg)
  93. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  94. {
  95. writel(data, pt1->regs + reg * 4);
  96. }
  97. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  98. {
  99. return readl(pt1->regs + reg * 4);
  100. }
  101. static int pt1_nr_tables = 64;
  102. module_param_named(nr_tables, pt1_nr_tables, int, 0);
  103. static void pt1_increment_table_count(struct pt1 *pt1)
  104. {
  105. pt1_write_reg(pt1, 0, 0x00000020);
  106. }
  107. static void pt1_init_table_count(struct pt1 *pt1)
  108. {
  109. pt1_write_reg(pt1, 0, 0x00000010);
  110. }
  111. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  112. {
  113. pt1_write_reg(pt1, 5, first_pfn);
  114. pt1_write_reg(pt1, 0, 0x0c000040);
  115. }
  116. static void pt1_unregister_tables(struct pt1 *pt1)
  117. {
  118. pt1_write_reg(pt1, 0, 0x08080000);
  119. }
  120. static int pt1_sync(struct pt1 *pt1)
  121. {
  122. int i;
  123. for (i = 0; i < 57; i++) {
  124. if (pt1_read_reg(pt1, 0) & 0x20000000)
  125. return 0;
  126. pt1_write_reg(pt1, 0, 0x00000008);
  127. }
  128. pt1_printk(KERN_ERR, pt1, "could not sync\n");
  129. return -EIO;
  130. }
  131. static u64 pt1_identify(struct pt1 *pt1)
  132. {
  133. int i;
  134. u64 id;
  135. id = 0;
  136. for (i = 0; i < 57; i++) {
  137. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  138. pt1_write_reg(pt1, 0, 0x00000008);
  139. }
  140. return id;
  141. }
  142. static int pt1_unlock(struct pt1 *pt1)
  143. {
  144. int i;
  145. pt1_write_reg(pt1, 0, 0x00000008);
  146. for (i = 0; i < 3; i++) {
  147. if (pt1_read_reg(pt1, 0) & 0x80000000)
  148. return 0;
  149. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  150. }
  151. pt1_printk(KERN_ERR, pt1, "could not unlock\n");
  152. return -EIO;
  153. }
  154. static int pt1_reset_pci(struct pt1 *pt1)
  155. {
  156. int i;
  157. pt1_write_reg(pt1, 0, 0x01010000);
  158. pt1_write_reg(pt1, 0, 0x01000000);
  159. for (i = 0; i < 10; i++) {
  160. if (pt1_read_reg(pt1, 0) & 0x00000001)
  161. return 0;
  162. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  163. }
  164. pt1_printk(KERN_ERR, pt1, "could not reset PCI\n");
  165. return -EIO;
  166. }
  167. static int pt1_reset_ram(struct pt1 *pt1)
  168. {
  169. int i;
  170. pt1_write_reg(pt1, 0, 0x02020000);
  171. pt1_write_reg(pt1, 0, 0x02000000);
  172. for (i = 0; i < 10; i++) {
  173. if (pt1_read_reg(pt1, 0) & 0x00000002)
  174. return 0;
  175. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  176. }
  177. pt1_printk(KERN_ERR, pt1, "could not reset RAM\n");
  178. return -EIO;
  179. }
  180. static int pt1_do_enable_ram(struct pt1 *pt1)
  181. {
  182. int i, j;
  183. u32 status;
  184. status = pt1_read_reg(pt1, 0) & 0x00000004;
  185. pt1_write_reg(pt1, 0, 0x00000002);
  186. for (i = 0; i < 10; i++) {
  187. for (j = 0; j < 1024; j++) {
  188. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  189. return 0;
  190. }
  191. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  192. }
  193. pt1_printk(KERN_ERR, pt1, "could not enable RAM\n");
  194. return -EIO;
  195. }
  196. static int pt1_enable_ram(struct pt1 *pt1)
  197. {
  198. int i, ret;
  199. int phase;
  200. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  201. phase = pt1->pdev->device == 0x211a ? 128 : 166;
  202. for (i = 0; i < phase; i++) {
  203. ret = pt1_do_enable_ram(pt1);
  204. if (ret < 0)
  205. return ret;
  206. }
  207. return 0;
  208. }
  209. static void pt1_disable_ram(struct pt1 *pt1)
  210. {
  211. pt1_write_reg(pt1, 0, 0x0b0b0000);
  212. }
  213. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  214. {
  215. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  216. }
  217. static void pt1_init_streams(struct pt1 *pt1)
  218. {
  219. int i;
  220. for (i = 0; i < PT1_NR_ADAPS; i++)
  221. pt1_set_stream(pt1, i, 0);
  222. }
  223. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  224. {
  225. u32 upacket;
  226. int i;
  227. int index;
  228. struct pt1_adapter *adap;
  229. int offset;
  230. u8 *buf;
  231. if (!page->upackets[PT1_NR_UPACKETS - 1])
  232. return 0;
  233. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  234. upacket = le32_to_cpu(page->upackets[i]);
  235. index = (upacket >> 29) - 1;
  236. if (index < 0 || index >= PT1_NR_ADAPS)
  237. continue;
  238. adap = pt1->adaps[index];
  239. if (upacket >> 25 & 1)
  240. adap->upacket_count = 0;
  241. else if (!adap->upacket_count)
  242. continue;
  243. buf = adap->buf;
  244. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  245. buf[offset] = upacket >> 16;
  246. buf[offset + 1] = upacket >> 8;
  247. if (adap->upacket_count != 62)
  248. buf[offset + 2] = upacket;
  249. if (++adap->upacket_count >= 63) {
  250. adap->upacket_count = 0;
  251. if (++adap->packet_count >= 21) {
  252. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  253. adap->packet_count = 0;
  254. }
  255. }
  256. }
  257. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  258. return 1;
  259. }
  260. static int pt1_thread(void *data)
  261. {
  262. struct pt1 *pt1;
  263. int table_index;
  264. int buf_index;
  265. struct pt1_buffer_page *page;
  266. pt1 = data;
  267. set_freezable();
  268. table_index = 0;
  269. buf_index = 0;
  270. while (!kthread_should_stop()) {
  271. try_to_freeze();
  272. page = pt1->tables[table_index].bufs[buf_index].page;
  273. if (!pt1_filter(pt1, page)) {
  274. schedule_timeout_interruptible((HZ + 999) / 1000);
  275. continue;
  276. }
  277. if (++buf_index >= PT1_NR_BUFS) {
  278. pt1_increment_table_count(pt1);
  279. buf_index = 0;
  280. if (++table_index >= pt1_nr_tables)
  281. table_index = 0;
  282. }
  283. }
  284. return 0;
  285. }
  286. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  287. {
  288. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  289. }
  290. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  291. {
  292. void *page;
  293. dma_addr_t addr;
  294. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  295. GFP_KERNEL);
  296. if (page == NULL)
  297. return NULL;
  298. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  299. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  300. *addrp = addr;
  301. *pfnp = addr >> PT1_PAGE_SHIFT;
  302. return page;
  303. }
  304. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  305. {
  306. pt1_free_page(pt1, buf->page, buf->addr);
  307. }
  308. static int
  309. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  310. {
  311. struct pt1_buffer_page *page;
  312. dma_addr_t addr;
  313. page = pt1_alloc_page(pt1, &addr, pfnp);
  314. if (page == NULL)
  315. return -ENOMEM;
  316. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  317. buf->page = page;
  318. buf->addr = addr;
  319. return 0;
  320. }
  321. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  322. {
  323. int i;
  324. for (i = 0; i < PT1_NR_BUFS; i++)
  325. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  326. pt1_free_page(pt1, table->page, table->addr);
  327. }
  328. static int
  329. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  330. {
  331. struct pt1_table_page *page;
  332. dma_addr_t addr;
  333. int i, ret;
  334. u32 buf_pfn;
  335. page = pt1_alloc_page(pt1, &addr, pfnp);
  336. if (page == NULL)
  337. return -ENOMEM;
  338. for (i = 0; i < PT1_NR_BUFS; i++) {
  339. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  340. if (ret < 0)
  341. goto err;
  342. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  343. }
  344. pt1_increment_table_count(pt1);
  345. table->page = page;
  346. table->addr = addr;
  347. return 0;
  348. err:
  349. while (i--)
  350. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  351. pt1_free_page(pt1, page, addr);
  352. return ret;
  353. }
  354. static void pt1_cleanup_tables(struct pt1 *pt1)
  355. {
  356. struct pt1_table *tables;
  357. int i;
  358. tables = pt1->tables;
  359. pt1_unregister_tables(pt1);
  360. for (i = 0; i < pt1_nr_tables; i++)
  361. pt1_cleanup_table(pt1, &tables[i]);
  362. vfree(tables);
  363. }
  364. static int pt1_init_tables(struct pt1 *pt1)
  365. {
  366. struct pt1_table *tables;
  367. int i, ret;
  368. u32 first_pfn, pfn;
  369. tables = vmalloc(sizeof(struct pt1_table) * pt1_nr_tables);
  370. if (tables == NULL)
  371. return -ENOMEM;
  372. pt1_init_table_count(pt1);
  373. i = 0;
  374. if (pt1_nr_tables) {
  375. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  376. if (ret)
  377. goto err;
  378. i++;
  379. }
  380. while (i < pt1_nr_tables) {
  381. ret = pt1_init_table(pt1, &tables[i], &pfn);
  382. if (ret)
  383. goto err;
  384. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  385. i++;
  386. }
  387. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  388. pt1_register_tables(pt1, first_pfn);
  389. pt1->tables = tables;
  390. return 0;
  391. err:
  392. while (i--)
  393. pt1_cleanup_table(pt1, &tables[i]);
  394. vfree(tables);
  395. return ret;
  396. }
  397. static int pt1_start_feed(struct dvb_demux_feed *feed)
  398. {
  399. struct pt1_adapter *adap;
  400. adap = container_of(feed->demux, struct pt1_adapter, demux);
  401. if (!adap->users++)
  402. pt1_set_stream(adap->pt1, adap->index, 1);
  403. return 0;
  404. }
  405. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  406. {
  407. struct pt1_adapter *adap;
  408. adap = container_of(feed->demux, struct pt1_adapter, demux);
  409. if (!--adap->users)
  410. pt1_set_stream(adap->pt1, adap->index, 0);
  411. return 0;
  412. }
  413. static void
  414. pt1_update_power(struct pt1 *pt1)
  415. {
  416. int bits;
  417. int i;
  418. struct pt1_adapter *adap;
  419. static const int sleep_bits[] = {
  420. 1 << 4,
  421. 1 << 6 | 1 << 7,
  422. 1 << 5,
  423. 1 << 6 | 1 << 8,
  424. };
  425. bits = pt1->power | !pt1->reset << 3;
  426. mutex_lock(&pt1->lock);
  427. for (i = 0; i < PT1_NR_ADAPS; i++) {
  428. adap = pt1->adaps[i];
  429. switch (adap->voltage) {
  430. case SEC_VOLTAGE_13: /* actually 11V */
  431. bits |= 1 << 1;
  432. break;
  433. case SEC_VOLTAGE_18: /* actually 15V */
  434. bits |= 1 << 1 | 1 << 2;
  435. break;
  436. default:
  437. break;
  438. }
  439. /* XXX: The bits should be changed depending on adap->sleep. */
  440. bits |= sleep_bits[i];
  441. }
  442. pt1_write_reg(pt1, 1, bits);
  443. mutex_unlock(&pt1->lock);
  444. }
  445. static int pt1_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  446. {
  447. struct pt1_adapter *adap;
  448. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  449. adap->voltage = voltage;
  450. pt1_update_power(adap->pt1);
  451. if (adap->orig_set_voltage)
  452. return adap->orig_set_voltage(fe, voltage);
  453. else
  454. return 0;
  455. }
  456. static int pt1_sleep(struct dvb_frontend *fe)
  457. {
  458. struct pt1_adapter *adap;
  459. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  460. adap->sleep = 1;
  461. pt1_update_power(adap->pt1);
  462. if (adap->orig_sleep)
  463. return adap->orig_sleep(fe);
  464. else
  465. return 0;
  466. }
  467. static int pt1_wakeup(struct dvb_frontend *fe)
  468. {
  469. struct pt1_adapter *adap;
  470. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  471. adap->sleep = 0;
  472. pt1_update_power(adap->pt1);
  473. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  474. if (adap->orig_init)
  475. return adap->orig_init(fe);
  476. else
  477. return 0;
  478. }
  479. static void pt1_free_adapter(struct pt1_adapter *adap)
  480. {
  481. dvb_net_release(&adap->net);
  482. adap->demux.dmx.close(&adap->demux.dmx);
  483. dvb_dmxdev_release(&adap->dmxdev);
  484. dvb_dmx_release(&adap->demux);
  485. dvb_unregister_adapter(&adap->adap);
  486. free_page((unsigned long)adap->buf);
  487. kfree(adap);
  488. }
  489. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  490. static struct pt1_adapter *
  491. pt1_alloc_adapter(struct pt1 *pt1)
  492. {
  493. struct pt1_adapter *adap;
  494. void *buf;
  495. struct dvb_adapter *dvb_adap;
  496. struct dvb_demux *demux;
  497. struct dmxdev *dmxdev;
  498. int ret;
  499. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  500. if (!adap) {
  501. ret = -ENOMEM;
  502. goto err;
  503. }
  504. adap->pt1 = pt1;
  505. adap->voltage = SEC_VOLTAGE_OFF;
  506. adap->sleep = 1;
  507. buf = (u8 *)__get_free_page(GFP_KERNEL);
  508. if (!buf) {
  509. ret = -ENOMEM;
  510. goto err_kfree;
  511. }
  512. adap->buf = buf;
  513. adap->upacket_count = 0;
  514. adap->packet_count = 0;
  515. dvb_adap = &adap->adap;
  516. dvb_adap->priv = adap;
  517. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  518. &pt1->pdev->dev, adapter_nr);
  519. if (ret < 0)
  520. goto err_free_page;
  521. demux = &adap->demux;
  522. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  523. demux->priv = adap;
  524. demux->feednum = 256;
  525. demux->filternum = 256;
  526. demux->start_feed = pt1_start_feed;
  527. demux->stop_feed = pt1_stop_feed;
  528. demux->write_to_decoder = NULL;
  529. ret = dvb_dmx_init(demux);
  530. if (ret < 0)
  531. goto err_unregister_adapter;
  532. dmxdev = &adap->dmxdev;
  533. dmxdev->filternum = 256;
  534. dmxdev->demux = &demux->dmx;
  535. dmxdev->capabilities = 0;
  536. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  537. if (ret < 0)
  538. goto err_dmx_release;
  539. dvb_net_init(dvb_adap, &adap->net, &demux->dmx);
  540. return adap;
  541. err_dmx_release:
  542. dvb_dmx_release(demux);
  543. err_unregister_adapter:
  544. dvb_unregister_adapter(dvb_adap);
  545. err_free_page:
  546. free_page((unsigned long)buf);
  547. err_kfree:
  548. kfree(adap);
  549. err:
  550. return ERR_PTR(ret);
  551. }
  552. static void pt1_cleanup_adapters(struct pt1 *pt1)
  553. {
  554. int i;
  555. for (i = 0; i < PT1_NR_ADAPS; i++)
  556. pt1_free_adapter(pt1->adaps[i]);
  557. }
  558. static int pt1_init_adapters(struct pt1 *pt1)
  559. {
  560. int i;
  561. struct pt1_adapter *adap;
  562. int ret;
  563. for (i = 0; i < PT1_NR_ADAPS; i++) {
  564. adap = pt1_alloc_adapter(pt1);
  565. if (IS_ERR(adap)) {
  566. ret = PTR_ERR(adap);
  567. goto err;
  568. }
  569. adap->index = i;
  570. pt1->adaps[i] = adap;
  571. }
  572. return 0;
  573. err:
  574. while (i--)
  575. pt1_free_adapter(pt1->adaps[i]);
  576. return ret;
  577. }
  578. static void pt1_cleanup_frontend(struct pt1_adapter *adap)
  579. {
  580. dvb_unregister_frontend(adap->fe);
  581. }
  582. static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
  583. {
  584. int ret;
  585. adap->orig_set_voltage = fe->ops.set_voltage;
  586. adap->orig_sleep = fe->ops.sleep;
  587. adap->orig_init = fe->ops.init;
  588. fe->ops.set_voltage = pt1_set_voltage;
  589. fe->ops.sleep = pt1_sleep;
  590. fe->ops.init = pt1_wakeup;
  591. ret = dvb_register_frontend(&adap->adap, fe);
  592. if (ret < 0)
  593. return ret;
  594. adap->fe = fe;
  595. return 0;
  596. }
  597. static void pt1_cleanup_frontends(struct pt1 *pt1)
  598. {
  599. int i;
  600. for (i = 0; i < PT1_NR_ADAPS; i++)
  601. pt1_cleanup_frontend(pt1->adaps[i]);
  602. }
  603. struct pt1_config {
  604. struct va1j5jf8007s_config va1j5jf8007s_config;
  605. struct va1j5jf8007t_config va1j5jf8007t_config;
  606. };
  607. static const struct pt1_config pt1_configs[2] = {
  608. {
  609. {
  610. .demod_address = 0x1b,
  611. .frequency = VA1J5JF8007S_20MHZ,
  612. },
  613. {
  614. .demod_address = 0x1a,
  615. .frequency = VA1J5JF8007T_20MHZ,
  616. },
  617. }, {
  618. {
  619. .demod_address = 0x19,
  620. .frequency = VA1J5JF8007S_20MHZ,
  621. },
  622. {
  623. .demod_address = 0x18,
  624. .frequency = VA1J5JF8007T_20MHZ,
  625. },
  626. },
  627. };
  628. static const struct pt1_config pt2_configs[2] = {
  629. {
  630. {
  631. .demod_address = 0x1b,
  632. .frequency = VA1J5JF8007S_25MHZ,
  633. },
  634. {
  635. .demod_address = 0x1a,
  636. .frequency = VA1J5JF8007T_25MHZ,
  637. },
  638. }, {
  639. {
  640. .demod_address = 0x19,
  641. .frequency = VA1J5JF8007S_25MHZ,
  642. },
  643. {
  644. .demod_address = 0x18,
  645. .frequency = VA1J5JF8007T_25MHZ,
  646. },
  647. },
  648. };
  649. static int pt1_init_frontends(struct pt1 *pt1)
  650. {
  651. int i, j;
  652. struct i2c_adapter *i2c_adap;
  653. const struct pt1_config *configs, *config;
  654. struct dvb_frontend *fe[4];
  655. int ret;
  656. i = 0;
  657. j = 0;
  658. i2c_adap = &pt1->i2c_adap;
  659. configs = pt1->pdev->device == 0x211a ? pt1_configs : pt2_configs;
  660. do {
  661. config = &configs[i / 2];
  662. fe[i] = va1j5jf8007s_attach(&config->va1j5jf8007s_config,
  663. i2c_adap);
  664. if (!fe[i]) {
  665. ret = -ENODEV; /* This does not sound nice... */
  666. goto err;
  667. }
  668. i++;
  669. fe[i] = va1j5jf8007t_attach(&config->va1j5jf8007t_config,
  670. i2c_adap);
  671. if (!fe[i]) {
  672. ret = -ENODEV;
  673. goto err;
  674. }
  675. i++;
  676. ret = va1j5jf8007s_prepare(fe[i - 2]);
  677. if (ret < 0)
  678. goto err;
  679. ret = va1j5jf8007t_prepare(fe[i - 1]);
  680. if (ret < 0)
  681. goto err;
  682. } while (i < 4);
  683. do {
  684. ret = pt1_init_frontend(pt1->adaps[j], fe[j]);
  685. if (ret < 0)
  686. goto err;
  687. } while (++j < 4);
  688. return 0;
  689. err:
  690. while (i-- > j)
  691. fe[i]->ops.release(fe[i]);
  692. while (j--)
  693. dvb_unregister_frontend(fe[j]);
  694. return ret;
  695. }
  696. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  697. int clock, int data, int next_addr)
  698. {
  699. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  700. !clock << 11 | !data << 10 | next_addr);
  701. }
  702. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  703. {
  704. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  705. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  706. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  707. *addrp = addr + 3;
  708. }
  709. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  710. {
  711. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  712. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  713. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  714. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  715. *addrp = addr + 4;
  716. }
  717. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  718. {
  719. int i;
  720. for (i = 0; i < 8; i++)
  721. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  722. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  723. *addrp = addr;
  724. }
  725. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  726. {
  727. int i;
  728. for (i = 0; i < 8; i++)
  729. pt1_i2c_read_bit(pt1, addr, &addr);
  730. pt1_i2c_write_bit(pt1, addr, &addr, last);
  731. *addrp = addr;
  732. }
  733. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  734. {
  735. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  736. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  737. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  738. *addrp = addr + 3;
  739. }
  740. static void
  741. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  742. {
  743. int i;
  744. pt1_i2c_prepare(pt1, addr, &addr);
  745. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  746. for (i = 0; i < msg->len; i++)
  747. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  748. *addrp = addr;
  749. }
  750. static void
  751. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  752. {
  753. int i;
  754. pt1_i2c_prepare(pt1, addr, &addr);
  755. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  756. for (i = 0; i < msg->len; i++)
  757. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  758. *addrp = addr;
  759. }
  760. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  761. {
  762. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  763. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  764. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  765. pt1_write_reg(pt1, 0, 0x00000004);
  766. do {
  767. if (signal_pending(current))
  768. return -EINTR;
  769. schedule_timeout_interruptible((HZ + 999) / 1000);
  770. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  771. return 0;
  772. }
  773. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  774. {
  775. int addr;
  776. addr = 0;
  777. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  778. addr = addr + 1;
  779. if (!pt1->i2c_running) {
  780. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  781. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  782. addr = addr + 2;
  783. pt1->i2c_running = 1;
  784. }
  785. *addrp = addr;
  786. }
  787. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  788. {
  789. struct pt1 *pt1;
  790. int i;
  791. struct i2c_msg *msg, *next_msg;
  792. int addr, ret;
  793. u16 len;
  794. u32 word;
  795. pt1 = i2c_get_adapdata(adap);
  796. for (i = 0; i < num; i++) {
  797. msg = &msgs[i];
  798. if (msg->flags & I2C_M_RD)
  799. return -ENOTSUPP;
  800. if (i + 1 < num)
  801. next_msg = &msgs[i + 1];
  802. else
  803. next_msg = NULL;
  804. if (next_msg && next_msg->flags & I2C_M_RD) {
  805. i++;
  806. len = next_msg->len;
  807. if (len > 4)
  808. return -ENOTSUPP;
  809. pt1_i2c_begin(pt1, &addr);
  810. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  811. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  812. ret = pt1_i2c_end(pt1, addr);
  813. if (ret < 0)
  814. return ret;
  815. word = pt1_read_reg(pt1, 2);
  816. while (len--) {
  817. next_msg->buf[len] = word;
  818. word >>= 8;
  819. }
  820. } else {
  821. pt1_i2c_begin(pt1, &addr);
  822. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  823. ret = pt1_i2c_end(pt1, addr);
  824. if (ret < 0)
  825. return ret;
  826. }
  827. }
  828. return num;
  829. }
  830. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  831. {
  832. return I2C_FUNC_I2C;
  833. }
  834. static const struct i2c_algorithm pt1_i2c_algo = {
  835. .master_xfer = pt1_i2c_xfer,
  836. .functionality = pt1_i2c_func,
  837. };
  838. static void pt1_i2c_wait(struct pt1 *pt1)
  839. {
  840. int i;
  841. for (i = 0; i < 128; i++)
  842. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  843. }
  844. static void pt1_i2c_init(struct pt1 *pt1)
  845. {
  846. int i;
  847. for (i = 0; i < 1024; i++)
  848. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  849. }
  850. static void __devexit pt1_remove(struct pci_dev *pdev)
  851. {
  852. struct pt1 *pt1;
  853. void __iomem *regs;
  854. pt1 = pci_get_drvdata(pdev);
  855. regs = pt1->regs;
  856. kthread_stop(pt1->kthread);
  857. pt1_cleanup_tables(pt1);
  858. pt1_cleanup_frontends(pt1);
  859. pt1_disable_ram(pt1);
  860. pt1->power = 0;
  861. pt1->reset = 1;
  862. pt1_update_power(pt1);
  863. pt1_cleanup_adapters(pt1);
  864. i2c_del_adapter(&pt1->i2c_adap);
  865. pci_set_drvdata(pdev, NULL);
  866. kfree(pt1);
  867. pci_iounmap(pdev, regs);
  868. pci_release_regions(pdev);
  869. pci_disable_device(pdev);
  870. }
  871. static int __devinit
  872. pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  873. {
  874. int ret;
  875. void __iomem *regs;
  876. struct pt1 *pt1;
  877. struct i2c_adapter *i2c_adap;
  878. struct task_struct *kthread;
  879. ret = pci_enable_device(pdev);
  880. if (ret < 0)
  881. goto err;
  882. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  883. if (ret < 0)
  884. goto err_pci_disable_device;
  885. pci_set_master(pdev);
  886. ret = pci_request_regions(pdev, DRIVER_NAME);
  887. if (ret < 0)
  888. goto err_pci_disable_device;
  889. regs = pci_iomap(pdev, 0, 0);
  890. if (!regs) {
  891. ret = -EIO;
  892. goto err_pci_release_regions;
  893. }
  894. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  895. if (!pt1) {
  896. ret = -ENOMEM;
  897. goto err_pci_iounmap;
  898. }
  899. mutex_init(&pt1->lock);
  900. pt1->pdev = pdev;
  901. pt1->regs = regs;
  902. pci_set_drvdata(pdev, pt1);
  903. ret = pt1_init_adapters(pt1);
  904. if (ret < 0)
  905. goto err_kfree;
  906. mutex_init(&pt1->lock);
  907. pt1->power = 0;
  908. pt1->reset = 1;
  909. pt1_update_power(pt1);
  910. i2c_adap = &pt1->i2c_adap;
  911. i2c_adap->algo = &pt1_i2c_algo;
  912. i2c_adap->algo_data = NULL;
  913. i2c_adap->dev.parent = &pdev->dev;
  914. i2c_set_adapdata(i2c_adap, pt1);
  915. ret = i2c_add_adapter(i2c_adap);
  916. if (ret < 0)
  917. goto err_pt1_cleanup_adapters;
  918. pt1_i2c_init(pt1);
  919. pt1_i2c_wait(pt1);
  920. ret = pt1_sync(pt1);
  921. if (ret < 0)
  922. goto err_i2c_del_adapter;
  923. pt1_identify(pt1);
  924. ret = pt1_unlock(pt1);
  925. if (ret < 0)
  926. goto err_i2c_del_adapter;
  927. ret = pt1_reset_pci(pt1);
  928. if (ret < 0)
  929. goto err_i2c_del_adapter;
  930. ret = pt1_reset_ram(pt1);
  931. if (ret < 0)
  932. goto err_i2c_del_adapter;
  933. ret = pt1_enable_ram(pt1);
  934. if (ret < 0)
  935. goto err_i2c_del_adapter;
  936. pt1_init_streams(pt1);
  937. pt1->power = 1;
  938. pt1_update_power(pt1);
  939. schedule_timeout_uninterruptible((HZ + 49) / 50);
  940. pt1->reset = 0;
  941. pt1_update_power(pt1);
  942. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  943. ret = pt1_init_frontends(pt1);
  944. if (ret < 0)
  945. goto err_pt1_disable_ram;
  946. ret = pt1_init_tables(pt1);
  947. if (ret < 0)
  948. goto err_pt1_cleanup_frontends;
  949. kthread = kthread_run(pt1_thread, pt1, "pt1");
  950. if (IS_ERR(kthread)) {
  951. ret = PTR_ERR(kthread);
  952. goto err_pt1_cleanup_tables;
  953. }
  954. pt1->kthread = kthread;
  955. return 0;
  956. err_pt1_cleanup_tables:
  957. pt1_cleanup_tables(pt1);
  958. err_pt1_cleanup_frontends:
  959. pt1_cleanup_frontends(pt1);
  960. err_pt1_disable_ram:
  961. pt1_disable_ram(pt1);
  962. pt1->power = 0;
  963. pt1->reset = 1;
  964. pt1_update_power(pt1);
  965. err_pt1_cleanup_adapters:
  966. pt1_cleanup_adapters(pt1);
  967. err_i2c_del_adapter:
  968. i2c_del_adapter(i2c_adap);
  969. err_kfree:
  970. pci_set_drvdata(pdev, NULL);
  971. kfree(pt1);
  972. err_pci_iounmap:
  973. pci_iounmap(pdev, regs);
  974. err_pci_release_regions:
  975. pci_release_regions(pdev);
  976. err_pci_disable_device:
  977. pci_disable_device(pdev);
  978. err:
  979. return ret;
  980. }
  981. static struct pci_device_id pt1_id_table[] = {
  982. { PCI_DEVICE(0x10ee, 0x211a) },
  983. { PCI_DEVICE(0x10ee, 0x222a) },
  984. { },
  985. };
  986. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  987. static struct pci_driver pt1_driver = {
  988. .name = DRIVER_NAME,
  989. .probe = pt1_probe,
  990. .remove = __devexit_p(pt1_remove),
  991. .id_table = pt1_id_table,
  992. };
  993. static int __init pt1_init(void)
  994. {
  995. return pci_register_driver(&pt1_driver);
  996. }
  997. static void __exit pt1_cleanup(void)
  998. {
  999. pci_unregister_driver(&pt1_driver);
  1000. }
  1001. module_init(pt1_init);
  1002. module_exit(pt1_cleanup);
  1003. MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
  1004. MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
  1005. MODULE_LICENSE("GPL");