mISDNisar.c 43 KB

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  1. /*
  2. * mISDNisar.c ISAR (Siemens PSB 7110) specific functions
  3. *
  4. * Author Karsten Keil (keil@isdn4linux.de)
  5. *
  6. * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. */
  22. /* define this to enable static debug messages, if you kernel supports
  23. * dynamic debugging, you should use debugfs for this
  24. */
  25. /* #define DEBUG */
  26. #include <linux/gfp.h>
  27. #include <linux/delay.h>
  28. #include <linux/vmalloc.h>
  29. #include <linux/mISDNhw.h>
  30. #include "isar.h"
  31. #define ISAR_REV "2.1"
  32. MODULE_AUTHOR("Karsten Keil");
  33. MODULE_LICENSE("GPL v2");
  34. MODULE_VERSION(ISAR_REV);
  35. #define DEBUG_HW_FIRMWARE_FIFO 0x10000
  36. static const u8 faxmodulation_s[] = "3,24,48,72,73,74,96,97,98,121,122,145,146";
  37. static const u8 faxmodulation[] = {3, 24, 48, 72, 73, 74, 96, 97, 98, 121,
  38. 122, 145, 146};
  39. #define FAXMODCNT 13
  40. static void isar_setup(struct isar_hw *);
  41. static inline int
  42. waitforHIA(struct isar_hw *isar, int timeout)
  43. {
  44. int t = timeout;
  45. u8 val = isar->read_reg(isar->hw, ISAR_HIA);
  46. while ((val & 1) && t) {
  47. udelay(1);
  48. t--;
  49. val = isar->read_reg(isar->hw, ISAR_HIA);
  50. }
  51. pr_debug("%s: HIA after %dus\n", isar->name, timeout - t);
  52. return timeout;
  53. }
  54. /*
  55. * send msg to ISAR mailbox
  56. * if msg is NULL use isar->buf
  57. */
  58. static int
  59. send_mbox(struct isar_hw *isar, u8 his, u8 creg, u8 len, u8 *msg)
  60. {
  61. if (!waitforHIA(isar, 1000))
  62. return 0;
  63. pr_debug("send_mbox(%02x,%02x,%d)\n", his, creg, len);
  64. isar->write_reg(isar->hw, ISAR_CTRL_H, creg);
  65. isar->write_reg(isar->hw, ISAR_CTRL_L, len);
  66. isar->write_reg(isar->hw, ISAR_WADR, 0);
  67. if (!msg)
  68. msg = isar->buf;
  69. if (msg && len) {
  70. isar->write_fifo(isar->hw, ISAR_MBOX, msg, len);
  71. if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) {
  72. int l = 0;
  73. while (l < (int)len) {
  74. hex_dump_to_buffer(msg + l, len - l, 32, 1,
  75. isar->log, 256, 1);
  76. pr_debug("%s: %s %02x: %s\n", isar->name,
  77. __func__, l, isar->log);
  78. l += 32;
  79. }
  80. }
  81. }
  82. isar->write_reg(isar->hw, ISAR_HIS, his);
  83. waitforHIA(isar, 1000);
  84. return 1;
  85. }
  86. /*
  87. * receive message from ISAR mailbox
  88. * if msg is NULL use isar->buf
  89. */
  90. static void
  91. rcv_mbox(struct isar_hw *isar, u8 *msg)
  92. {
  93. if (!msg)
  94. msg = isar->buf;
  95. isar->write_reg(isar->hw, ISAR_RADR, 0);
  96. if (msg && isar->clsb) {
  97. isar->read_fifo(isar->hw, ISAR_MBOX, msg, isar->clsb);
  98. if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) {
  99. int l = 0;
  100. while (l < (int)isar->clsb) {
  101. hex_dump_to_buffer(msg + l, isar->clsb - l, 32,
  102. 1, isar->log, 256, 1);
  103. pr_debug("%s: %s %02x: %s\n", isar->name,
  104. __func__, l, isar->log);
  105. l += 32;
  106. }
  107. }
  108. }
  109. isar->write_reg(isar->hw, ISAR_IIA, 0);
  110. }
  111. static inline void
  112. get_irq_infos(struct isar_hw *isar)
  113. {
  114. isar->iis = isar->read_reg(isar->hw, ISAR_IIS);
  115. isar->cmsb = isar->read_reg(isar->hw, ISAR_CTRL_H);
  116. isar->clsb = isar->read_reg(isar->hw, ISAR_CTRL_L);
  117. pr_debug("%s: rcv_mbox(%02x,%02x,%d)\n", isar->name,
  118. isar->iis, isar->cmsb, isar->clsb);
  119. }
  120. /*
  121. * poll answer message from ISAR mailbox
  122. * should be used only with ISAR IRQs disabled before DSP was started
  123. *
  124. */
  125. static int
  126. poll_mbox(struct isar_hw *isar, int maxdelay)
  127. {
  128. int t = maxdelay;
  129. u8 irq;
  130. irq = isar->read_reg(isar->hw, ISAR_IRQBIT);
  131. while (t && !(irq & ISAR_IRQSTA)) {
  132. udelay(1);
  133. t--;
  134. }
  135. if (t) {
  136. get_irq_infos(isar);
  137. rcv_mbox(isar, NULL);
  138. }
  139. pr_debug("%s: pulled %d bytes after %d us\n",
  140. isar->name, isar->clsb, maxdelay - t);
  141. return t;
  142. }
  143. static int
  144. ISARVersion(struct isar_hw *isar)
  145. {
  146. int ver;
  147. /* disable ISAR IRQ */
  148. isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
  149. isar->buf[0] = ISAR_MSG_HWVER;
  150. isar->buf[1] = 0;
  151. isar->buf[2] = 1;
  152. if (!send_mbox(isar, ISAR_HIS_VNR, 0, 3, NULL))
  153. return -1;
  154. if (!poll_mbox(isar, 1000))
  155. return -2;
  156. if (isar->iis == ISAR_IIS_VNR) {
  157. if (isar->clsb == 1) {
  158. ver = isar->buf[0] & 0xf;
  159. return ver;
  160. }
  161. return -3;
  162. }
  163. return -4;
  164. }
  165. static int
  166. load_firmware(struct isar_hw *isar, const u8 *buf, int size)
  167. {
  168. u32 saved_debug = isar->ch[0].bch.debug;
  169. int ret, cnt;
  170. u8 nom, noc;
  171. u16 left, val, *sp = (u16 *)buf;
  172. u8 *mp;
  173. u_long flags;
  174. struct {
  175. u16 sadr;
  176. u16 len;
  177. u16 d_key;
  178. } blk_head;
  179. if (1 != isar->version) {
  180. pr_err("%s: ISAR wrong version %d firmware download aborted\n",
  181. isar->name, isar->version);
  182. return -EINVAL;
  183. }
  184. if (!(saved_debug & DEBUG_HW_FIRMWARE_FIFO))
  185. isar->ch[0].bch.debug &= ~DEBUG_HW_BFIFO;
  186. pr_debug("%s: load firmware %d words (%d bytes)\n",
  187. isar->name, size/2, size);
  188. cnt = 0;
  189. size /= 2;
  190. /* disable ISAR IRQ */
  191. spin_lock_irqsave(isar->hwlock, flags);
  192. isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
  193. spin_unlock_irqrestore(isar->hwlock, flags);
  194. while (cnt < size) {
  195. blk_head.sadr = le16_to_cpu(*sp++);
  196. blk_head.len = le16_to_cpu(*sp++);
  197. blk_head.d_key = le16_to_cpu(*sp++);
  198. cnt += 3;
  199. pr_debug("ISAR firmware block (%#x,%d,%#x)\n",
  200. blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
  201. left = blk_head.len;
  202. if (cnt + left > size) {
  203. pr_info("%s: firmware error have %d need %d words\n",
  204. isar->name, size, cnt + left);
  205. ret = -EINVAL;
  206. goto reterrflg;
  207. }
  208. spin_lock_irqsave(isar->hwlock, flags);
  209. if (!send_mbox(isar, ISAR_HIS_DKEY, blk_head.d_key & 0xff,
  210. 0, NULL)) {
  211. pr_info("ISAR send_mbox dkey failed\n");
  212. ret = -ETIME;
  213. goto reterror;
  214. }
  215. if (!poll_mbox(isar, 1000)) {
  216. pr_warning("ISAR poll_mbox dkey failed\n");
  217. ret = -ETIME;
  218. goto reterror;
  219. }
  220. spin_unlock_irqrestore(isar->hwlock, flags);
  221. if ((isar->iis != ISAR_IIS_DKEY) || isar->cmsb || isar->clsb) {
  222. pr_info("ISAR wrong dkey response (%x,%x,%x)\n",
  223. isar->iis, isar->cmsb, isar->clsb);
  224. ret = 1;
  225. goto reterrflg;
  226. }
  227. while (left > 0) {
  228. if (left > 126)
  229. noc = 126;
  230. else
  231. noc = left;
  232. nom = (2 * noc) + 3;
  233. mp = isar->buf;
  234. /* the ISAR is big endian */
  235. *mp++ = blk_head.sadr >> 8;
  236. *mp++ = blk_head.sadr & 0xFF;
  237. left -= noc;
  238. cnt += noc;
  239. *mp++ = noc;
  240. pr_debug("%s: load %3d words at %04x\n", isar->name,
  241. noc, blk_head.sadr);
  242. blk_head.sadr += noc;
  243. while (noc) {
  244. val = le16_to_cpu(*sp++);
  245. *mp++ = val >> 8;
  246. *mp++ = val & 0xFF;
  247. noc--;
  248. }
  249. spin_lock_irqsave(isar->hwlock, flags);
  250. if (!send_mbox(isar, ISAR_HIS_FIRM, 0, nom, NULL)) {
  251. pr_info("ISAR send_mbox prog failed\n");
  252. ret = -ETIME;
  253. goto reterror;
  254. }
  255. if (!poll_mbox(isar, 1000)) {
  256. pr_info("ISAR poll_mbox prog failed\n");
  257. ret = -ETIME;
  258. goto reterror;
  259. }
  260. spin_unlock_irqrestore(isar->hwlock, flags);
  261. if ((isar->iis != ISAR_IIS_FIRM) ||
  262. isar->cmsb || isar->clsb) {
  263. pr_info("ISAR wrong prog response (%x,%x,%x)\n",
  264. isar->iis, isar->cmsb, isar->clsb);
  265. ret = -EIO;
  266. goto reterrflg;
  267. }
  268. }
  269. pr_debug("%s: ISAR firmware block %d words loaded\n",
  270. isar->name, blk_head.len);
  271. }
  272. isar->ch[0].bch.debug = saved_debug;
  273. /* 10ms delay */
  274. cnt = 10;
  275. while (cnt--)
  276. mdelay(1);
  277. isar->buf[0] = 0xff;
  278. isar->buf[1] = 0xfe;
  279. isar->bstat = 0;
  280. spin_lock_irqsave(isar->hwlock, flags);
  281. if (!send_mbox(isar, ISAR_HIS_STDSP, 0, 2, NULL)) {
  282. pr_info("ISAR send_mbox start dsp failed\n");
  283. ret = -ETIME;
  284. goto reterror;
  285. }
  286. if (!poll_mbox(isar, 1000)) {
  287. pr_info("ISAR poll_mbox start dsp failed\n");
  288. ret = -ETIME;
  289. goto reterror;
  290. }
  291. if ((isar->iis != ISAR_IIS_STDSP) || isar->cmsb || isar->clsb) {
  292. pr_info("ISAR wrong start dsp response (%x,%x,%x)\n",
  293. isar->iis, isar->cmsb, isar->clsb);
  294. ret = -EIO;
  295. goto reterror;
  296. } else
  297. pr_debug("%s: ISAR start dsp success\n", isar->name);
  298. /* NORMAL mode entered */
  299. /* Enable IRQs of ISAR */
  300. isar->write_reg(isar->hw, ISAR_IRQBIT, ISAR_IRQSTA);
  301. spin_unlock_irqrestore(isar->hwlock, flags);
  302. cnt = 1000; /* max 1s */
  303. while ((!isar->bstat) && cnt) {
  304. mdelay(1);
  305. cnt--;
  306. }
  307. if (!cnt) {
  308. pr_info("ISAR no general status event received\n");
  309. ret = -ETIME;
  310. goto reterrflg;
  311. } else
  312. pr_debug("%s: ISAR general status event %x\n",
  313. isar->name, isar->bstat);
  314. /* 10ms delay */
  315. cnt = 10;
  316. while (cnt--)
  317. mdelay(1);
  318. isar->iis = 0;
  319. spin_lock_irqsave(isar->hwlock, flags);
  320. if (!send_mbox(isar, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
  321. pr_info("ISAR send_mbox self tst failed\n");
  322. ret = -ETIME;
  323. goto reterror;
  324. }
  325. spin_unlock_irqrestore(isar->hwlock, flags);
  326. cnt = 10000; /* max 100 ms */
  327. while ((isar->iis != ISAR_IIS_DIAG) && cnt) {
  328. udelay(10);
  329. cnt--;
  330. }
  331. mdelay(1);
  332. if (!cnt) {
  333. pr_info("ISAR no self tst response\n");
  334. ret = -ETIME;
  335. goto reterrflg;
  336. }
  337. if ((isar->cmsb == ISAR_CTRL_STST) && (isar->clsb == 1)
  338. && (isar->buf[0] == 0))
  339. pr_debug("%s: ISAR selftest OK\n", isar->name);
  340. else {
  341. pr_info("ISAR selftest not OK %x/%x/%x\n",
  342. isar->cmsb, isar->clsb, isar->buf[0]);
  343. ret = -EIO;
  344. goto reterrflg;
  345. }
  346. spin_lock_irqsave(isar->hwlock, flags);
  347. isar->iis = 0;
  348. if (!send_mbox(isar, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
  349. pr_info("ISAR RQST SVN failed\n");
  350. ret = -ETIME;
  351. goto reterror;
  352. }
  353. spin_unlock_irqrestore(isar->hwlock, flags);
  354. cnt = 30000; /* max 300 ms */
  355. while ((isar->iis != ISAR_IIS_DIAG) && cnt) {
  356. udelay(10);
  357. cnt--;
  358. }
  359. mdelay(1);
  360. if (!cnt) {
  361. pr_info("ISAR no SVN response\n");
  362. ret = -ETIME;
  363. goto reterrflg;
  364. } else {
  365. if ((isar->cmsb == ISAR_CTRL_SWVER) && (isar->clsb == 1)) {
  366. pr_notice("%s: ISAR software version %#x\n",
  367. isar->name, isar->buf[0]);
  368. } else {
  369. pr_info("%s: ISAR wrong swver response (%x,%x)"
  370. " cnt(%d)\n", isar->name, isar->cmsb,
  371. isar->clsb, cnt);
  372. ret = -EIO;
  373. goto reterrflg;
  374. }
  375. }
  376. spin_lock_irqsave(isar->hwlock, flags);
  377. isar_setup(isar);
  378. spin_unlock_irqrestore(isar->hwlock, flags);
  379. ret = 0;
  380. reterrflg:
  381. spin_lock_irqsave(isar->hwlock, flags);
  382. reterror:
  383. isar->ch[0].bch.debug = saved_debug;
  384. if (ret)
  385. /* disable ISAR IRQ */
  386. isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
  387. spin_unlock_irqrestore(isar->hwlock, flags);
  388. return ret;
  389. }
  390. static inline void
  391. deliver_status(struct isar_ch *ch, int status)
  392. {
  393. pr_debug("%s: HL->LL FAXIND %x\n", ch->is->name, status);
  394. _queue_data(&ch->bch.ch, PH_CONTROL_IND, status, 0, NULL, GFP_ATOMIC);
  395. }
  396. static inline void
  397. isar_rcv_frame(struct isar_ch *ch)
  398. {
  399. u8 *ptr;
  400. if (!ch->is->clsb) {
  401. pr_debug("%s; ISAR zero len frame\n", ch->is->name);
  402. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  403. return;
  404. }
  405. switch (ch->bch.state) {
  406. case ISDN_P_NONE:
  407. pr_debug("%s: ISAR protocol 0 spurious IIS_RDATA %x/%x/%x\n",
  408. ch->is->name, ch->is->iis, ch->is->cmsb, ch->is->clsb);
  409. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  410. break;
  411. case ISDN_P_B_RAW:
  412. case ISDN_P_B_L2DTMF:
  413. case ISDN_P_B_MODEM_ASYNC:
  414. if (!ch->bch.rx_skb) {
  415. ch->bch.rx_skb = mI_alloc_skb(ch->bch.maxlen,
  416. GFP_ATOMIC);
  417. if (unlikely(!ch->bch.rx_skb)) {
  418. pr_info("%s: B receive out of memory\n",
  419. ch->is->name);
  420. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  421. break;
  422. }
  423. }
  424. rcv_mbox(ch->is, skb_put(ch->bch.rx_skb, ch->is->clsb));
  425. recv_Bchannel(&ch->bch, 0);
  426. break;
  427. case ISDN_P_B_HDLC:
  428. if (!ch->bch.rx_skb) {
  429. ch->bch.rx_skb = mI_alloc_skb(ch->bch.maxlen,
  430. GFP_ATOMIC);
  431. if (unlikely(!ch->bch.rx_skb)) {
  432. pr_info("%s: B receive out of memory\n",
  433. ch->is->name);
  434. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  435. break;
  436. }
  437. }
  438. if ((ch->bch.rx_skb->len + ch->is->clsb) >
  439. (ch->bch.maxlen + 2)) {
  440. pr_debug("%s: incoming packet too large\n",
  441. ch->is->name);
  442. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  443. skb_trim(ch->bch.rx_skb, 0);
  444. break;
  445. }
  446. if (ch->is->cmsb & HDLC_ERROR) {
  447. pr_debug("%s: ISAR frame error %x len %d\n",
  448. ch->is->name, ch->is->cmsb, ch->is->clsb);
  449. #ifdef ERROR_STATISTIC
  450. if (ch->is->cmsb & HDLC_ERR_RER)
  451. ch->bch.err_inv++;
  452. if (ch->is->cmsb & HDLC_ERR_CER)
  453. ch->bch.err_crc++;
  454. #endif
  455. skb_trim(ch->bch.rx_skb, 0);
  456. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  457. break;
  458. }
  459. if (ch->is->cmsb & HDLC_FSD)
  460. skb_trim(ch->bch.rx_skb, 0);
  461. ptr = skb_put(ch->bch.rx_skb, ch->is->clsb);
  462. rcv_mbox(ch->is, ptr);
  463. if (ch->is->cmsb & HDLC_FED) {
  464. if (ch->bch.rx_skb->len < 3) { /* last 2 are the FCS */
  465. pr_debug("%s: ISAR frame to short %d\n",
  466. ch->is->name, ch->bch.rx_skb->len);
  467. skb_trim(ch->bch.rx_skb, 0);
  468. break;
  469. }
  470. skb_trim(ch->bch.rx_skb, ch->bch.rx_skb->len - 2);
  471. recv_Bchannel(&ch->bch, 0);
  472. }
  473. break;
  474. case ISDN_P_B_T30_FAX:
  475. if (ch->state != STFAX_ACTIV) {
  476. pr_debug("%s: isar_rcv_frame: not ACTIV\n",
  477. ch->is->name);
  478. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  479. if (ch->bch.rx_skb)
  480. skb_trim(ch->bch.rx_skb, 0);
  481. break;
  482. }
  483. if (!ch->bch.rx_skb) {
  484. ch->bch.rx_skb = mI_alloc_skb(ch->bch.maxlen,
  485. GFP_ATOMIC);
  486. if (unlikely(!ch->bch.rx_skb)) {
  487. pr_info("%s: B receive out of memory\n",
  488. __func__);
  489. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  490. break;
  491. }
  492. }
  493. if (ch->cmd == PCTRL_CMD_FRM) {
  494. rcv_mbox(ch->is, skb_put(ch->bch.rx_skb, ch->is->clsb));
  495. pr_debug("%s: isar_rcv_frame: %d\n",
  496. ch->is->name, ch->bch.rx_skb->len);
  497. if (ch->is->cmsb & SART_NMD) { /* ABORT */
  498. pr_debug("%s: isar_rcv_frame: no more data\n",
  499. ch->is->name);
  500. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  501. send_mbox(ch->is, SET_DPS(ch->dpath) |
  502. ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
  503. 0, NULL);
  504. ch->state = STFAX_ESCAPE;
  505. /* set_skb_flag(skb, DF_NOMOREDATA); */
  506. }
  507. recv_Bchannel(&ch->bch, 0);
  508. if (ch->is->cmsb & SART_NMD)
  509. deliver_status(ch, HW_MOD_NOCARR);
  510. break;
  511. }
  512. if (ch->cmd != PCTRL_CMD_FRH) {
  513. pr_debug("%s: isar_rcv_frame: unknown fax mode %x\n",
  514. ch->is->name, ch->cmd);
  515. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  516. if (ch->bch.rx_skb)
  517. skb_trim(ch->bch.rx_skb, 0);
  518. break;
  519. }
  520. /* PCTRL_CMD_FRH */
  521. if ((ch->bch.rx_skb->len + ch->is->clsb) >
  522. (ch->bch.maxlen + 2)) {
  523. pr_info("%s: %s incoming packet too large\n",
  524. ch->is->name, __func__);
  525. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  526. skb_trim(ch->bch.rx_skb, 0);
  527. break;
  528. } else if (ch->is->cmsb & HDLC_ERROR) {
  529. pr_info("%s: ISAR frame error %x len %d\n",
  530. ch->is->name, ch->is->cmsb, ch->is->clsb);
  531. skb_trim(ch->bch.rx_skb, 0);
  532. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  533. break;
  534. }
  535. if (ch->is->cmsb & HDLC_FSD)
  536. skb_trim(ch->bch.rx_skb, 0);
  537. ptr = skb_put(ch->bch.rx_skb, ch->is->clsb);
  538. rcv_mbox(ch->is, ptr);
  539. if (ch->is->cmsb & HDLC_FED) {
  540. if (ch->bch.rx_skb->len < 3) { /* last 2 are the FCS */
  541. pr_info("%s: ISAR frame to short %d\n",
  542. ch->is->name, ch->bch.rx_skb->len);
  543. skb_trim(ch->bch.rx_skb, 0);
  544. break;
  545. }
  546. skb_trim(ch->bch.rx_skb, ch->bch.rx_skb->len - 2);
  547. recv_Bchannel(&ch->bch, 0);
  548. }
  549. if (ch->is->cmsb & SART_NMD) { /* ABORT */
  550. pr_debug("%s: isar_rcv_frame: no more data\n",
  551. ch->is->name);
  552. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  553. if (ch->bch.rx_skb)
  554. skb_trim(ch->bch.rx_skb, 0);
  555. send_mbox(ch->is, SET_DPS(ch->dpath) |
  556. ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
  557. ch->state = STFAX_ESCAPE;
  558. deliver_status(ch, HW_MOD_NOCARR);
  559. }
  560. break;
  561. default:
  562. pr_info("isar_rcv_frame protocol (%x)error\n", ch->bch.state);
  563. ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
  564. break;
  565. }
  566. }
  567. static void
  568. isar_fill_fifo(struct isar_ch *ch)
  569. {
  570. int count;
  571. u8 msb;
  572. u8 *ptr;
  573. pr_debug("%s: ch%d tx_skb %p tx_idx %d\n",
  574. ch->is->name, ch->bch.nr, ch->bch.tx_skb, ch->bch.tx_idx);
  575. if (!ch->bch.tx_skb)
  576. return;
  577. count = ch->bch.tx_skb->len - ch->bch.tx_idx;
  578. if (count <= 0)
  579. return;
  580. if (!(ch->is->bstat &
  581. (ch->dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
  582. return;
  583. if (count > ch->mml) {
  584. msb = 0;
  585. count = ch->mml;
  586. } else {
  587. msb = HDLC_FED;
  588. }
  589. ptr = ch->bch.tx_skb->data + ch->bch.tx_idx;
  590. if (!ch->bch.tx_idx) {
  591. pr_debug("%s: frame start\n", ch->is->name);
  592. if ((ch->bch.state == ISDN_P_B_T30_FAX) &&
  593. (ch->cmd == PCTRL_CMD_FTH)) {
  594. if (count > 1) {
  595. if ((ptr[0] == 0xff) && (ptr[1] == 0x13)) {
  596. /* last frame */
  597. test_and_set_bit(FLG_LASTDATA,
  598. &ch->bch.Flags);
  599. pr_debug("%s: set LASTDATA\n",
  600. ch->is->name);
  601. if (msb == HDLC_FED)
  602. test_and_set_bit(FLG_DLEETX,
  603. &ch->bch.Flags);
  604. }
  605. }
  606. }
  607. msb |= HDLC_FST;
  608. }
  609. ch->bch.tx_idx += count;
  610. switch (ch->bch.state) {
  611. case ISDN_P_NONE:
  612. pr_info("%s: wrong protocol 0\n", __func__);
  613. break;
  614. case ISDN_P_B_RAW:
  615. case ISDN_P_B_L2DTMF:
  616. case ISDN_P_B_MODEM_ASYNC:
  617. send_mbox(ch->is, SET_DPS(ch->dpath) | ISAR_HIS_SDATA,
  618. 0, count, ptr);
  619. break;
  620. case ISDN_P_B_HDLC:
  621. send_mbox(ch->is, SET_DPS(ch->dpath) | ISAR_HIS_SDATA,
  622. msb, count, ptr);
  623. break;
  624. case ISDN_P_B_T30_FAX:
  625. if (ch->state != STFAX_ACTIV)
  626. pr_debug("%s: not ACTIV\n", ch->is->name);
  627. else if (ch->cmd == PCTRL_CMD_FTH)
  628. send_mbox(ch->is, SET_DPS(ch->dpath) | ISAR_HIS_SDATA,
  629. msb, count, ptr);
  630. else if (ch->cmd == PCTRL_CMD_FTM)
  631. send_mbox(ch->is, SET_DPS(ch->dpath) | ISAR_HIS_SDATA,
  632. 0, count, ptr);
  633. else
  634. pr_debug("%s: not FTH/FTM\n", ch->is->name);
  635. break;
  636. default:
  637. pr_info("%s: protocol(%x) error\n",
  638. __func__, ch->bch.state);
  639. break;
  640. }
  641. }
  642. static inline struct isar_ch *
  643. sel_bch_isar(struct isar_hw *isar, u8 dpath)
  644. {
  645. struct isar_ch *base = &isar->ch[0];
  646. if ((!dpath) || (dpath > 2))
  647. return NULL;
  648. if (base->dpath == dpath)
  649. return base;
  650. base++;
  651. if (base->dpath == dpath)
  652. return base;
  653. return NULL;
  654. }
  655. static void
  656. send_next(struct isar_ch *ch)
  657. {
  658. pr_debug("%s: %s ch%d tx_skb %p tx_idx %d\n",
  659. ch->is->name, __func__, ch->bch.nr,
  660. ch->bch.tx_skb, ch->bch.tx_idx);
  661. if (ch->bch.state == ISDN_P_B_T30_FAX) {
  662. if (ch->cmd == PCTRL_CMD_FTH) {
  663. if (test_bit(FLG_LASTDATA, &ch->bch.Flags)) {
  664. pr_debug("set NMD_DATA\n");
  665. test_and_set_bit(FLG_NMD_DATA, &ch->bch.Flags);
  666. }
  667. } else if (ch->cmd == PCTRL_CMD_FTM) {
  668. if (test_bit(FLG_DLEETX, &ch->bch.Flags)) {
  669. test_and_set_bit(FLG_LASTDATA, &ch->bch.Flags);
  670. test_and_set_bit(FLG_NMD_DATA, &ch->bch.Flags);
  671. }
  672. }
  673. }
  674. if (ch->bch.tx_skb) {
  675. /* send confirm, on trans, free on hdlc. */
  676. if (test_bit(FLG_TRANSPARENT, &ch->bch.Flags))
  677. confirm_Bsend(&ch->bch);
  678. dev_kfree_skb(ch->bch.tx_skb);
  679. }
  680. if (get_next_bframe(&ch->bch))
  681. isar_fill_fifo(ch);
  682. else {
  683. if (test_and_clear_bit(FLG_DLEETX, &ch->bch.Flags)) {
  684. if (test_and_clear_bit(FLG_LASTDATA,
  685. &ch->bch.Flags)) {
  686. if (test_and_clear_bit(FLG_NMD_DATA,
  687. &ch->bch.Flags)) {
  688. u8 zd = 0;
  689. send_mbox(ch->is, SET_DPS(ch->dpath) |
  690. ISAR_HIS_SDATA, 0x01, 1, &zd);
  691. }
  692. test_and_set_bit(FLG_LL_OK, &ch->bch.Flags);
  693. } else {
  694. deliver_status(ch, HW_MOD_CONNECT);
  695. }
  696. }
  697. }
  698. }
  699. static void
  700. check_send(struct isar_hw *isar, u8 rdm)
  701. {
  702. struct isar_ch *ch;
  703. pr_debug("%s: rdm %x\n", isar->name, rdm);
  704. if (rdm & BSTAT_RDM1) {
  705. ch = sel_bch_isar(isar, 1);
  706. if (ch && test_bit(FLG_ACTIVE, &ch->bch.Flags)) {
  707. if (ch->bch.tx_skb && (ch->bch.tx_skb->len >
  708. ch->bch.tx_idx))
  709. isar_fill_fifo(ch);
  710. else
  711. send_next(ch);
  712. }
  713. }
  714. if (rdm & BSTAT_RDM2) {
  715. ch = sel_bch_isar(isar, 2);
  716. if (ch && test_bit(FLG_ACTIVE, &ch->bch.Flags)) {
  717. if (ch->bch.tx_skb && (ch->bch.tx_skb->len >
  718. ch->bch.tx_idx))
  719. isar_fill_fifo(ch);
  720. else
  721. send_next(ch);
  722. }
  723. }
  724. }
  725. const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200", "NODEF4",
  726. "300", "600", "1200", "2400", "4800", "7200",
  727. "9600nt", "9600t", "12000", "14400", "WRONG"};
  728. const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
  729. "Bell103", "V23", "Bell202", "V17", "V29", "V27ter"};
  730. static void
  731. isar_pump_status_rsp(struct isar_ch *ch) {
  732. u8 ril = ch->is->buf[0];
  733. u8 rim;
  734. if (!test_and_clear_bit(ISAR_RATE_REQ, &ch->is->Flags))
  735. return;
  736. if (ril > 14) {
  737. pr_info("%s: wrong pstrsp ril=%d\n", ch->is->name, ril);
  738. ril = 15;
  739. }
  740. switch (ch->is->buf[1]) {
  741. case 0:
  742. rim = 0;
  743. break;
  744. case 0x20:
  745. rim = 2;
  746. break;
  747. case 0x40:
  748. rim = 3;
  749. break;
  750. case 0x41:
  751. rim = 4;
  752. break;
  753. case 0x51:
  754. rim = 5;
  755. break;
  756. case 0x61:
  757. rim = 6;
  758. break;
  759. case 0x71:
  760. rim = 7;
  761. break;
  762. case 0x82:
  763. rim = 8;
  764. break;
  765. case 0x92:
  766. rim = 9;
  767. break;
  768. case 0xa2:
  769. rim = 10;
  770. break;
  771. default:
  772. rim = 1;
  773. break;
  774. }
  775. sprintf(ch->conmsg, "%s %s", dmril[ril], dmrim[rim]);
  776. pr_debug("%s: pump strsp %s\n", ch->is->name, ch->conmsg);
  777. }
  778. static void
  779. isar_pump_statev_modem(struct isar_ch *ch, u8 devt) {
  780. u8 dps = SET_DPS(ch->dpath);
  781. switch (devt) {
  782. case PSEV_10MS_TIMER:
  783. pr_debug("%s: pump stev TIMER\n", ch->is->name);
  784. break;
  785. case PSEV_CON_ON:
  786. pr_debug("%s: pump stev CONNECT\n", ch->is->name);
  787. deliver_status(ch, HW_MOD_CONNECT);
  788. break;
  789. case PSEV_CON_OFF:
  790. pr_debug("%s: pump stev NO CONNECT\n", ch->is->name);
  791. send_mbox(ch->is, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  792. deliver_status(ch, HW_MOD_NOCARR);
  793. break;
  794. case PSEV_V24_OFF:
  795. pr_debug("%s: pump stev V24 OFF\n", ch->is->name);
  796. break;
  797. case PSEV_CTS_ON:
  798. pr_debug("%s: pump stev CTS ON\n", ch->is->name);
  799. break;
  800. case PSEV_CTS_OFF:
  801. pr_debug("%s pump stev CTS OFF\n", ch->is->name);
  802. break;
  803. case PSEV_DCD_ON:
  804. pr_debug("%s: pump stev CARRIER ON\n", ch->is->name);
  805. test_and_set_bit(ISAR_RATE_REQ, &ch->is->Flags);
  806. send_mbox(ch->is, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  807. break;
  808. case PSEV_DCD_OFF:
  809. pr_debug("%s: pump stev CARRIER OFF\n", ch->is->name);
  810. break;
  811. case PSEV_DSR_ON:
  812. pr_debug("%s: pump stev DSR ON\n", ch->is->name);
  813. break;
  814. case PSEV_DSR_OFF:
  815. pr_debug("%s: pump stev DSR_OFF\n", ch->is->name);
  816. break;
  817. case PSEV_REM_RET:
  818. pr_debug("%s: pump stev REMOTE RETRAIN\n", ch->is->name);
  819. break;
  820. case PSEV_REM_REN:
  821. pr_debug("%s: pump stev REMOTE RENEGOTIATE\n", ch->is->name);
  822. break;
  823. case PSEV_GSTN_CLR:
  824. pr_debug("%s: pump stev GSTN CLEAR\n", ch->is->name);
  825. break;
  826. default:
  827. pr_info("u%s: unknown pump stev %x\n", ch->is->name, devt);
  828. break;
  829. }
  830. }
  831. static void
  832. isar_pump_statev_fax(struct isar_ch *ch, u8 devt) {
  833. u8 dps = SET_DPS(ch->dpath);
  834. u8 p1;
  835. switch (devt) {
  836. case PSEV_10MS_TIMER:
  837. pr_debug("%s: pump stev TIMER\n", ch->is->name);
  838. break;
  839. case PSEV_RSP_READY:
  840. pr_debug("%s: pump stev RSP_READY\n", ch->is->name);
  841. ch->state = STFAX_READY;
  842. deliver_status(ch, HW_MOD_READY);
  843. #ifdef AUTOCON
  844. if (test_bit(BC_FLG_ORIG, &ch->bch.Flags))
  845. isar_pump_cmd(bch, HW_MOD_FRH, 3);
  846. else
  847. isar_pump_cmd(bch, HW_MOD_FTH, 3);
  848. #endif
  849. break;
  850. case PSEV_LINE_TX_H:
  851. if (ch->state == STFAX_LINE) {
  852. pr_debug("%s: pump stev LINE_TX_H\n", ch->is->name);
  853. ch->state = STFAX_CONT;
  854. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
  855. PCTRL_CMD_CONT, 0, NULL);
  856. } else {
  857. pr_debug("%s: pump stev LINE_TX_H wrong st %x\n",
  858. ch->is->name, ch->state);
  859. }
  860. break;
  861. case PSEV_LINE_RX_H:
  862. if (ch->state == STFAX_LINE) {
  863. pr_debug("%s: pump stev LINE_RX_H\n", ch->is->name);
  864. ch->state = STFAX_CONT;
  865. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
  866. PCTRL_CMD_CONT, 0, NULL);
  867. } else {
  868. pr_debug("%s: pump stev LINE_RX_H wrong st %x\n",
  869. ch->is->name, ch->state);
  870. }
  871. break;
  872. case PSEV_LINE_TX_B:
  873. if (ch->state == STFAX_LINE) {
  874. pr_debug("%s: pump stev LINE_TX_B\n", ch->is->name);
  875. ch->state = STFAX_CONT;
  876. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
  877. PCTRL_CMD_CONT, 0, NULL);
  878. } else {
  879. pr_debug("%s: pump stev LINE_TX_B wrong st %x\n",
  880. ch->is->name, ch->state);
  881. }
  882. break;
  883. case PSEV_LINE_RX_B:
  884. if (ch->state == STFAX_LINE) {
  885. pr_debug("%s: pump stev LINE_RX_B\n", ch->is->name);
  886. ch->state = STFAX_CONT;
  887. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
  888. PCTRL_CMD_CONT, 0, NULL);
  889. } else {
  890. pr_debug("%s: pump stev LINE_RX_B wrong st %x\n",
  891. ch->is->name, ch->state);
  892. }
  893. break;
  894. case PSEV_RSP_CONN:
  895. if (ch->state == STFAX_CONT) {
  896. pr_debug("%s: pump stev RSP_CONN\n", ch->is->name);
  897. ch->state = STFAX_ACTIV;
  898. test_and_set_bit(ISAR_RATE_REQ, &ch->is->Flags);
  899. send_mbox(ch->is, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  900. if (ch->cmd == PCTRL_CMD_FTH) {
  901. int delay = (ch->mod == 3) ? 1000 : 200;
  902. /* 1s (200 ms) Flags before data */
  903. if (test_and_set_bit(FLG_FTI_RUN,
  904. &ch->bch.Flags))
  905. del_timer(&ch->ftimer);
  906. ch->ftimer.expires =
  907. jiffies + ((delay * HZ)/1000);
  908. test_and_set_bit(FLG_LL_CONN,
  909. &ch->bch.Flags);
  910. add_timer(&ch->ftimer);
  911. } else {
  912. deliver_status(ch, HW_MOD_CONNECT);
  913. }
  914. } else {
  915. pr_debug("%s: pump stev RSP_CONN wrong st %x\n",
  916. ch->is->name, ch->state);
  917. }
  918. break;
  919. case PSEV_FLAGS_DET:
  920. pr_debug("%s: pump stev FLAGS_DET\n", ch->is->name);
  921. break;
  922. case PSEV_RSP_DISC:
  923. pr_debug("%s: pump stev RSP_DISC state(%d)\n",
  924. ch->is->name, ch->state);
  925. if (ch->state == STFAX_ESCAPE) {
  926. p1 = 5;
  927. switch (ch->newcmd) {
  928. case 0:
  929. ch->state = STFAX_READY;
  930. break;
  931. case PCTRL_CMD_FTM:
  932. p1 = 2;
  933. case PCTRL_CMD_FTH:
  934. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
  935. PCTRL_CMD_SILON, 1, &p1);
  936. ch->state = STFAX_SILDET;
  937. break;
  938. case PCTRL_CMD_FRH:
  939. case PCTRL_CMD_FRM:
  940. ch->mod = ch->newmod;
  941. p1 = ch->newmod;
  942. ch->newmod = 0;
  943. ch->cmd = ch->newcmd;
  944. ch->newcmd = 0;
  945. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
  946. ch->cmd, 1, &p1);
  947. ch->state = STFAX_LINE;
  948. ch->try_mod = 3;
  949. break;
  950. default:
  951. pr_debug("%s: RSP_DISC unknown newcmd %x\n",
  952. ch->is->name, ch->newcmd);
  953. break;
  954. }
  955. } else if (ch->state == STFAX_ACTIV) {
  956. if (test_and_clear_bit(FLG_LL_OK, &ch->bch.Flags))
  957. deliver_status(ch, HW_MOD_OK);
  958. else if (ch->cmd == PCTRL_CMD_FRM)
  959. deliver_status(ch, HW_MOD_NOCARR);
  960. else
  961. deliver_status(ch, HW_MOD_FCERROR);
  962. ch->state = STFAX_READY;
  963. } else if (ch->state != STFAX_SILDET) {
  964. /* ignore in STFAX_SILDET */
  965. ch->state = STFAX_READY;
  966. deliver_status(ch, HW_MOD_FCERROR);
  967. }
  968. break;
  969. case PSEV_RSP_SILDET:
  970. pr_debug("%s: pump stev RSP_SILDET\n", ch->is->name);
  971. if (ch->state == STFAX_SILDET) {
  972. ch->mod = ch->newmod;
  973. p1 = ch->newmod;
  974. ch->newmod = 0;
  975. ch->cmd = ch->newcmd;
  976. ch->newcmd = 0;
  977. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
  978. ch->cmd, 1, &p1);
  979. ch->state = STFAX_LINE;
  980. ch->try_mod = 3;
  981. }
  982. break;
  983. case PSEV_RSP_SILOFF:
  984. pr_debug("%s: pump stev RSP_SILOFF\n", ch->is->name);
  985. break;
  986. case PSEV_RSP_FCERR:
  987. if (ch->state == STFAX_LINE) {
  988. pr_debug("%s: pump stev RSP_FCERR try %d\n",
  989. ch->is->name, ch->try_mod);
  990. if (ch->try_mod--) {
  991. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
  992. ch->cmd, 1, &ch->mod);
  993. break;
  994. }
  995. }
  996. pr_debug("%s: pump stev RSP_FCERR\n", ch->is->name);
  997. ch->state = STFAX_ESCAPE;
  998. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
  999. 0, NULL);
  1000. deliver_status(ch, HW_MOD_FCERROR);
  1001. break;
  1002. default:
  1003. break;
  1004. }
  1005. }
  1006. void
  1007. mISDNisar_irq(struct isar_hw *isar)
  1008. {
  1009. struct isar_ch *ch;
  1010. get_irq_infos(isar);
  1011. switch (isar->iis & ISAR_IIS_MSCMSD) {
  1012. case ISAR_IIS_RDATA:
  1013. ch = sel_bch_isar(isar, isar->iis >> 6);
  1014. if (ch)
  1015. isar_rcv_frame(ch);
  1016. else {
  1017. pr_debug("%s: ISAR spurious IIS_RDATA %x/%x/%x\n",
  1018. isar->name, isar->iis, isar->cmsb,
  1019. isar->clsb);
  1020. isar->write_reg(isar->hw, ISAR_IIA, 0);
  1021. }
  1022. break;
  1023. case ISAR_IIS_GSTEV:
  1024. isar->write_reg(isar->hw, ISAR_IIA, 0);
  1025. isar->bstat |= isar->cmsb;
  1026. check_send(isar, isar->cmsb);
  1027. break;
  1028. case ISAR_IIS_BSTEV:
  1029. #ifdef ERROR_STATISTIC
  1030. ch = sel_bch_isar(isar, isar->iis >> 6);
  1031. if (ch) {
  1032. if (isar->cmsb == BSTEV_TBO)
  1033. ch->bch.err_tx++;
  1034. if (isar->cmsb == BSTEV_RBO)
  1035. ch->bch.err_rdo++;
  1036. }
  1037. #endif
  1038. pr_debug("%s: Buffer STEV dpath%d msb(%x)\n",
  1039. isar->name, isar->iis>>6, isar->cmsb);
  1040. isar->write_reg(isar->hw, ISAR_IIA, 0);
  1041. break;
  1042. case ISAR_IIS_PSTEV:
  1043. ch = sel_bch_isar(isar, isar->iis >> 6);
  1044. if (ch) {
  1045. rcv_mbox(isar, NULL);
  1046. if (ch->bch.state == ISDN_P_B_MODEM_ASYNC)
  1047. isar_pump_statev_modem(ch, isar->cmsb);
  1048. else if (ch->bch.state == ISDN_P_B_T30_FAX)
  1049. isar_pump_statev_fax(ch, isar->cmsb);
  1050. else if (ch->bch.state == ISDN_P_B_RAW) {
  1051. int tt;
  1052. tt = isar->cmsb | 0x30;
  1053. if (tt == 0x3e)
  1054. tt = '*';
  1055. else if (tt == 0x3f)
  1056. tt = '#';
  1057. else if (tt > '9')
  1058. tt += 7;
  1059. tt |= DTMF_TONE_VAL;
  1060. _queue_data(&ch->bch.ch, PH_CONTROL_IND,
  1061. MISDN_ID_ANY, sizeof(tt), &tt,
  1062. GFP_ATOMIC);
  1063. } else
  1064. pr_debug("%s: ISAR IIS_PSTEV pm %d sta %x\n",
  1065. isar->name, ch->bch.state,
  1066. isar->cmsb);
  1067. } else {
  1068. pr_debug("%s: ISAR spurious IIS_PSTEV %x/%x/%x\n",
  1069. isar->name, isar->iis, isar->cmsb,
  1070. isar->clsb);
  1071. isar->write_reg(isar->hw, ISAR_IIA, 0);
  1072. }
  1073. break;
  1074. case ISAR_IIS_PSTRSP:
  1075. ch = sel_bch_isar(isar, isar->iis >> 6);
  1076. if (ch) {
  1077. rcv_mbox(isar, NULL);
  1078. isar_pump_status_rsp(ch);
  1079. } else {
  1080. pr_debug("%s: ISAR spurious IIS_PSTRSP %x/%x/%x\n",
  1081. isar->name, isar->iis, isar->cmsb,
  1082. isar->clsb);
  1083. isar->write_reg(isar->hw, ISAR_IIA, 0);
  1084. }
  1085. break;
  1086. case ISAR_IIS_DIAG:
  1087. case ISAR_IIS_BSTRSP:
  1088. case ISAR_IIS_IOM2RSP:
  1089. rcv_mbox(isar, NULL);
  1090. break;
  1091. case ISAR_IIS_INVMSG:
  1092. rcv_mbox(isar, NULL);
  1093. pr_debug("%s: invalid msg his:%x\n", isar->name, isar->cmsb);
  1094. break;
  1095. default:
  1096. rcv_mbox(isar, NULL);
  1097. pr_debug("%s: unhandled msg iis(%x) ctrl(%x/%x)\n",
  1098. isar->name, isar->iis, isar->cmsb, isar->clsb);
  1099. break;
  1100. }
  1101. }
  1102. EXPORT_SYMBOL(mISDNisar_irq);
  1103. static void
  1104. ftimer_handler(unsigned long data)
  1105. {
  1106. struct isar_ch *ch = (struct isar_ch *)data;
  1107. pr_debug("%s: ftimer flags %lx\n", ch->is->name, ch->bch.Flags);
  1108. test_and_clear_bit(FLG_FTI_RUN, &ch->bch.Flags);
  1109. if (test_and_clear_bit(FLG_LL_CONN, &ch->bch.Flags))
  1110. deliver_status(ch, HW_MOD_CONNECT);
  1111. }
  1112. static void
  1113. setup_pump(struct isar_ch *ch) {
  1114. u8 dps = SET_DPS(ch->dpath);
  1115. u8 ctrl, param[6];
  1116. switch (ch->bch.state) {
  1117. case ISDN_P_NONE:
  1118. case ISDN_P_B_RAW:
  1119. case ISDN_P_B_HDLC:
  1120. send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
  1121. break;
  1122. case ISDN_P_B_L2DTMF:
  1123. if (test_bit(FLG_DTMFSEND, &ch->bch.Flags)) {
  1124. param[0] = 5; /* TOA 5 db */
  1125. send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG,
  1126. PMOD_DTMF_TRANS, 1, param);
  1127. } else {
  1128. param[0] = 40; /* REL -46 dbm */
  1129. send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG,
  1130. PMOD_DTMF, 1, param);
  1131. }
  1132. case ISDN_P_B_MODEM_ASYNC:
  1133. ctrl = PMOD_DATAMODEM;
  1134. if (test_bit(FLG_ORIGIN, &ch->bch.Flags)) {
  1135. ctrl |= PCTRL_ORIG;
  1136. param[5] = PV32P6_CTN;
  1137. } else {
  1138. param[5] = PV32P6_ATN;
  1139. }
  1140. param[0] = 6; /* 6 db */
  1141. param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
  1142. PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
  1143. param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
  1144. param[3] = PV32P4_UT144;
  1145. param[4] = PV32P5_UT144;
  1146. send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
  1147. break;
  1148. case ISDN_P_B_T30_FAX:
  1149. ctrl = PMOD_FAX;
  1150. if (test_bit(FLG_ORIGIN, &ch->bch.Flags)) {
  1151. ctrl |= PCTRL_ORIG;
  1152. param[1] = PFAXP2_CTN;
  1153. } else {
  1154. param[1] = PFAXP2_ATN;
  1155. }
  1156. param[0] = 6; /* 6 db */
  1157. send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
  1158. ch->state = STFAX_NULL;
  1159. ch->newcmd = 0;
  1160. ch->newmod = 0;
  1161. test_and_set_bit(FLG_FTI_RUN, &ch->bch.Flags);
  1162. break;
  1163. }
  1164. udelay(1000);
  1165. send_mbox(ch->is, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  1166. udelay(1000);
  1167. }
  1168. static void
  1169. setup_sart(struct isar_ch *ch) {
  1170. u8 dps = SET_DPS(ch->dpath);
  1171. u8 ctrl, param[2] = {0, 0};
  1172. switch (ch->bch.state) {
  1173. case ISDN_P_NONE:
  1174. send_mbox(ch->is, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE,
  1175. 0, NULL);
  1176. break;
  1177. case ISDN_P_B_RAW:
  1178. case ISDN_P_B_L2DTMF:
  1179. send_mbox(ch->is, dps | ISAR_HIS_SARTCFG, SMODE_BINARY,
  1180. 2, param);
  1181. break;
  1182. case ISDN_P_B_HDLC:
  1183. case ISDN_P_B_T30_FAX:
  1184. send_mbox(ch->is, dps | ISAR_HIS_SARTCFG, SMODE_HDLC,
  1185. 1, param);
  1186. break;
  1187. case ISDN_P_B_MODEM_ASYNC:
  1188. ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
  1189. param[0] = S_P1_CHS_8;
  1190. param[1] = S_P2_BFT_DEF;
  1191. send_mbox(ch->is, dps | ISAR_HIS_SARTCFG, ctrl, 2, param);
  1192. break;
  1193. }
  1194. udelay(1000);
  1195. send_mbox(ch->is, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
  1196. udelay(1000);
  1197. }
  1198. static void
  1199. setup_iom2(struct isar_ch *ch) {
  1200. u8 dps = SET_DPS(ch->dpath);
  1201. u8 cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD, 0, 0, 0, 0};
  1202. if (ch->bch.nr == 2) {
  1203. msg[1] = 1;
  1204. msg[3] = 1;
  1205. }
  1206. switch (ch->bch.state) {
  1207. case ISDN_P_NONE:
  1208. cmsb = 0;
  1209. /* dummy slot */
  1210. msg[1] = ch->dpath + 2;
  1211. msg[3] = ch->dpath + 2;
  1212. break;
  1213. case ISDN_P_B_RAW:
  1214. case ISDN_P_B_HDLC:
  1215. break;
  1216. case ISDN_P_B_MODEM_ASYNC:
  1217. case ISDN_P_B_T30_FAX:
  1218. cmsb |= IOM_CTRL_RCV;
  1219. case ISDN_P_B_L2DTMF:
  1220. if (test_bit(FLG_DTMFSEND, &ch->bch.Flags))
  1221. cmsb |= IOM_CTRL_RCV;
  1222. cmsb |= IOM_CTRL_ALAW;
  1223. break;
  1224. }
  1225. send_mbox(ch->is, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
  1226. udelay(1000);
  1227. send_mbox(ch->is, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
  1228. udelay(1000);
  1229. }
  1230. static int
  1231. modeisar(struct isar_ch *ch, u32 bprotocol)
  1232. {
  1233. /* Here we are selecting the best datapath for requested protocol */
  1234. if (ch->bch.state == ISDN_P_NONE) { /* New Setup */
  1235. switch (bprotocol) {
  1236. case ISDN_P_NONE: /* init */
  1237. if (!ch->dpath)
  1238. /* no init for dpath 0 */
  1239. return 0;
  1240. test_and_clear_bit(FLG_HDLC, &ch->bch.Flags);
  1241. test_and_clear_bit(FLG_TRANSPARENT, &ch->bch.Flags);
  1242. break;
  1243. case ISDN_P_B_RAW:
  1244. case ISDN_P_B_HDLC:
  1245. /* best is datapath 2 */
  1246. if (!test_and_set_bit(ISAR_DP2_USE, &ch->is->Flags))
  1247. ch->dpath = 2;
  1248. else if (!test_and_set_bit(ISAR_DP1_USE,
  1249. &ch->is->Flags))
  1250. ch->dpath = 1;
  1251. else {
  1252. pr_info("modeisar both pathes in use\n");
  1253. return -EBUSY;
  1254. }
  1255. if (bprotocol == ISDN_P_B_HDLC)
  1256. test_and_set_bit(FLG_HDLC, &ch->bch.Flags);
  1257. else
  1258. test_and_set_bit(FLG_TRANSPARENT,
  1259. &ch->bch.Flags);
  1260. break;
  1261. case ISDN_P_B_MODEM_ASYNC:
  1262. case ISDN_P_B_T30_FAX:
  1263. case ISDN_P_B_L2DTMF:
  1264. /* only datapath 1 */
  1265. if (!test_and_set_bit(ISAR_DP1_USE, &ch->is->Flags))
  1266. ch->dpath = 1;
  1267. else {
  1268. pr_info("%s: ISAR modeisar analog functions"
  1269. "only with DP1\n", ch->is->name);
  1270. return -EBUSY;
  1271. }
  1272. break;
  1273. default:
  1274. pr_info("%s: protocol not known %x\n", ch->is->name,
  1275. bprotocol);
  1276. return -ENOPROTOOPT;
  1277. }
  1278. }
  1279. pr_debug("%s: ISAR ch%d dp%d protocol %x->%x\n", ch->is->name,
  1280. ch->bch.nr, ch->dpath, ch->bch.state, bprotocol);
  1281. ch->bch.state = bprotocol;
  1282. setup_pump(ch);
  1283. setup_iom2(ch);
  1284. setup_sart(ch);
  1285. if (ch->bch.state == ISDN_P_NONE) {
  1286. /* Clear resources */
  1287. if (ch->dpath == 1)
  1288. test_and_clear_bit(ISAR_DP1_USE, &ch->is->Flags);
  1289. else if (ch->dpath == 2)
  1290. test_and_clear_bit(ISAR_DP2_USE, &ch->is->Flags);
  1291. ch->dpath = 0;
  1292. ch->is->ctrl(ch->is->hw, HW_DEACT_IND, ch->bch.nr);
  1293. } else
  1294. ch->is->ctrl(ch->is->hw, HW_ACTIVATE_IND, ch->bch.nr);
  1295. return 0;
  1296. }
  1297. static void
  1298. isar_pump_cmd(struct isar_ch *ch, u32 cmd, u8 para)
  1299. {
  1300. u8 dps = SET_DPS(ch->dpath);
  1301. u8 ctrl = 0, nom = 0, p1 = 0;
  1302. pr_debug("%s: isar_pump_cmd %x/%x state(%x)\n",
  1303. ch->is->name, cmd, para, ch->bch.state);
  1304. switch (cmd) {
  1305. case HW_MOD_FTM:
  1306. if (ch->state == STFAX_READY) {
  1307. p1 = para;
  1308. ctrl = PCTRL_CMD_FTM;
  1309. nom = 1;
  1310. ch->state = STFAX_LINE;
  1311. ch->cmd = ctrl;
  1312. ch->mod = para;
  1313. ch->newmod = 0;
  1314. ch->newcmd = 0;
  1315. ch->try_mod = 3;
  1316. } else if ((ch->state == STFAX_ACTIV) &&
  1317. (ch->cmd == PCTRL_CMD_FTM) && (ch->mod == para))
  1318. deliver_status(ch, HW_MOD_CONNECT);
  1319. else {
  1320. ch->newmod = para;
  1321. ch->newcmd = PCTRL_CMD_FTM;
  1322. nom = 0;
  1323. ctrl = PCTRL_CMD_ESC;
  1324. ch->state = STFAX_ESCAPE;
  1325. }
  1326. break;
  1327. case HW_MOD_FTH:
  1328. if (ch->state == STFAX_READY) {
  1329. p1 = para;
  1330. ctrl = PCTRL_CMD_FTH;
  1331. nom = 1;
  1332. ch->state = STFAX_LINE;
  1333. ch->cmd = ctrl;
  1334. ch->mod = para;
  1335. ch->newmod = 0;
  1336. ch->newcmd = 0;
  1337. ch->try_mod = 3;
  1338. } else if ((ch->state == STFAX_ACTIV) &&
  1339. (ch->cmd == PCTRL_CMD_FTH) && (ch->mod == para))
  1340. deliver_status(ch, HW_MOD_CONNECT);
  1341. else {
  1342. ch->newmod = para;
  1343. ch->newcmd = PCTRL_CMD_FTH;
  1344. nom = 0;
  1345. ctrl = PCTRL_CMD_ESC;
  1346. ch->state = STFAX_ESCAPE;
  1347. }
  1348. break;
  1349. case HW_MOD_FRM:
  1350. if (ch->state == STFAX_READY) {
  1351. p1 = para;
  1352. ctrl = PCTRL_CMD_FRM;
  1353. nom = 1;
  1354. ch->state = STFAX_LINE;
  1355. ch->cmd = ctrl;
  1356. ch->mod = para;
  1357. ch->newmod = 0;
  1358. ch->newcmd = 0;
  1359. ch->try_mod = 3;
  1360. } else if ((ch->state == STFAX_ACTIV) &&
  1361. (ch->cmd == PCTRL_CMD_FRM) && (ch->mod == para))
  1362. deliver_status(ch, HW_MOD_CONNECT);
  1363. else {
  1364. ch->newmod = para;
  1365. ch->newcmd = PCTRL_CMD_FRM;
  1366. nom = 0;
  1367. ctrl = PCTRL_CMD_ESC;
  1368. ch->state = STFAX_ESCAPE;
  1369. }
  1370. break;
  1371. case HW_MOD_FRH:
  1372. if (ch->state == STFAX_READY) {
  1373. p1 = para;
  1374. ctrl = PCTRL_CMD_FRH;
  1375. nom = 1;
  1376. ch->state = STFAX_LINE;
  1377. ch->cmd = ctrl;
  1378. ch->mod = para;
  1379. ch->newmod = 0;
  1380. ch->newcmd = 0;
  1381. ch->try_mod = 3;
  1382. } else if ((ch->state == STFAX_ACTIV) &&
  1383. (ch->cmd == PCTRL_CMD_FRH) && (ch->mod == para))
  1384. deliver_status(ch, HW_MOD_CONNECT);
  1385. else {
  1386. ch->newmod = para;
  1387. ch->newcmd = PCTRL_CMD_FRH;
  1388. nom = 0;
  1389. ctrl = PCTRL_CMD_ESC;
  1390. ch->state = STFAX_ESCAPE;
  1391. }
  1392. break;
  1393. case PCTRL_CMD_TDTMF:
  1394. p1 = para;
  1395. nom = 1;
  1396. ctrl = PCTRL_CMD_TDTMF;
  1397. break;
  1398. }
  1399. if (ctrl)
  1400. send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
  1401. }
  1402. static void
  1403. isar_setup(struct isar_hw *isar)
  1404. {
  1405. u8 msg;
  1406. int i;
  1407. /* Dpath 1, 2 */
  1408. msg = 61;
  1409. for (i = 0; i < 2; i++) {
  1410. /* Buffer Config */
  1411. send_mbox(isar, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
  1412. ISAR_HIS_P12CFG, 4, 1, &msg);
  1413. isar->ch[i].mml = msg;
  1414. isar->ch[i].bch.state = 0;
  1415. isar->ch[i].dpath = i + 1;
  1416. modeisar(&isar->ch[i], ISDN_P_NONE);
  1417. }
  1418. }
  1419. static int
  1420. isar_l2l1(struct mISDNchannel *ch, struct sk_buff *skb)
  1421. {
  1422. struct bchannel *bch = container_of(ch, struct bchannel, ch);
  1423. struct isar_ch *ich = container_of(bch, struct isar_ch, bch);
  1424. int ret = -EINVAL;
  1425. struct mISDNhead *hh = mISDN_HEAD_P(skb);
  1426. u32 id, *val;
  1427. u_long flags;
  1428. switch (hh->prim) {
  1429. case PH_DATA_REQ:
  1430. spin_lock_irqsave(ich->is->hwlock, flags);
  1431. ret = bchannel_senddata(bch, skb);
  1432. if (ret > 0) { /* direct TX */
  1433. id = hh->id; /* skb can be freed */
  1434. ret = 0;
  1435. isar_fill_fifo(ich);
  1436. spin_unlock_irqrestore(ich->is->hwlock, flags);
  1437. if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
  1438. queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
  1439. } else
  1440. spin_unlock_irqrestore(ich->is->hwlock, flags);
  1441. return ret;
  1442. case PH_ACTIVATE_REQ:
  1443. spin_lock_irqsave(ich->is->hwlock, flags);
  1444. if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
  1445. ret = modeisar(ich, ch->protocol);
  1446. else
  1447. ret = 0;
  1448. spin_unlock_irqrestore(ich->is->hwlock, flags);
  1449. if (!ret)
  1450. _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
  1451. NULL, GFP_KERNEL);
  1452. break;
  1453. case PH_DEACTIVATE_REQ:
  1454. spin_lock_irqsave(ich->is->hwlock, flags);
  1455. mISDN_clear_bchannel(bch);
  1456. modeisar(ich, ISDN_P_NONE);
  1457. spin_unlock_irqrestore(ich->is->hwlock, flags);
  1458. _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
  1459. NULL, GFP_KERNEL);
  1460. ret = 0;
  1461. break;
  1462. case PH_CONTROL_REQ:
  1463. val = (u32 *)skb->data;
  1464. pr_debug("%s: PH_CONTROL | REQUEST %x/%x\n", ich->is->name,
  1465. hh->id, *val);
  1466. if ((hh->id == 0) && ((*val & ~DTMF_TONE_MASK) ==
  1467. DTMF_TONE_VAL)) {
  1468. if (bch->state == ISDN_P_B_L2DTMF) {
  1469. char tt = *val & DTMF_TONE_MASK;
  1470. if (tt == '*')
  1471. tt = 0x1e;
  1472. else if (tt == '#')
  1473. tt = 0x1f;
  1474. else if (tt > '9')
  1475. tt -= 7;
  1476. tt &= 0x1f;
  1477. spin_lock_irqsave(ich->is->hwlock, flags);
  1478. isar_pump_cmd(ich, PCTRL_CMD_TDTMF, tt);
  1479. spin_unlock_irqrestore(ich->is->hwlock, flags);
  1480. } else {
  1481. pr_info("%s: DTMF send wrong protocol %x\n",
  1482. __func__, bch->state);
  1483. return -EINVAL;
  1484. }
  1485. } else if ((hh->id == HW_MOD_FRM) || (hh->id == HW_MOD_FRH) ||
  1486. (hh->id == HW_MOD_FTM) || (hh->id == HW_MOD_FTH)) {
  1487. for (id = 0; id < FAXMODCNT; id++)
  1488. if (faxmodulation[id] == *val)
  1489. break;
  1490. if ((FAXMODCNT > id) &&
  1491. test_bit(FLG_INITIALIZED, &bch->Flags)) {
  1492. pr_debug("%s: isar: new mod\n", ich->is->name);
  1493. isar_pump_cmd(ich, hh->id, *val);
  1494. ret = 0;
  1495. } else {
  1496. pr_info("%s: wrong modulation\n",
  1497. ich->is->name);
  1498. ret = -EINVAL;
  1499. }
  1500. } else if (hh->id == HW_MOD_LASTDATA)
  1501. test_and_set_bit(FLG_DLEETX, &bch->Flags);
  1502. else {
  1503. pr_info("%s: unknown PH_CONTROL_REQ %x\n",
  1504. ich->is->name, hh->id);
  1505. ret = -EINVAL;
  1506. }
  1507. default:
  1508. pr_info("%s: %s unknown prim(%x,%x)\n",
  1509. ich->is->name, __func__, hh->prim, hh->id);
  1510. ret = -EINVAL;
  1511. }
  1512. if (!ret)
  1513. dev_kfree_skb(skb);
  1514. return ret;
  1515. }
  1516. static int
  1517. channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
  1518. {
  1519. int ret = 0;
  1520. switch (cq->op) {
  1521. case MISDN_CTRL_GETOP:
  1522. cq->op = 0;
  1523. break;
  1524. /* Nothing implemented yet */
  1525. case MISDN_CTRL_FILL_EMPTY:
  1526. default:
  1527. pr_info("%s: unknown Op %x\n", __func__, cq->op);
  1528. ret = -EINVAL;
  1529. break;
  1530. }
  1531. return ret;
  1532. }
  1533. static int
  1534. isar_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
  1535. {
  1536. struct bchannel *bch = container_of(ch, struct bchannel, ch);
  1537. struct isar_ch *ich = container_of(bch, struct isar_ch, bch);
  1538. int ret = -EINVAL;
  1539. u_long flags;
  1540. pr_debug("%s: %s cmd:%x %p\n", ich->is->name, __func__, cmd, arg);
  1541. switch (cmd) {
  1542. case CLOSE_CHANNEL:
  1543. test_and_clear_bit(FLG_OPEN, &bch->Flags);
  1544. if (test_bit(FLG_ACTIVE, &bch->Flags)) {
  1545. spin_lock_irqsave(ich->is->hwlock, flags);
  1546. mISDN_freebchannel(bch);
  1547. modeisar(ich, ISDN_P_NONE);
  1548. spin_unlock_irqrestore(ich->is->hwlock, flags);
  1549. } else {
  1550. skb_queue_purge(&bch->rqueue);
  1551. bch->rcount = 0;
  1552. }
  1553. ch->protocol = ISDN_P_NONE;
  1554. ch->peer = NULL;
  1555. module_put(ich->is->owner);
  1556. ret = 0;
  1557. break;
  1558. case CONTROL_CHANNEL:
  1559. ret = channel_bctrl(bch, arg);
  1560. break;
  1561. default:
  1562. pr_info("%s: %s unknown prim(%x)\n",
  1563. ich->is->name, __func__, cmd);
  1564. }
  1565. return ret;
  1566. }
  1567. static void
  1568. free_isar(struct isar_hw *isar)
  1569. {
  1570. modeisar(&isar->ch[0], ISDN_P_NONE);
  1571. modeisar(&isar->ch[1], ISDN_P_NONE);
  1572. del_timer(&isar->ch[0].ftimer);
  1573. del_timer(&isar->ch[1].ftimer);
  1574. test_and_clear_bit(FLG_INITIALIZED, &isar->ch[0].bch.Flags);
  1575. test_and_clear_bit(FLG_INITIALIZED, &isar->ch[1].bch.Flags);
  1576. }
  1577. static int
  1578. init_isar(struct isar_hw *isar)
  1579. {
  1580. int cnt = 3;
  1581. while (cnt--) {
  1582. isar->version = ISARVersion(isar);
  1583. if (isar->ch[0].bch.debug & DEBUG_HW)
  1584. pr_notice("%s: Testing version %d (%d time)\n",
  1585. isar->name, isar->version, 3 - cnt);
  1586. if (isar->version == 1)
  1587. break;
  1588. isar->ctrl(isar->hw, HW_RESET_REQ, 0);
  1589. }
  1590. if (isar->version != 1)
  1591. return -EINVAL;
  1592. isar->ch[0].ftimer.function = &ftimer_handler;
  1593. isar->ch[0].ftimer.data = (long)&isar->ch[0];
  1594. init_timer(&isar->ch[0].ftimer);
  1595. test_and_set_bit(FLG_INITIALIZED, &isar->ch[0].bch.Flags);
  1596. isar->ch[1].ftimer.function = &ftimer_handler;
  1597. isar->ch[1].ftimer.data = (long)&isar->ch[1];
  1598. init_timer(&isar->ch[1].ftimer);
  1599. test_and_set_bit(FLG_INITIALIZED, &isar->ch[1].bch.Flags);
  1600. return 0;
  1601. }
  1602. static int
  1603. isar_open(struct isar_hw *isar, struct channel_req *rq)
  1604. {
  1605. struct bchannel *bch;
  1606. if (rq->adr.channel > 2)
  1607. return -EINVAL;
  1608. if (rq->protocol == ISDN_P_NONE)
  1609. return -EINVAL;
  1610. bch = &isar->ch[rq->adr.channel - 1].bch;
  1611. if (test_and_set_bit(FLG_OPEN, &bch->Flags))
  1612. return -EBUSY; /* b-channel can be only open once */
  1613. test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
  1614. bch->ch.protocol = rq->protocol;
  1615. rq->ch = &bch->ch;
  1616. return 0;
  1617. }
  1618. u32
  1619. mISDNisar_init(struct isar_hw *isar, void *hw)
  1620. {
  1621. u32 ret, i;
  1622. isar->hw = hw;
  1623. for (i = 0; i < 2; i++) {
  1624. isar->ch[i].bch.nr = i + 1;
  1625. mISDN_initbchannel(&isar->ch[i].bch, MAX_DATA_MEM);
  1626. isar->ch[i].bch.ch.nr = i + 1;
  1627. isar->ch[i].bch.ch.send = &isar_l2l1;
  1628. isar->ch[i].bch.ch.ctrl = isar_bctrl;
  1629. isar->ch[i].bch.hw = hw;
  1630. isar->ch[i].is = isar;
  1631. }
  1632. isar->init = &init_isar;
  1633. isar->release = &free_isar;
  1634. isar->firmware = &load_firmware;
  1635. isar->open = &isar_open;
  1636. ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
  1637. (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)) |
  1638. (1 << (ISDN_P_B_L2DTMF & ISDN_P_B_MASK)) |
  1639. (1 << (ISDN_P_B_MODEM_ASYNC & ISDN_P_B_MASK)) |
  1640. (1 << (ISDN_P_B_T30_FAX & ISDN_P_B_MASK));
  1641. return ret;
  1642. }
  1643. EXPORT_SYMBOL(mISDNisar_init);
  1644. static int __init isar_mod_init(void)
  1645. {
  1646. pr_notice("mISDN: ISAR driver Rev. %s\n", ISAR_REV);
  1647. return 0;
  1648. }
  1649. static void __exit isar_mod_cleanup(void)
  1650. {
  1651. pr_notice("mISDN: ISAR module unloaded\n");
  1652. }
  1653. module_init(isar_mod_init);
  1654. module_exit(isar_mod_cleanup);