radeon_fence.c 11 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <asm/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #include "radeon_trace.h"
  42. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  43. {
  44. unsigned long irq_flags;
  45. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  46. if (fence->emited) {
  47. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  48. return 0;
  49. }
  50. fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  51. if (!rdev->cp.ready) {
  52. /* FIXME: cp is not running assume everythings is done right
  53. * away
  54. */
  55. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  56. } else
  57. radeon_fence_ring_emit(rdev, fence);
  58. trace_radeon_fence_emit(rdev->ddev, fence->seq);
  59. fence->emited = true;
  60. list_move_tail(&fence->list, &rdev->fence_drv.emited);
  61. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  62. return 0;
  63. }
  64. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  65. {
  66. struct radeon_fence *fence;
  67. struct list_head *i, *n;
  68. uint32_t seq;
  69. bool wake = false;
  70. unsigned long cjiffies;
  71. if (rdev->wb.enabled) {
  72. u32 scratch_index;
  73. if (rdev->wb.use_event)
  74. scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  75. else
  76. scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  77. seq = rdev->wb.wb[scratch_index/4];
  78. } else
  79. seq = RREG32(rdev->fence_drv.scratch_reg);
  80. if (seq != rdev->fence_drv.last_seq) {
  81. rdev->fence_drv.last_seq = seq;
  82. rdev->fence_drv.last_jiffies = jiffies;
  83. rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  84. } else {
  85. cjiffies = jiffies;
  86. if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) {
  87. cjiffies -= rdev->fence_drv.last_jiffies;
  88. if (time_after(rdev->fence_drv.last_timeout, cjiffies)) {
  89. /* update the timeout */
  90. rdev->fence_drv.last_timeout -= cjiffies;
  91. } else {
  92. /* the 500ms timeout is elapsed we should test
  93. * for GPU lockup
  94. */
  95. rdev->fence_drv.last_timeout = 1;
  96. }
  97. } else {
  98. /* wrap around update last jiffies, we will just wait
  99. * a little longer
  100. */
  101. rdev->fence_drv.last_jiffies = cjiffies;
  102. }
  103. return false;
  104. }
  105. n = NULL;
  106. list_for_each(i, &rdev->fence_drv.emited) {
  107. fence = list_entry(i, struct radeon_fence, list);
  108. if (fence->seq == seq) {
  109. n = i;
  110. break;
  111. }
  112. }
  113. /* all fence previous to this one are considered as signaled */
  114. if (n) {
  115. i = n;
  116. do {
  117. n = i->prev;
  118. list_move_tail(i, &rdev->fence_drv.signaled);
  119. fence = list_entry(i, struct radeon_fence, list);
  120. fence->signaled = true;
  121. i = n;
  122. } while (i != &rdev->fence_drv.emited);
  123. wake = true;
  124. }
  125. return wake;
  126. }
  127. static void radeon_fence_destroy(struct kref *kref)
  128. {
  129. unsigned long irq_flags;
  130. struct radeon_fence *fence;
  131. fence = container_of(kref, struct radeon_fence, kref);
  132. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  133. list_del(&fence->list);
  134. fence->emited = false;
  135. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  136. kfree(fence);
  137. }
  138. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  139. {
  140. unsigned long irq_flags;
  141. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  142. if ((*fence) == NULL) {
  143. return -ENOMEM;
  144. }
  145. kref_init(&((*fence)->kref));
  146. (*fence)->rdev = rdev;
  147. (*fence)->emited = false;
  148. (*fence)->signaled = false;
  149. (*fence)->seq = 0;
  150. INIT_LIST_HEAD(&(*fence)->list);
  151. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  152. list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  153. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  154. return 0;
  155. }
  156. bool radeon_fence_signaled(struct radeon_fence *fence)
  157. {
  158. unsigned long irq_flags;
  159. bool signaled = false;
  160. if (!fence)
  161. return true;
  162. if (fence->rdev->gpu_lockup)
  163. return true;
  164. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  165. signaled = fence->signaled;
  166. /* if we are shuting down report all fence as signaled */
  167. if (fence->rdev->shutdown) {
  168. signaled = true;
  169. }
  170. if (!fence->emited) {
  171. WARN(1, "Querying an unemited fence : %p !\n", fence);
  172. signaled = true;
  173. }
  174. if (!signaled) {
  175. radeon_fence_poll_locked(fence->rdev);
  176. signaled = fence->signaled;
  177. }
  178. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  179. return signaled;
  180. }
  181. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  182. {
  183. struct radeon_device *rdev;
  184. unsigned long irq_flags, timeout;
  185. u32 seq;
  186. int r;
  187. if (fence == NULL) {
  188. WARN(1, "Querying an invalid fence : %p !\n", fence);
  189. return 0;
  190. }
  191. rdev = fence->rdev;
  192. if (radeon_fence_signaled(fence)) {
  193. return 0;
  194. }
  195. timeout = rdev->fence_drv.last_timeout;
  196. retry:
  197. /* save current sequence used to check for GPU lockup */
  198. seq = rdev->fence_drv.last_seq;
  199. trace_radeon_fence_wait_begin(rdev->ddev, seq);
  200. if (intr) {
  201. radeon_irq_kms_sw_irq_get(rdev);
  202. r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  203. radeon_fence_signaled(fence), timeout);
  204. radeon_irq_kms_sw_irq_put(rdev);
  205. if (unlikely(r < 0)) {
  206. return r;
  207. }
  208. } else {
  209. radeon_irq_kms_sw_irq_get(rdev);
  210. r = wait_event_timeout(rdev->fence_drv.queue,
  211. radeon_fence_signaled(fence), timeout);
  212. radeon_irq_kms_sw_irq_put(rdev);
  213. }
  214. trace_radeon_fence_wait_end(rdev->ddev, seq);
  215. if (unlikely(!radeon_fence_signaled(fence))) {
  216. /* we were interrupted for some reason and fence isn't
  217. * isn't signaled yet, resume wait
  218. */
  219. if (r) {
  220. timeout = r;
  221. goto retry;
  222. }
  223. /* don't protect read access to rdev->fence_drv.last_seq
  224. * if we experiencing a lockup the value doesn't change
  225. */
  226. if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) {
  227. /* good news we believe it's a lockup */
  228. WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
  229. fence->seq, seq);
  230. /* FIXME: what should we do ? marking everyone
  231. * as signaled for now
  232. */
  233. rdev->gpu_lockup = true;
  234. r = radeon_gpu_reset(rdev);
  235. if (r)
  236. return r;
  237. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  238. rdev->gpu_lockup = false;
  239. }
  240. timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  241. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  242. rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  243. rdev->fence_drv.last_jiffies = jiffies;
  244. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  245. goto retry;
  246. }
  247. return 0;
  248. }
  249. int radeon_fence_wait_next(struct radeon_device *rdev)
  250. {
  251. unsigned long irq_flags;
  252. struct radeon_fence *fence;
  253. int r;
  254. if (rdev->gpu_lockup) {
  255. return 0;
  256. }
  257. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  258. if (list_empty(&rdev->fence_drv.emited)) {
  259. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  260. return 0;
  261. }
  262. fence = list_entry(rdev->fence_drv.emited.next,
  263. struct radeon_fence, list);
  264. radeon_fence_ref(fence);
  265. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  266. r = radeon_fence_wait(fence, false);
  267. radeon_fence_unref(&fence);
  268. return r;
  269. }
  270. int radeon_fence_wait_last(struct radeon_device *rdev)
  271. {
  272. unsigned long irq_flags;
  273. struct radeon_fence *fence;
  274. int r;
  275. if (rdev->gpu_lockup) {
  276. return 0;
  277. }
  278. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  279. if (list_empty(&rdev->fence_drv.emited)) {
  280. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  281. return 0;
  282. }
  283. fence = list_entry(rdev->fence_drv.emited.prev,
  284. struct radeon_fence, list);
  285. radeon_fence_ref(fence);
  286. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  287. r = radeon_fence_wait(fence, false);
  288. radeon_fence_unref(&fence);
  289. return r;
  290. }
  291. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  292. {
  293. kref_get(&fence->kref);
  294. return fence;
  295. }
  296. void radeon_fence_unref(struct radeon_fence **fence)
  297. {
  298. struct radeon_fence *tmp = *fence;
  299. *fence = NULL;
  300. if (tmp) {
  301. kref_put(&tmp->kref, &radeon_fence_destroy);
  302. }
  303. }
  304. void radeon_fence_process(struct radeon_device *rdev)
  305. {
  306. unsigned long irq_flags;
  307. bool wake;
  308. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  309. wake = radeon_fence_poll_locked(rdev);
  310. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  311. if (wake) {
  312. wake_up_all(&rdev->fence_drv.queue);
  313. }
  314. }
  315. int radeon_fence_driver_init(struct radeon_device *rdev)
  316. {
  317. unsigned long irq_flags;
  318. int r;
  319. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  320. r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  321. if (r) {
  322. dev_err(rdev->dev, "fence failed to get scratch register\n");
  323. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  324. return r;
  325. }
  326. WREG32(rdev->fence_drv.scratch_reg, 0);
  327. atomic_set(&rdev->fence_drv.seq, 0);
  328. INIT_LIST_HEAD(&rdev->fence_drv.created);
  329. INIT_LIST_HEAD(&rdev->fence_drv.emited);
  330. INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  331. init_waitqueue_head(&rdev->fence_drv.queue);
  332. rdev->fence_drv.initialized = true;
  333. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  334. if (radeon_debugfs_fence_init(rdev)) {
  335. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  336. }
  337. return 0;
  338. }
  339. void radeon_fence_driver_fini(struct radeon_device *rdev)
  340. {
  341. unsigned long irq_flags;
  342. if (!rdev->fence_drv.initialized)
  343. return;
  344. wake_up_all(&rdev->fence_drv.queue);
  345. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  346. radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
  347. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  348. rdev->fence_drv.initialized = false;
  349. }
  350. /*
  351. * Fence debugfs
  352. */
  353. #if defined(CONFIG_DEBUG_FS)
  354. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  355. {
  356. struct drm_info_node *node = (struct drm_info_node *)m->private;
  357. struct drm_device *dev = node->minor->dev;
  358. struct radeon_device *rdev = dev->dev_private;
  359. struct radeon_fence *fence;
  360. seq_printf(m, "Last signaled fence 0x%08X\n",
  361. RREG32(rdev->fence_drv.scratch_reg));
  362. if (!list_empty(&rdev->fence_drv.emited)) {
  363. fence = list_entry(rdev->fence_drv.emited.prev,
  364. struct radeon_fence, list);
  365. seq_printf(m, "Last emited fence %p with 0x%08X\n",
  366. fence, fence->seq);
  367. }
  368. return 0;
  369. }
  370. static struct drm_info_list radeon_debugfs_fence_list[] = {
  371. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  372. };
  373. #endif
  374. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  375. {
  376. #if defined(CONFIG_DEBUG_FS)
  377. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  378. #else
  379. return 0;
  380. #endif
  381. }