nouveau_drv.c 13 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #include <linux/console.h>
  25. #include "drmP.h"
  26. #include "drm.h"
  27. #include "drm_crtc_helper.h"
  28. #include "nouveau_drv.h"
  29. #include "nouveau_hw.h"
  30. #include "nouveau_fb.h"
  31. #include "nouveau_fbcon.h"
  32. #include "nouveau_pm.h"
  33. #include "nv50_display.h"
  34. #include "drm_pciids.h"
  35. MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
  36. int nouveau_agpmode = -1;
  37. module_param_named(agpmode, nouveau_agpmode, int, 0400);
  38. MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  39. static int nouveau_modeset = -1; /* kms */
  40. module_param_named(modeset, nouveau_modeset, int, 0400);
  41. MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  42. char *nouveau_vbios;
  43. module_param_named(vbios, nouveau_vbios, charp, 0400);
  44. MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  45. int nouveau_vram_pushbuf;
  46. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  47. MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  48. int nouveau_vram_notify = 0;
  49. module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  50. MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  51. int nouveau_duallink = 1;
  52. module_param_named(duallink, nouveau_duallink, int, 0400);
  53. MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  54. int nouveau_uscript_lvds = -1;
  55. module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  56. MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  57. int nouveau_uscript_tmds = -1;
  58. module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  59. MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  60. int nouveau_ignorelid = 0;
  61. module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  62. MODULE_PARM_DESC(noaccel, "Disable all acceleration");
  63. int nouveau_noaccel = 0;
  64. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  65. MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
  66. int nouveau_nofbaccel = 0;
  67. module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  68. MODULE_PARM_DESC(force_post, "Force POST");
  69. int nouveau_force_post = 0;
  70. module_param_named(force_post, nouveau_force_post, int, 0400);
  71. MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
  72. int nouveau_override_conntype = 0;
  73. module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
  74. MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
  75. int nouveau_tv_disable = 0;
  76. module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
  77. MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  78. "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  79. "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  80. "\t\tDefault: PAL\n"
  81. "\t\t*NOTE* Ignored for cards with external TV encoders.");
  82. char *nouveau_tv_norm;
  83. module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  84. MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  85. "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  86. "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  87. "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
  88. int nouveau_reg_debug;
  89. module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  90. MODULE_PARM_DESC(perflvl, "Performance level (default: boot)\n");
  91. char *nouveau_perflvl;
  92. module_param_named(perflvl, nouveau_perflvl, charp, 0400);
  93. MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)\n");
  94. int nouveau_perflvl_wr;
  95. module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
  96. MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n");
  97. int nouveau_msi;
  98. module_param_named(msi, nouveau_msi, int, 0400);
  99. int nouveau_fbpercrtc;
  100. #if 0
  101. module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  102. #endif
  103. static struct pci_device_id pciidlist[] = {
  104. {
  105. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  106. .class = PCI_BASE_CLASS_DISPLAY << 16,
  107. .class_mask = 0xff << 16,
  108. },
  109. {
  110. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  111. .class = PCI_BASE_CLASS_DISPLAY << 16,
  112. .class_mask = 0xff << 16,
  113. },
  114. {}
  115. };
  116. MODULE_DEVICE_TABLE(pci, pciidlist);
  117. static struct drm_driver driver;
  118. static int __devinit
  119. nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  120. {
  121. return drm_get_pci_dev(pdev, ent, &driver);
  122. }
  123. static void
  124. nouveau_pci_remove(struct pci_dev *pdev)
  125. {
  126. struct drm_device *dev = pci_get_drvdata(pdev);
  127. drm_put_dev(dev);
  128. }
  129. int
  130. nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
  131. {
  132. struct drm_device *dev = pci_get_drvdata(pdev);
  133. struct drm_nouveau_private *dev_priv = dev->dev_private;
  134. struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  135. struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  136. struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  137. struct nouveau_channel *chan;
  138. struct drm_crtc *crtc;
  139. int ret, i;
  140. if (pm_state.event == PM_EVENT_PRETHAW)
  141. return 0;
  142. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  143. return 0;
  144. NV_INFO(dev, "Disabling fbcon acceleration...\n");
  145. nouveau_fbcon_save_disable_accel(dev);
  146. NV_INFO(dev, "Unpinning framebuffer(s)...\n");
  147. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  148. struct nouveau_framebuffer *nouveau_fb;
  149. nouveau_fb = nouveau_framebuffer(crtc->fb);
  150. if (!nouveau_fb || !nouveau_fb->nvbo)
  151. continue;
  152. nouveau_bo_unpin(nouveau_fb->nvbo);
  153. }
  154. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  155. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  156. nouveau_bo_unmap(nv_crtc->cursor.nvbo);
  157. nouveau_bo_unpin(nv_crtc->cursor.nvbo);
  158. }
  159. NV_INFO(dev, "Evicting buffers...\n");
  160. ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  161. NV_INFO(dev, "Idling channels...\n");
  162. for (i = 0; i < pfifo->channels; i++) {
  163. chan = dev_priv->channels.ptr[i];
  164. if (chan && chan->pushbuf_bo)
  165. nouveau_channel_idle(chan);
  166. }
  167. pgraph->fifo_access(dev, false);
  168. nouveau_wait_for_idle(dev);
  169. pfifo->reassign(dev, false);
  170. pfifo->disable(dev);
  171. pfifo->unload_context(dev);
  172. pgraph->unload_context(dev);
  173. ret = pinstmem->suspend(dev);
  174. if (ret) {
  175. NV_ERROR(dev, "... failed: %d\n", ret);
  176. goto out_abort;
  177. }
  178. NV_INFO(dev, "Suspending GPU objects...\n");
  179. ret = nouveau_gpuobj_suspend(dev);
  180. if (ret) {
  181. NV_ERROR(dev, "... failed: %d\n", ret);
  182. pinstmem->resume(dev);
  183. goto out_abort;
  184. }
  185. NV_INFO(dev, "And we're gone!\n");
  186. pci_save_state(pdev);
  187. if (pm_state.event == PM_EVENT_SUSPEND) {
  188. pci_disable_device(pdev);
  189. pci_set_power_state(pdev, PCI_D3hot);
  190. }
  191. console_lock();
  192. nouveau_fbcon_set_suspend(dev, 1);
  193. console_unlock();
  194. nouveau_fbcon_restore_accel(dev);
  195. return 0;
  196. out_abort:
  197. NV_INFO(dev, "Re-enabling acceleration..\n");
  198. pfifo->enable(dev);
  199. pfifo->reassign(dev, true);
  200. pgraph->fifo_access(dev, true);
  201. return ret;
  202. }
  203. int
  204. nouveau_pci_resume(struct pci_dev *pdev)
  205. {
  206. struct drm_device *dev = pci_get_drvdata(pdev);
  207. struct drm_nouveau_private *dev_priv = dev->dev_private;
  208. struct nouveau_engine *engine = &dev_priv->engine;
  209. struct drm_crtc *crtc;
  210. int ret, i;
  211. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  212. return 0;
  213. nouveau_fbcon_save_disable_accel(dev);
  214. NV_INFO(dev, "We're back, enabling device...\n");
  215. pci_set_power_state(pdev, PCI_D0);
  216. pci_restore_state(pdev);
  217. if (pci_enable_device(pdev))
  218. return -1;
  219. pci_set_master(dev->pdev);
  220. /* Make sure the AGP controller is in a consistent state */
  221. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
  222. nouveau_mem_reset_agp(dev);
  223. /* Make the CRTCs accessible */
  224. engine->display.early_init(dev);
  225. NV_INFO(dev, "POSTing device...\n");
  226. ret = nouveau_run_vbios_init(dev);
  227. if (ret)
  228. return ret;
  229. nouveau_pm_resume(dev);
  230. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  231. ret = nouveau_mem_init_agp(dev);
  232. if (ret) {
  233. NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
  234. return ret;
  235. }
  236. }
  237. NV_INFO(dev, "Restoring GPU objects...\n");
  238. nouveau_gpuobj_resume(dev);
  239. NV_INFO(dev, "Reinitialising engines...\n");
  240. engine->instmem.resume(dev);
  241. engine->mc.init(dev);
  242. engine->timer.init(dev);
  243. engine->fb.init(dev);
  244. engine->graph.init(dev);
  245. engine->crypt.init(dev);
  246. engine->fifo.init(dev);
  247. nouveau_irq_postinstall(dev);
  248. /* Re-write SKIPS, they'll have been lost over the suspend */
  249. if (nouveau_vram_pushbuf) {
  250. struct nouveau_channel *chan;
  251. int j;
  252. for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  253. chan = dev_priv->channels.ptr[i];
  254. if (!chan || !chan->pushbuf_bo)
  255. continue;
  256. for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
  257. nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
  258. }
  259. }
  260. NV_INFO(dev, "Restoring mode...\n");
  261. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  262. struct nouveau_framebuffer *nouveau_fb;
  263. nouveau_fb = nouveau_framebuffer(crtc->fb);
  264. if (!nouveau_fb || !nouveau_fb->nvbo)
  265. continue;
  266. nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
  267. }
  268. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  269. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  270. ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
  271. if (!ret)
  272. ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
  273. if (ret)
  274. NV_ERROR(dev, "Could not pin/map cursor.\n");
  275. }
  276. engine->display.init(dev);
  277. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  278. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  279. u32 offset = nv_crtc->cursor.nvbo->bo.mem.start << PAGE_SHIFT;
  280. nv_crtc->cursor.set_offset(nv_crtc, offset);
  281. nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
  282. nv_crtc->cursor_saved_y);
  283. }
  284. /* Force CLUT to get re-loaded during modeset */
  285. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  286. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  287. nv_crtc->lut.depth = 0;
  288. }
  289. console_lock();
  290. nouveau_fbcon_set_suspend(dev, 0);
  291. console_unlock();
  292. nouveau_fbcon_zfill_all(dev);
  293. drm_helper_resume_force_mode(dev);
  294. nouveau_fbcon_restore_accel(dev);
  295. return 0;
  296. }
  297. static struct drm_driver driver = {
  298. .driver_features =
  299. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  300. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
  301. DRIVER_MODESET,
  302. .load = nouveau_load,
  303. .firstopen = nouveau_firstopen,
  304. .lastclose = nouveau_lastclose,
  305. .unload = nouveau_unload,
  306. .preclose = nouveau_preclose,
  307. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  308. .debugfs_init = nouveau_debugfs_init,
  309. .debugfs_cleanup = nouveau_debugfs_takedown,
  310. #endif
  311. .irq_preinstall = nouveau_irq_preinstall,
  312. .irq_postinstall = nouveau_irq_postinstall,
  313. .irq_uninstall = nouveau_irq_uninstall,
  314. .irq_handler = nouveau_irq_handler,
  315. .get_vblank_counter = drm_vblank_count,
  316. .enable_vblank = nouveau_vblank_enable,
  317. .disable_vblank = nouveau_vblank_disable,
  318. .reclaim_buffers = drm_core_reclaim_buffers,
  319. .ioctls = nouveau_ioctls,
  320. .fops = {
  321. .owner = THIS_MODULE,
  322. .open = drm_open,
  323. .release = drm_release,
  324. .unlocked_ioctl = drm_ioctl,
  325. .mmap = nouveau_ttm_mmap,
  326. .poll = drm_poll,
  327. .fasync = drm_fasync,
  328. .read = drm_read,
  329. #if defined(CONFIG_COMPAT)
  330. .compat_ioctl = nouveau_compat_ioctl,
  331. #endif
  332. .llseek = noop_llseek,
  333. },
  334. .gem_init_object = nouveau_gem_object_new,
  335. .gem_free_object = nouveau_gem_object_del,
  336. .name = DRIVER_NAME,
  337. .desc = DRIVER_DESC,
  338. #ifdef GIT_REVISION
  339. .date = GIT_REVISION,
  340. #else
  341. .date = DRIVER_DATE,
  342. #endif
  343. .major = DRIVER_MAJOR,
  344. .minor = DRIVER_MINOR,
  345. .patchlevel = DRIVER_PATCHLEVEL,
  346. };
  347. static struct pci_driver nouveau_pci_driver = {
  348. .name = DRIVER_NAME,
  349. .id_table = pciidlist,
  350. .probe = nouveau_pci_probe,
  351. .remove = nouveau_pci_remove,
  352. .suspend = nouveau_pci_suspend,
  353. .resume = nouveau_pci_resume
  354. };
  355. static int __init nouveau_init(void)
  356. {
  357. driver.num_ioctls = nouveau_max_ioctl;
  358. if (nouveau_modeset == -1) {
  359. #ifdef CONFIG_VGA_CONSOLE
  360. if (vgacon_text_force())
  361. nouveau_modeset = 0;
  362. else
  363. #endif
  364. nouveau_modeset = 1;
  365. }
  366. if (!nouveau_modeset)
  367. return 0;
  368. nouveau_register_dsm_handler();
  369. return drm_pci_init(&driver, &nouveau_pci_driver);
  370. }
  371. static void __exit nouveau_exit(void)
  372. {
  373. if (!nouveau_modeset)
  374. return;
  375. drm_pci_exit(&driver, &nouveau_pci_driver);
  376. nouveau_unregister_dsm_handler();
  377. }
  378. module_init(nouveau_init);
  379. module_exit(nouveau_exit);
  380. MODULE_AUTHOR(DRIVER_AUTHOR);
  381. MODULE_DESCRIPTION(DRIVER_DESC);
  382. MODULE_LICENSE("GPL and additional rights");