intel_sdvo.c 79 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "drm_crtc.h"
  34. #include "drm_edid.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. static const char *tv_format_names[] = {
  50. "NTSC_M" , "NTSC_J" , "NTSC_443",
  51. "PAL_B" , "PAL_D" , "PAL_G" ,
  52. "PAL_H" , "PAL_I" , "PAL_M" ,
  53. "PAL_N" , "PAL_NC" , "PAL_60" ,
  54. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  55. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  56. "SECAM_60"
  57. };
  58. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  59. struct intel_sdvo {
  60. struct intel_encoder base;
  61. struct i2c_adapter *i2c;
  62. u8 slave_addr;
  63. struct i2c_adapter ddc;
  64. /* Register for the SDVO device: SDVOB or SDVOC */
  65. int sdvo_reg;
  66. /* Active outputs controlled by this SDVO output */
  67. uint16_t controlled_output;
  68. /*
  69. * Capabilities of the SDVO device returned by
  70. * i830_sdvo_get_capabilities()
  71. */
  72. struct intel_sdvo_caps caps;
  73. /* Pixel clock limitations reported by the SDVO device, in kHz */
  74. int pixel_clock_min, pixel_clock_max;
  75. /*
  76. * For multiple function SDVO device,
  77. * this is for current attached outputs.
  78. */
  79. uint16_t attached_output;
  80. /**
  81. * This is used to select the color range of RBG outputs in HDMI mode.
  82. * It is only valid when using TMDS encoding and 8 bit per color mode.
  83. */
  84. uint32_t color_range;
  85. /**
  86. * This is set if we're going to treat the device as TV-out.
  87. *
  88. * While we have these nice friendly flags for output types that ought
  89. * to decide this for us, the S-Video output on our HDMI+S-Video card
  90. * shows up as RGB1 (VGA).
  91. */
  92. bool is_tv;
  93. /* This is for current tv format name */
  94. int tv_format_index;
  95. /**
  96. * This is set if we treat the device as HDMI, instead of DVI.
  97. */
  98. bool is_hdmi;
  99. bool has_hdmi_monitor;
  100. bool has_hdmi_audio;
  101. /**
  102. * This is set if we detect output of sdvo device as LVDS and
  103. * have a valid fixed mode to use with the panel.
  104. */
  105. bool is_lvds;
  106. /**
  107. * This is sdvo fixed pannel mode pointer
  108. */
  109. struct drm_display_mode *sdvo_lvds_fixed_mode;
  110. /* DDC bus used by this SDVO encoder */
  111. uint8_t ddc_bus;
  112. /* Input timings for adjusted_mode */
  113. struct intel_sdvo_dtd input_dtd;
  114. };
  115. struct intel_sdvo_connector {
  116. struct intel_connector base;
  117. /* Mark the type of connector */
  118. uint16_t output_flag;
  119. int force_audio;
  120. /* This contains all current supported TV format */
  121. u8 tv_format_supported[TV_FORMAT_NUM];
  122. int format_supported_num;
  123. struct drm_property *tv_format;
  124. struct drm_property *force_audio_property;
  125. /* add the property for the SDVO-TV */
  126. struct drm_property *left;
  127. struct drm_property *right;
  128. struct drm_property *top;
  129. struct drm_property *bottom;
  130. struct drm_property *hpos;
  131. struct drm_property *vpos;
  132. struct drm_property *contrast;
  133. struct drm_property *saturation;
  134. struct drm_property *hue;
  135. struct drm_property *sharpness;
  136. struct drm_property *flicker_filter;
  137. struct drm_property *flicker_filter_adaptive;
  138. struct drm_property *flicker_filter_2d;
  139. struct drm_property *tv_chroma_filter;
  140. struct drm_property *tv_luma_filter;
  141. struct drm_property *dot_crawl;
  142. /* add the property for the SDVO-TV/LVDS */
  143. struct drm_property *brightness;
  144. /* Add variable to record current setting for the above property */
  145. u32 left_margin, right_margin, top_margin, bottom_margin;
  146. /* this is to get the range of margin.*/
  147. u32 max_hscan, max_vscan;
  148. u32 max_hpos, cur_hpos;
  149. u32 max_vpos, cur_vpos;
  150. u32 cur_brightness, max_brightness;
  151. u32 cur_contrast, max_contrast;
  152. u32 cur_saturation, max_saturation;
  153. u32 cur_hue, max_hue;
  154. u32 cur_sharpness, max_sharpness;
  155. u32 cur_flicker_filter, max_flicker_filter;
  156. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  157. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  158. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  159. u32 cur_tv_luma_filter, max_tv_luma_filter;
  160. u32 cur_dot_crawl, max_dot_crawl;
  161. };
  162. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  163. {
  164. return container_of(encoder, struct intel_sdvo, base.base);
  165. }
  166. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  167. {
  168. return container_of(intel_attached_encoder(connector),
  169. struct intel_sdvo, base);
  170. }
  171. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  172. {
  173. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  174. }
  175. static bool
  176. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  177. static bool
  178. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  179. struct intel_sdvo_connector *intel_sdvo_connector,
  180. int type);
  181. static bool
  182. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  183. struct intel_sdvo_connector *intel_sdvo_connector);
  184. /**
  185. * Writes the SDVOB or SDVOC with the given value, but always writes both
  186. * SDVOB and SDVOC to work around apparent hardware issues (according to
  187. * comments in the BIOS).
  188. */
  189. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  190. {
  191. struct drm_device *dev = intel_sdvo->base.base.dev;
  192. struct drm_i915_private *dev_priv = dev->dev_private;
  193. u32 bval = val, cval = val;
  194. int i;
  195. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  196. I915_WRITE(intel_sdvo->sdvo_reg, val);
  197. I915_READ(intel_sdvo->sdvo_reg);
  198. return;
  199. }
  200. if (intel_sdvo->sdvo_reg == SDVOB) {
  201. cval = I915_READ(SDVOC);
  202. } else {
  203. bval = I915_READ(SDVOB);
  204. }
  205. /*
  206. * Write the registers twice for luck. Sometimes,
  207. * writing them only once doesn't appear to 'stick'.
  208. * The BIOS does this too. Yay, magic
  209. */
  210. for (i = 0; i < 2; i++)
  211. {
  212. I915_WRITE(SDVOB, bval);
  213. I915_READ(SDVOB);
  214. I915_WRITE(SDVOC, cval);
  215. I915_READ(SDVOC);
  216. }
  217. }
  218. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  219. {
  220. struct i2c_msg msgs[] = {
  221. {
  222. .addr = intel_sdvo->slave_addr,
  223. .flags = 0,
  224. .len = 1,
  225. .buf = &addr,
  226. },
  227. {
  228. .addr = intel_sdvo->slave_addr,
  229. .flags = I2C_M_RD,
  230. .len = 1,
  231. .buf = ch,
  232. }
  233. };
  234. int ret;
  235. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  236. return true;
  237. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  238. return false;
  239. }
  240. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  241. /** Mapping of command numbers to names, for debug output */
  242. static const struct _sdvo_cmd_name {
  243. u8 cmd;
  244. const char *name;
  245. } sdvo_cmd_names[] = {
  246. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  247. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  248. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  289. /* Add the op code for SDVO enhancements */
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  334. /* HDMI op code */
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  355. };
  356. #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
  357. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  358. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  359. const void *args, int args_len)
  360. {
  361. int i;
  362. DRM_DEBUG_KMS("%s: W: %02X ",
  363. SDVO_NAME(intel_sdvo), cmd);
  364. for (i = 0; i < args_len; i++)
  365. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  366. for (; i < 8; i++)
  367. DRM_LOG_KMS(" ");
  368. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  369. if (cmd == sdvo_cmd_names[i].cmd) {
  370. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  371. break;
  372. }
  373. }
  374. if (i == ARRAY_SIZE(sdvo_cmd_names))
  375. DRM_LOG_KMS("(%02X)", cmd);
  376. DRM_LOG_KMS("\n");
  377. }
  378. static const char *cmd_status_names[] = {
  379. "Power on",
  380. "Success",
  381. "Not supported",
  382. "Invalid arg",
  383. "Pending",
  384. "Target not specified",
  385. "Scaling not supported"
  386. };
  387. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  388. const void *args, int args_len)
  389. {
  390. u8 buf[args_len*2 + 2], status;
  391. struct i2c_msg msgs[args_len + 3];
  392. int i, ret;
  393. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  394. for (i = 0; i < args_len; i++) {
  395. msgs[i].addr = intel_sdvo->slave_addr;
  396. msgs[i].flags = 0;
  397. msgs[i].len = 2;
  398. msgs[i].buf = buf + 2 *i;
  399. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  400. buf[2*i + 1] = ((u8*)args)[i];
  401. }
  402. msgs[i].addr = intel_sdvo->slave_addr;
  403. msgs[i].flags = 0;
  404. msgs[i].len = 2;
  405. msgs[i].buf = buf + 2*i;
  406. buf[2*i + 0] = SDVO_I2C_OPCODE;
  407. buf[2*i + 1] = cmd;
  408. /* the following two are to read the response */
  409. status = SDVO_I2C_CMD_STATUS;
  410. msgs[i+1].addr = intel_sdvo->slave_addr;
  411. msgs[i+1].flags = 0;
  412. msgs[i+1].len = 1;
  413. msgs[i+1].buf = &status;
  414. msgs[i+2].addr = intel_sdvo->slave_addr;
  415. msgs[i+2].flags = I2C_M_RD;
  416. msgs[i+2].len = 1;
  417. msgs[i+2].buf = &status;
  418. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  419. if (ret < 0) {
  420. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  421. return false;
  422. }
  423. if (ret != i+3) {
  424. /* failure in I2C transfer */
  425. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  426. return false;
  427. }
  428. return true;
  429. }
  430. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  431. void *response, int response_len)
  432. {
  433. u8 retry = 5;
  434. u8 status;
  435. int i;
  436. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  437. /*
  438. * The documentation states that all commands will be
  439. * processed within 15µs, and that we need only poll
  440. * the status byte a maximum of 3 times in order for the
  441. * command to be complete.
  442. *
  443. * Check 5 times in case the hardware failed to read the docs.
  444. */
  445. if (!intel_sdvo_read_byte(intel_sdvo,
  446. SDVO_I2C_CMD_STATUS,
  447. &status))
  448. goto log_fail;
  449. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  450. udelay(15);
  451. if (!intel_sdvo_read_byte(intel_sdvo,
  452. SDVO_I2C_CMD_STATUS,
  453. &status))
  454. goto log_fail;
  455. }
  456. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  457. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  458. else
  459. DRM_LOG_KMS("(??? %d)", status);
  460. if (status != SDVO_CMD_STATUS_SUCCESS)
  461. goto log_fail;
  462. /* Read the command response */
  463. for (i = 0; i < response_len; i++) {
  464. if (!intel_sdvo_read_byte(intel_sdvo,
  465. SDVO_I2C_RETURN_0 + i,
  466. &((u8 *)response)[i]))
  467. goto log_fail;
  468. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  469. }
  470. DRM_LOG_KMS("\n");
  471. return true;
  472. log_fail:
  473. DRM_LOG_KMS("... failed\n");
  474. return false;
  475. }
  476. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  477. {
  478. if (mode->clock >= 100000)
  479. return 1;
  480. else if (mode->clock >= 50000)
  481. return 2;
  482. else
  483. return 4;
  484. }
  485. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  486. u8 ddc_bus)
  487. {
  488. /* This must be the immediately preceding write before the i2c xfer */
  489. return intel_sdvo_write_cmd(intel_sdvo,
  490. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  491. &ddc_bus, 1);
  492. }
  493. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  494. {
  495. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  496. return false;
  497. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  498. }
  499. static bool
  500. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  501. {
  502. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  503. return false;
  504. return intel_sdvo_read_response(intel_sdvo, value, len);
  505. }
  506. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  507. {
  508. struct intel_sdvo_set_target_input_args targets = {0};
  509. return intel_sdvo_set_value(intel_sdvo,
  510. SDVO_CMD_SET_TARGET_INPUT,
  511. &targets, sizeof(targets));
  512. }
  513. /**
  514. * Return whether each input is trained.
  515. *
  516. * This function is making an assumption about the layout of the response,
  517. * which should be checked against the docs.
  518. */
  519. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  520. {
  521. struct intel_sdvo_get_trained_inputs_response response;
  522. BUILD_BUG_ON(sizeof(response) != 1);
  523. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  524. &response, sizeof(response)))
  525. return false;
  526. *input_1 = response.input0_trained;
  527. *input_2 = response.input1_trained;
  528. return true;
  529. }
  530. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  531. u16 outputs)
  532. {
  533. return intel_sdvo_set_value(intel_sdvo,
  534. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  535. &outputs, sizeof(outputs));
  536. }
  537. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  538. int mode)
  539. {
  540. u8 state = SDVO_ENCODER_STATE_ON;
  541. switch (mode) {
  542. case DRM_MODE_DPMS_ON:
  543. state = SDVO_ENCODER_STATE_ON;
  544. break;
  545. case DRM_MODE_DPMS_STANDBY:
  546. state = SDVO_ENCODER_STATE_STANDBY;
  547. break;
  548. case DRM_MODE_DPMS_SUSPEND:
  549. state = SDVO_ENCODER_STATE_SUSPEND;
  550. break;
  551. case DRM_MODE_DPMS_OFF:
  552. state = SDVO_ENCODER_STATE_OFF;
  553. break;
  554. }
  555. return intel_sdvo_set_value(intel_sdvo,
  556. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  557. }
  558. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  559. int *clock_min,
  560. int *clock_max)
  561. {
  562. struct intel_sdvo_pixel_clock_range clocks;
  563. BUILD_BUG_ON(sizeof(clocks) != 4);
  564. if (!intel_sdvo_get_value(intel_sdvo,
  565. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  566. &clocks, sizeof(clocks)))
  567. return false;
  568. /* Convert the values from units of 10 kHz to kHz. */
  569. *clock_min = clocks.min * 10;
  570. *clock_max = clocks.max * 10;
  571. return true;
  572. }
  573. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  574. u16 outputs)
  575. {
  576. return intel_sdvo_set_value(intel_sdvo,
  577. SDVO_CMD_SET_TARGET_OUTPUT,
  578. &outputs, sizeof(outputs));
  579. }
  580. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  581. struct intel_sdvo_dtd *dtd)
  582. {
  583. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  584. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  585. }
  586. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  587. struct intel_sdvo_dtd *dtd)
  588. {
  589. return intel_sdvo_set_timing(intel_sdvo,
  590. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  591. }
  592. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  593. struct intel_sdvo_dtd *dtd)
  594. {
  595. return intel_sdvo_set_timing(intel_sdvo,
  596. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  597. }
  598. static bool
  599. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  600. uint16_t clock,
  601. uint16_t width,
  602. uint16_t height)
  603. {
  604. struct intel_sdvo_preferred_input_timing_args args;
  605. memset(&args, 0, sizeof(args));
  606. args.clock = clock;
  607. args.width = width;
  608. args.height = height;
  609. args.interlace = 0;
  610. if (intel_sdvo->is_lvds &&
  611. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  612. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  613. args.scaled = 1;
  614. return intel_sdvo_set_value(intel_sdvo,
  615. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  616. &args, sizeof(args));
  617. }
  618. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  619. struct intel_sdvo_dtd *dtd)
  620. {
  621. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  622. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  623. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  624. &dtd->part1, sizeof(dtd->part1)) &&
  625. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  626. &dtd->part2, sizeof(dtd->part2));
  627. }
  628. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  629. {
  630. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  631. }
  632. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  633. const struct drm_display_mode *mode)
  634. {
  635. uint16_t width, height;
  636. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  637. uint16_t h_sync_offset, v_sync_offset;
  638. width = mode->crtc_hdisplay;
  639. height = mode->crtc_vdisplay;
  640. /* do some mode translations */
  641. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  642. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  643. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  644. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  645. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  646. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  647. dtd->part1.clock = mode->clock / 10;
  648. dtd->part1.h_active = width & 0xff;
  649. dtd->part1.h_blank = h_blank_len & 0xff;
  650. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  651. ((h_blank_len >> 8) & 0xf);
  652. dtd->part1.v_active = height & 0xff;
  653. dtd->part1.v_blank = v_blank_len & 0xff;
  654. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  655. ((v_blank_len >> 8) & 0xf);
  656. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  657. dtd->part2.h_sync_width = h_sync_len & 0xff;
  658. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  659. (v_sync_len & 0xf);
  660. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  661. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  662. ((v_sync_len & 0x30) >> 4);
  663. dtd->part2.dtd_flags = 0x18;
  664. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  665. dtd->part2.dtd_flags |= 0x2;
  666. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  667. dtd->part2.dtd_flags |= 0x4;
  668. dtd->part2.sdvo_flags = 0;
  669. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  670. dtd->part2.reserved = 0;
  671. }
  672. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  673. const struct intel_sdvo_dtd *dtd)
  674. {
  675. mode->hdisplay = dtd->part1.h_active;
  676. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  677. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  678. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  679. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  680. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  681. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  682. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  683. mode->vdisplay = dtd->part1.v_active;
  684. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  685. mode->vsync_start = mode->vdisplay;
  686. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  687. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  688. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  689. mode->vsync_end = mode->vsync_start +
  690. (dtd->part2.v_sync_off_width & 0xf);
  691. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  692. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  693. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  694. mode->clock = dtd->part1.clock * 10;
  695. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  696. if (dtd->part2.dtd_flags & 0x2)
  697. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  698. if (dtd->part2.dtd_flags & 0x4)
  699. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  700. }
  701. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  702. {
  703. struct intel_sdvo_encode encode;
  704. BUILD_BUG_ON(sizeof(encode) != 2);
  705. return intel_sdvo_get_value(intel_sdvo,
  706. SDVO_CMD_GET_SUPP_ENCODE,
  707. &encode, sizeof(encode));
  708. }
  709. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  710. uint8_t mode)
  711. {
  712. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  713. }
  714. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  715. uint8_t mode)
  716. {
  717. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  718. }
  719. #if 0
  720. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  721. {
  722. int i, j;
  723. uint8_t set_buf_index[2];
  724. uint8_t av_split;
  725. uint8_t buf_size;
  726. uint8_t buf[48];
  727. uint8_t *pos;
  728. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  729. for (i = 0; i <= av_split; i++) {
  730. set_buf_index[0] = i; set_buf_index[1] = 0;
  731. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  732. set_buf_index, 2);
  733. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  734. intel_sdvo_read_response(encoder, &buf_size, 1);
  735. pos = buf;
  736. for (j = 0; j <= buf_size; j += 8) {
  737. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  738. NULL, 0);
  739. intel_sdvo_read_response(encoder, pos, 8);
  740. pos += 8;
  741. }
  742. }
  743. }
  744. #endif
  745. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
  746. {
  747. struct dip_infoframe avi_if = {
  748. .type = DIP_TYPE_AVI,
  749. .ver = DIP_VERSION_AVI,
  750. .len = DIP_LEN_AVI,
  751. };
  752. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  753. uint8_t set_buf_index[2] = { 1, 0 };
  754. uint64_t *data = (uint64_t *)&avi_if;
  755. unsigned i;
  756. intel_dip_infoframe_csum(&avi_if);
  757. if (!intel_sdvo_set_value(intel_sdvo,
  758. SDVO_CMD_SET_HBUF_INDEX,
  759. set_buf_index, 2))
  760. return false;
  761. for (i = 0; i < sizeof(avi_if); i += 8) {
  762. if (!intel_sdvo_set_value(intel_sdvo,
  763. SDVO_CMD_SET_HBUF_DATA,
  764. data, 8))
  765. return false;
  766. data++;
  767. }
  768. return intel_sdvo_set_value(intel_sdvo,
  769. SDVO_CMD_SET_HBUF_TXRATE,
  770. &tx_rate, 1);
  771. }
  772. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  773. {
  774. struct intel_sdvo_tv_format format;
  775. uint32_t format_map;
  776. format_map = 1 << intel_sdvo->tv_format_index;
  777. memset(&format, 0, sizeof(format));
  778. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  779. BUILD_BUG_ON(sizeof(format) != 6);
  780. return intel_sdvo_set_value(intel_sdvo,
  781. SDVO_CMD_SET_TV_FORMAT,
  782. &format, sizeof(format));
  783. }
  784. static bool
  785. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  786. struct drm_display_mode *mode)
  787. {
  788. struct intel_sdvo_dtd output_dtd;
  789. if (!intel_sdvo_set_target_output(intel_sdvo,
  790. intel_sdvo->attached_output))
  791. return false;
  792. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  793. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  794. return false;
  795. return true;
  796. }
  797. static bool
  798. intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
  799. struct drm_display_mode *mode,
  800. struct drm_display_mode *adjusted_mode)
  801. {
  802. /* Reset the input timing to the screen. Assume always input 0. */
  803. if (!intel_sdvo_set_target_input(intel_sdvo))
  804. return false;
  805. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  806. mode->clock / 10,
  807. mode->hdisplay,
  808. mode->vdisplay))
  809. return false;
  810. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  811. &intel_sdvo->input_dtd))
  812. return false;
  813. intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
  814. drm_mode_set_crtcinfo(adjusted_mode, 0);
  815. return true;
  816. }
  817. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  818. struct drm_display_mode *mode,
  819. struct drm_display_mode *adjusted_mode)
  820. {
  821. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  822. int multiplier;
  823. /* We need to construct preferred input timings based on our
  824. * output timings. To do that, we have to set the output
  825. * timings, even though this isn't really the right place in
  826. * the sequence to do it. Oh well.
  827. */
  828. if (intel_sdvo->is_tv) {
  829. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  830. return false;
  831. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  832. mode,
  833. adjusted_mode);
  834. } else if (intel_sdvo->is_lvds) {
  835. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  836. intel_sdvo->sdvo_lvds_fixed_mode))
  837. return false;
  838. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  839. mode,
  840. adjusted_mode);
  841. }
  842. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  843. * SDVO device will factor out the multiplier during mode_set.
  844. */
  845. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  846. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  847. return true;
  848. }
  849. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  850. struct drm_display_mode *mode,
  851. struct drm_display_mode *adjusted_mode)
  852. {
  853. struct drm_device *dev = encoder->dev;
  854. struct drm_i915_private *dev_priv = dev->dev_private;
  855. struct drm_crtc *crtc = encoder->crtc;
  856. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  857. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  858. u32 sdvox;
  859. struct intel_sdvo_in_out_map in_out;
  860. struct intel_sdvo_dtd input_dtd;
  861. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  862. int rate;
  863. if (!mode)
  864. return;
  865. /* First, set the input mapping for the first input to our controlled
  866. * output. This is only correct if we're a single-input device, in
  867. * which case the first input is the output from the appropriate SDVO
  868. * channel on the motherboard. In a two-input device, the first input
  869. * will be SDVOB and the second SDVOC.
  870. */
  871. in_out.in0 = intel_sdvo->attached_output;
  872. in_out.in1 = 0;
  873. intel_sdvo_set_value(intel_sdvo,
  874. SDVO_CMD_SET_IN_OUT_MAP,
  875. &in_out, sizeof(in_out));
  876. /* Set the output timings to the screen */
  877. if (!intel_sdvo_set_target_output(intel_sdvo,
  878. intel_sdvo->attached_output))
  879. return;
  880. /* We have tried to get input timing in mode_fixup, and filled into
  881. * adjusted_mode.
  882. */
  883. if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
  884. input_dtd = intel_sdvo->input_dtd;
  885. } else {
  886. /* Set the output timing to the screen */
  887. if (!intel_sdvo_set_target_output(intel_sdvo,
  888. intel_sdvo->attached_output))
  889. return;
  890. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  891. (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
  892. }
  893. /* Set the input timing to the screen. Assume always input 0. */
  894. if (!intel_sdvo_set_target_input(intel_sdvo))
  895. return;
  896. if (intel_sdvo->has_hdmi_monitor) {
  897. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  898. intel_sdvo_set_colorimetry(intel_sdvo,
  899. SDVO_COLORIMETRY_RGB256);
  900. intel_sdvo_set_avi_infoframe(intel_sdvo);
  901. } else
  902. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  903. if (intel_sdvo->is_tv &&
  904. !intel_sdvo_set_tv_format(intel_sdvo))
  905. return;
  906. (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
  907. switch (pixel_multiplier) {
  908. default:
  909. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  910. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  911. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  912. }
  913. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  914. return;
  915. /* Set the SDVO control regs. */
  916. if (INTEL_INFO(dev)->gen >= 4) {
  917. sdvox = 0;
  918. if (intel_sdvo->is_hdmi)
  919. sdvox |= intel_sdvo->color_range;
  920. if (INTEL_INFO(dev)->gen < 5)
  921. sdvox |= SDVO_BORDER_ENABLE;
  922. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  923. sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  924. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  925. sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  926. } else {
  927. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  928. switch (intel_sdvo->sdvo_reg) {
  929. case SDVOB:
  930. sdvox &= SDVOB_PRESERVE_MASK;
  931. break;
  932. case SDVOC:
  933. sdvox &= SDVOC_PRESERVE_MASK;
  934. break;
  935. }
  936. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  937. }
  938. if (intel_crtc->pipe == 1)
  939. sdvox |= SDVO_PIPE_B_SELECT;
  940. if (intel_sdvo->has_hdmi_audio)
  941. sdvox |= SDVO_AUDIO_ENABLE;
  942. if (INTEL_INFO(dev)->gen >= 4) {
  943. /* done in crtc_mode_set as the dpll_md reg must be written early */
  944. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  945. /* done in crtc_mode_set as it lives inside the dpll register */
  946. } else {
  947. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  948. }
  949. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  950. INTEL_INFO(dev)->gen < 5)
  951. sdvox |= SDVO_STALL_SELECT;
  952. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  953. }
  954. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  955. {
  956. struct drm_device *dev = encoder->dev;
  957. struct drm_i915_private *dev_priv = dev->dev_private;
  958. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  959. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  960. u32 temp;
  961. if (mode != DRM_MODE_DPMS_ON) {
  962. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  963. if (0)
  964. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  965. if (mode == DRM_MODE_DPMS_OFF) {
  966. temp = I915_READ(intel_sdvo->sdvo_reg);
  967. if ((temp & SDVO_ENABLE) != 0) {
  968. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  969. }
  970. }
  971. } else {
  972. bool input1, input2;
  973. int i;
  974. u8 status;
  975. temp = I915_READ(intel_sdvo->sdvo_reg);
  976. if ((temp & SDVO_ENABLE) == 0)
  977. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  978. for (i = 0; i < 2; i++)
  979. intel_wait_for_vblank(dev, intel_crtc->pipe);
  980. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  981. /* Warn if the device reported failure to sync.
  982. * A lot of SDVO devices fail to notify of sync, but it's
  983. * a given it the status is a success, we succeeded.
  984. */
  985. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  986. DRM_DEBUG_KMS("First %s output reported failure to "
  987. "sync\n", SDVO_NAME(intel_sdvo));
  988. }
  989. if (0)
  990. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  991. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  992. }
  993. return;
  994. }
  995. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  996. struct drm_display_mode *mode)
  997. {
  998. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  999. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1000. return MODE_NO_DBLESCAN;
  1001. if (intel_sdvo->pixel_clock_min > mode->clock)
  1002. return MODE_CLOCK_LOW;
  1003. if (intel_sdvo->pixel_clock_max < mode->clock)
  1004. return MODE_CLOCK_HIGH;
  1005. if (intel_sdvo->is_lvds) {
  1006. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1007. return MODE_PANEL;
  1008. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1009. return MODE_PANEL;
  1010. }
  1011. return MODE_OK;
  1012. }
  1013. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1014. {
  1015. BUILD_BUG_ON(sizeof(*caps) != 8);
  1016. if (!intel_sdvo_get_value(intel_sdvo,
  1017. SDVO_CMD_GET_DEVICE_CAPS,
  1018. caps, sizeof(*caps)))
  1019. return false;
  1020. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1021. " vendor_id: %d\n"
  1022. " device_id: %d\n"
  1023. " device_rev_id: %d\n"
  1024. " sdvo_version_major: %d\n"
  1025. " sdvo_version_minor: %d\n"
  1026. " sdvo_inputs_mask: %d\n"
  1027. " smooth_scaling: %d\n"
  1028. " sharp_scaling: %d\n"
  1029. " up_scaling: %d\n"
  1030. " down_scaling: %d\n"
  1031. " stall_support: %d\n"
  1032. " output_flags: %d\n",
  1033. caps->vendor_id,
  1034. caps->device_id,
  1035. caps->device_rev_id,
  1036. caps->sdvo_version_major,
  1037. caps->sdvo_version_minor,
  1038. caps->sdvo_inputs_mask,
  1039. caps->smooth_scaling,
  1040. caps->sharp_scaling,
  1041. caps->up_scaling,
  1042. caps->down_scaling,
  1043. caps->stall_support,
  1044. caps->output_flags);
  1045. return true;
  1046. }
  1047. /* No use! */
  1048. #if 0
  1049. struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1050. {
  1051. struct drm_connector *connector = NULL;
  1052. struct intel_sdvo *iout = NULL;
  1053. struct intel_sdvo *sdvo;
  1054. /* find the sdvo connector */
  1055. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1056. iout = to_intel_sdvo(connector);
  1057. if (iout->type != INTEL_OUTPUT_SDVO)
  1058. continue;
  1059. sdvo = iout->dev_priv;
  1060. if (sdvo->sdvo_reg == SDVOB && sdvoB)
  1061. return connector;
  1062. if (sdvo->sdvo_reg == SDVOC && !sdvoB)
  1063. return connector;
  1064. }
  1065. return NULL;
  1066. }
  1067. int intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1068. {
  1069. u8 response[2];
  1070. u8 status;
  1071. struct intel_sdvo *intel_sdvo;
  1072. DRM_DEBUG_KMS("\n");
  1073. if (!connector)
  1074. return 0;
  1075. intel_sdvo = to_intel_sdvo(connector);
  1076. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1077. &response, 2) && response[0];
  1078. }
  1079. void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1080. {
  1081. u8 response[2];
  1082. u8 status;
  1083. struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
  1084. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1085. intel_sdvo_read_response(intel_sdvo, &response, 2);
  1086. if (on) {
  1087. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1088. status = intel_sdvo_read_response(intel_sdvo, &response, 2);
  1089. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1090. } else {
  1091. response[0] = 0;
  1092. response[1] = 0;
  1093. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1094. }
  1095. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1096. intel_sdvo_read_response(intel_sdvo, &response, 2);
  1097. }
  1098. #endif
  1099. static bool
  1100. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1101. {
  1102. /* Is there more than one type of output? */
  1103. int caps = intel_sdvo->caps.output_flags & 0xf;
  1104. return caps & -caps;
  1105. }
  1106. static struct edid *
  1107. intel_sdvo_get_edid(struct drm_connector *connector)
  1108. {
  1109. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1110. return drm_get_edid(connector, &sdvo->ddc);
  1111. }
  1112. /* Mac mini hack -- use the same DDC as the analog connector */
  1113. static struct edid *
  1114. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1115. {
  1116. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1117. return drm_get_edid(connector,
  1118. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1119. }
  1120. enum drm_connector_status
  1121. intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1122. {
  1123. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1124. enum drm_connector_status status;
  1125. struct edid *edid;
  1126. edid = intel_sdvo_get_edid(connector);
  1127. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1128. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1129. /*
  1130. * Don't use the 1 as the argument of DDC bus switch to get
  1131. * the EDID. It is used for SDVO SPD ROM.
  1132. */
  1133. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1134. intel_sdvo->ddc_bus = ddc;
  1135. edid = intel_sdvo_get_edid(connector);
  1136. if (edid)
  1137. break;
  1138. }
  1139. /*
  1140. * If we found the EDID on the other bus,
  1141. * assume that is the correct DDC bus.
  1142. */
  1143. if (edid == NULL)
  1144. intel_sdvo->ddc_bus = saved_ddc;
  1145. }
  1146. /*
  1147. * When there is no edid and no monitor is connected with VGA
  1148. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1149. */
  1150. if (edid == NULL)
  1151. edid = intel_sdvo_get_analog_edid(connector);
  1152. status = connector_status_unknown;
  1153. if (edid != NULL) {
  1154. /* DDC bus is shared, match EDID to connector type */
  1155. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1156. status = connector_status_connected;
  1157. if (intel_sdvo->is_hdmi) {
  1158. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1159. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1160. }
  1161. } else
  1162. status = connector_status_disconnected;
  1163. connector->display_info.raw_edid = NULL;
  1164. kfree(edid);
  1165. }
  1166. if (status == connector_status_connected) {
  1167. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1168. if (intel_sdvo_connector->force_audio)
  1169. intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
  1170. }
  1171. return status;
  1172. }
  1173. static enum drm_connector_status
  1174. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1175. {
  1176. uint16_t response;
  1177. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1178. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1179. enum drm_connector_status ret;
  1180. if (!intel_sdvo_write_cmd(intel_sdvo,
  1181. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1182. return connector_status_unknown;
  1183. /* add 30ms delay when the output type might be TV */
  1184. if (intel_sdvo->caps.output_flags &
  1185. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1186. mdelay(30);
  1187. if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
  1188. return connector_status_unknown;
  1189. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1190. response & 0xff, response >> 8,
  1191. intel_sdvo_connector->output_flag);
  1192. if (response == 0)
  1193. return connector_status_disconnected;
  1194. intel_sdvo->attached_output = response;
  1195. intel_sdvo->has_hdmi_monitor = false;
  1196. intel_sdvo->has_hdmi_audio = false;
  1197. if ((intel_sdvo_connector->output_flag & response) == 0)
  1198. ret = connector_status_disconnected;
  1199. else if (IS_TMDS(intel_sdvo_connector))
  1200. ret = intel_sdvo_hdmi_sink_detect(connector);
  1201. else {
  1202. struct edid *edid;
  1203. /* if we have an edid check it matches the connection */
  1204. edid = intel_sdvo_get_edid(connector);
  1205. if (edid == NULL)
  1206. edid = intel_sdvo_get_analog_edid(connector);
  1207. if (edid != NULL) {
  1208. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1209. ret = connector_status_disconnected;
  1210. else
  1211. ret = connector_status_connected;
  1212. connector->display_info.raw_edid = NULL;
  1213. kfree(edid);
  1214. } else
  1215. ret = connector_status_connected;
  1216. }
  1217. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1218. if (ret == connector_status_connected) {
  1219. intel_sdvo->is_tv = false;
  1220. intel_sdvo->is_lvds = false;
  1221. intel_sdvo->base.needs_tv_clock = false;
  1222. if (response & SDVO_TV_MASK) {
  1223. intel_sdvo->is_tv = true;
  1224. intel_sdvo->base.needs_tv_clock = true;
  1225. }
  1226. if (response & SDVO_LVDS_MASK)
  1227. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1228. }
  1229. return ret;
  1230. }
  1231. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1232. {
  1233. struct edid *edid;
  1234. /* set the bus switch and get the modes */
  1235. edid = intel_sdvo_get_edid(connector);
  1236. /*
  1237. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1238. * link between analog and digital outputs. So, if the regular SDVO
  1239. * DDC fails, check to see if the analog output is disconnected, in
  1240. * which case we'll look there for the digital DDC data.
  1241. */
  1242. if (edid == NULL)
  1243. edid = intel_sdvo_get_analog_edid(connector);
  1244. if (edid != NULL) {
  1245. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1246. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1247. bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector);
  1248. if (connector_is_digital == monitor_is_digital) {
  1249. drm_mode_connector_update_edid_property(connector, edid);
  1250. drm_add_edid_modes(connector, edid);
  1251. }
  1252. connector->display_info.raw_edid = NULL;
  1253. kfree(edid);
  1254. }
  1255. }
  1256. /*
  1257. * Set of SDVO TV modes.
  1258. * Note! This is in reply order (see loop in get_tv_modes).
  1259. * XXX: all 60Hz refresh?
  1260. */
  1261. static const struct drm_display_mode sdvo_tv_modes[] = {
  1262. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1263. 416, 0, 200, 201, 232, 233, 0,
  1264. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1265. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1266. 416, 0, 240, 241, 272, 273, 0,
  1267. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1268. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1269. 496, 0, 300, 301, 332, 333, 0,
  1270. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1271. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1272. 736, 0, 350, 351, 382, 383, 0,
  1273. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1274. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1275. 736, 0, 400, 401, 432, 433, 0,
  1276. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1277. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1278. 736, 0, 480, 481, 512, 513, 0,
  1279. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1280. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1281. 800, 0, 480, 481, 512, 513, 0,
  1282. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1283. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1284. 800, 0, 576, 577, 608, 609, 0,
  1285. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1286. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1287. 816, 0, 350, 351, 382, 383, 0,
  1288. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1289. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1290. 816, 0, 400, 401, 432, 433, 0,
  1291. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1292. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1293. 816, 0, 480, 481, 512, 513, 0,
  1294. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1295. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1296. 816, 0, 540, 541, 572, 573, 0,
  1297. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1298. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1299. 816, 0, 576, 577, 608, 609, 0,
  1300. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1301. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1302. 864, 0, 576, 577, 608, 609, 0,
  1303. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1304. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1305. 896, 0, 600, 601, 632, 633, 0,
  1306. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1307. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1308. 928, 0, 624, 625, 656, 657, 0,
  1309. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1310. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1311. 1016, 0, 766, 767, 798, 799, 0,
  1312. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1313. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1314. 1120, 0, 768, 769, 800, 801, 0,
  1315. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1316. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1317. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1318. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1319. };
  1320. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1321. {
  1322. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1323. struct intel_sdvo_sdtv_resolution_request tv_res;
  1324. uint32_t reply = 0, format_map = 0;
  1325. int i;
  1326. /* Read the list of supported input resolutions for the selected TV
  1327. * format.
  1328. */
  1329. format_map = 1 << intel_sdvo->tv_format_index;
  1330. memcpy(&tv_res, &format_map,
  1331. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1332. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1333. return;
  1334. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1335. if (!intel_sdvo_write_cmd(intel_sdvo,
  1336. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1337. &tv_res, sizeof(tv_res)))
  1338. return;
  1339. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1340. return;
  1341. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1342. if (reply & (1 << i)) {
  1343. struct drm_display_mode *nmode;
  1344. nmode = drm_mode_duplicate(connector->dev,
  1345. &sdvo_tv_modes[i]);
  1346. if (nmode)
  1347. drm_mode_probed_add(connector, nmode);
  1348. }
  1349. }
  1350. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1351. {
  1352. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1353. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1354. struct drm_display_mode *newmode;
  1355. /*
  1356. * Attempt to get the mode list from DDC.
  1357. * Assume that the preferred modes are
  1358. * arranged in priority order.
  1359. */
  1360. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1361. if (list_empty(&connector->probed_modes) == false)
  1362. goto end;
  1363. /* Fetch modes from VBT */
  1364. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1365. newmode = drm_mode_duplicate(connector->dev,
  1366. dev_priv->sdvo_lvds_vbt_mode);
  1367. if (newmode != NULL) {
  1368. /* Guarantee the mode is preferred */
  1369. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1370. DRM_MODE_TYPE_DRIVER);
  1371. drm_mode_probed_add(connector, newmode);
  1372. }
  1373. }
  1374. end:
  1375. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1376. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1377. intel_sdvo->sdvo_lvds_fixed_mode =
  1378. drm_mode_duplicate(connector->dev, newmode);
  1379. drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
  1380. 0);
  1381. intel_sdvo->is_lvds = true;
  1382. break;
  1383. }
  1384. }
  1385. }
  1386. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1387. {
  1388. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1389. if (IS_TV(intel_sdvo_connector))
  1390. intel_sdvo_get_tv_modes(connector);
  1391. else if (IS_LVDS(intel_sdvo_connector))
  1392. intel_sdvo_get_lvds_modes(connector);
  1393. else
  1394. intel_sdvo_get_ddc_modes(connector);
  1395. return !list_empty(&connector->probed_modes);
  1396. }
  1397. static void
  1398. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1399. {
  1400. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1401. struct drm_device *dev = connector->dev;
  1402. if (intel_sdvo_connector->left)
  1403. drm_property_destroy(dev, intel_sdvo_connector->left);
  1404. if (intel_sdvo_connector->right)
  1405. drm_property_destroy(dev, intel_sdvo_connector->right);
  1406. if (intel_sdvo_connector->top)
  1407. drm_property_destroy(dev, intel_sdvo_connector->top);
  1408. if (intel_sdvo_connector->bottom)
  1409. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1410. if (intel_sdvo_connector->hpos)
  1411. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1412. if (intel_sdvo_connector->vpos)
  1413. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1414. if (intel_sdvo_connector->saturation)
  1415. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1416. if (intel_sdvo_connector->contrast)
  1417. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1418. if (intel_sdvo_connector->hue)
  1419. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1420. if (intel_sdvo_connector->sharpness)
  1421. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1422. if (intel_sdvo_connector->flicker_filter)
  1423. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1424. if (intel_sdvo_connector->flicker_filter_2d)
  1425. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1426. if (intel_sdvo_connector->flicker_filter_adaptive)
  1427. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1428. if (intel_sdvo_connector->tv_luma_filter)
  1429. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1430. if (intel_sdvo_connector->tv_chroma_filter)
  1431. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1432. if (intel_sdvo_connector->dot_crawl)
  1433. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1434. if (intel_sdvo_connector->brightness)
  1435. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1436. }
  1437. static void intel_sdvo_destroy(struct drm_connector *connector)
  1438. {
  1439. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1440. if (intel_sdvo_connector->tv_format)
  1441. drm_property_destroy(connector->dev,
  1442. intel_sdvo_connector->tv_format);
  1443. intel_sdvo_destroy_enhance_property(connector);
  1444. drm_sysfs_connector_remove(connector);
  1445. drm_connector_cleanup(connector);
  1446. kfree(connector);
  1447. }
  1448. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1449. {
  1450. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1451. struct edid *edid;
  1452. bool has_audio = false;
  1453. if (!intel_sdvo->is_hdmi)
  1454. return false;
  1455. edid = intel_sdvo_get_edid(connector);
  1456. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1457. has_audio = drm_detect_monitor_audio(edid);
  1458. return has_audio;
  1459. }
  1460. static int
  1461. intel_sdvo_set_property(struct drm_connector *connector,
  1462. struct drm_property *property,
  1463. uint64_t val)
  1464. {
  1465. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1466. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1467. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1468. uint16_t temp_value;
  1469. uint8_t cmd;
  1470. int ret;
  1471. ret = drm_connector_property_set_value(connector, property, val);
  1472. if (ret)
  1473. return ret;
  1474. if (property == intel_sdvo_connector->force_audio_property) {
  1475. int i = val;
  1476. bool has_audio;
  1477. if (i == intel_sdvo_connector->force_audio)
  1478. return 0;
  1479. intel_sdvo_connector->force_audio = i;
  1480. if (i == 0)
  1481. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1482. else
  1483. has_audio = i > 0;
  1484. if (has_audio == intel_sdvo->has_hdmi_audio)
  1485. return 0;
  1486. intel_sdvo->has_hdmi_audio = has_audio;
  1487. goto done;
  1488. }
  1489. if (property == dev_priv->broadcast_rgb_property) {
  1490. if (val == !!intel_sdvo->color_range)
  1491. return 0;
  1492. intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1493. goto done;
  1494. }
  1495. #define CHECK_PROPERTY(name, NAME) \
  1496. if (intel_sdvo_connector->name == property) { \
  1497. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1498. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1499. cmd = SDVO_CMD_SET_##NAME; \
  1500. intel_sdvo_connector->cur_##name = temp_value; \
  1501. goto set_value; \
  1502. }
  1503. if (property == intel_sdvo_connector->tv_format) {
  1504. if (val >= TV_FORMAT_NUM)
  1505. return -EINVAL;
  1506. if (intel_sdvo->tv_format_index ==
  1507. intel_sdvo_connector->tv_format_supported[val])
  1508. return 0;
  1509. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1510. goto done;
  1511. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1512. temp_value = val;
  1513. if (intel_sdvo_connector->left == property) {
  1514. drm_connector_property_set_value(connector,
  1515. intel_sdvo_connector->right, val);
  1516. if (intel_sdvo_connector->left_margin == temp_value)
  1517. return 0;
  1518. intel_sdvo_connector->left_margin = temp_value;
  1519. intel_sdvo_connector->right_margin = temp_value;
  1520. temp_value = intel_sdvo_connector->max_hscan -
  1521. intel_sdvo_connector->left_margin;
  1522. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1523. goto set_value;
  1524. } else if (intel_sdvo_connector->right == property) {
  1525. drm_connector_property_set_value(connector,
  1526. intel_sdvo_connector->left, val);
  1527. if (intel_sdvo_connector->right_margin == temp_value)
  1528. return 0;
  1529. intel_sdvo_connector->left_margin = temp_value;
  1530. intel_sdvo_connector->right_margin = temp_value;
  1531. temp_value = intel_sdvo_connector->max_hscan -
  1532. intel_sdvo_connector->left_margin;
  1533. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1534. goto set_value;
  1535. } else if (intel_sdvo_connector->top == property) {
  1536. drm_connector_property_set_value(connector,
  1537. intel_sdvo_connector->bottom, val);
  1538. if (intel_sdvo_connector->top_margin == temp_value)
  1539. return 0;
  1540. intel_sdvo_connector->top_margin = temp_value;
  1541. intel_sdvo_connector->bottom_margin = temp_value;
  1542. temp_value = intel_sdvo_connector->max_vscan -
  1543. intel_sdvo_connector->top_margin;
  1544. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1545. goto set_value;
  1546. } else if (intel_sdvo_connector->bottom == property) {
  1547. drm_connector_property_set_value(connector,
  1548. intel_sdvo_connector->top, val);
  1549. if (intel_sdvo_connector->bottom_margin == temp_value)
  1550. return 0;
  1551. intel_sdvo_connector->top_margin = temp_value;
  1552. intel_sdvo_connector->bottom_margin = temp_value;
  1553. temp_value = intel_sdvo_connector->max_vscan -
  1554. intel_sdvo_connector->top_margin;
  1555. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1556. goto set_value;
  1557. }
  1558. CHECK_PROPERTY(hpos, HPOS)
  1559. CHECK_PROPERTY(vpos, VPOS)
  1560. CHECK_PROPERTY(saturation, SATURATION)
  1561. CHECK_PROPERTY(contrast, CONTRAST)
  1562. CHECK_PROPERTY(hue, HUE)
  1563. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1564. CHECK_PROPERTY(sharpness, SHARPNESS)
  1565. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1566. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1567. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1568. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1569. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1570. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1571. }
  1572. return -EINVAL; /* unknown property */
  1573. set_value:
  1574. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1575. return -EIO;
  1576. done:
  1577. if (intel_sdvo->base.base.crtc) {
  1578. struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
  1579. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1580. crtc->y, crtc->fb);
  1581. }
  1582. return 0;
  1583. #undef CHECK_PROPERTY
  1584. }
  1585. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1586. .dpms = intel_sdvo_dpms,
  1587. .mode_fixup = intel_sdvo_mode_fixup,
  1588. .prepare = intel_encoder_prepare,
  1589. .mode_set = intel_sdvo_mode_set,
  1590. .commit = intel_encoder_commit,
  1591. };
  1592. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1593. .dpms = drm_helper_connector_dpms,
  1594. .detect = intel_sdvo_detect,
  1595. .fill_modes = drm_helper_probe_single_connector_modes,
  1596. .set_property = intel_sdvo_set_property,
  1597. .destroy = intel_sdvo_destroy,
  1598. };
  1599. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1600. .get_modes = intel_sdvo_get_modes,
  1601. .mode_valid = intel_sdvo_mode_valid,
  1602. .best_encoder = intel_best_encoder,
  1603. };
  1604. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1605. {
  1606. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1607. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1608. drm_mode_destroy(encoder->dev,
  1609. intel_sdvo->sdvo_lvds_fixed_mode);
  1610. i2c_del_adapter(&intel_sdvo->ddc);
  1611. intel_encoder_destroy(encoder);
  1612. }
  1613. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1614. .destroy = intel_sdvo_enc_destroy,
  1615. };
  1616. static void
  1617. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1618. {
  1619. uint16_t mask = 0;
  1620. unsigned int num_bits;
  1621. /* Make a mask of outputs less than or equal to our own priority in the
  1622. * list.
  1623. */
  1624. switch (sdvo->controlled_output) {
  1625. case SDVO_OUTPUT_LVDS1:
  1626. mask |= SDVO_OUTPUT_LVDS1;
  1627. case SDVO_OUTPUT_LVDS0:
  1628. mask |= SDVO_OUTPUT_LVDS0;
  1629. case SDVO_OUTPUT_TMDS1:
  1630. mask |= SDVO_OUTPUT_TMDS1;
  1631. case SDVO_OUTPUT_TMDS0:
  1632. mask |= SDVO_OUTPUT_TMDS0;
  1633. case SDVO_OUTPUT_RGB1:
  1634. mask |= SDVO_OUTPUT_RGB1;
  1635. case SDVO_OUTPUT_RGB0:
  1636. mask |= SDVO_OUTPUT_RGB0;
  1637. break;
  1638. }
  1639. /* Count bits to find what number we are in the priority list. */
  1640. mask &= sdvo->caps.output_flags;
  1641. num_bits = hweight16(mask);
  1642. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1643. if (num_bits > 3)
  1644. num_bits = 3;
  1645. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1646. sdvo->ddc_bus = 1 << num_bits;
  1647. }
  1648. /**
  1649. * Choose the appropriate DDC bus for control bus switch command for this
  1650. * SDVO output based on the controlled output.
  1651. *
  1652. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1653. * outputs, then LVDS outputs.
  1654. */
  1655. static void
  1656. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1657. struct intel_sdvo *sdvo, u32 reg)
  1658. {
  1659. struct sdvo_device_mapping *mapping;
  1660. if (IS_SDVOB(reg))
  1661. mapping = &(dev_priv->sdvo_mappings[0]);
  1662. else
  1663. mapping = &(dev_priv->sdvo_mappings[1]);
  1664. if (mapping->initialized)
  1665. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1666. else
  1667. intel_sdvo_guess_ddc_bus(sdvo);
  1668. }
  1669. static void
  1670. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1671. struct intel_sdvo *sdvo, u32 reg)
  1672. {
  1673. struct sdvo_device_mapping *mapping;
  1674. u8 pin, speed;
  1675. if (IS_SDVOB(reg))
  1676. mapping = &dev_priv->sdvo_mappings[0];
  1677. else
  1678. mapping = &dev_priv->sdvo_mappings[1];
  1679. pin = GMBUS_PORT_DPB;
  1680. speed = GMBUS_RATE_1MHZ >> 8;
  1681. if (mapping->initialized) {
  1682. pin = mapping->i2c_pin;
  1683. speed = mapping->i2c_speed;
  1684. }
  1685. if (pin < GMBUS_NUM_PORTS) {
  1686. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1687. intel_gmbus_set_speed(sdvo->i2c, speed);
  1688. intel_gmbus_force_bit(sdvo->i2c, true);
  1689. } else
  1690. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1691. }
  1692. static bool
  1693. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1694. {
  1695. return intel_sdvo_check_supp_encode(intel_sdvo);
  1696. }
  1697. static u8
  1698. intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1699. {
  1700. struct drm_i915_private *dev_priv = dev->dev_private;
  1701. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1702. if (IS_SDVOB(sdvo_reg)) {
  1703. my_mapping = &dev_priv->sdvo_mappings[0];
  1704. other_mapping = &dev_priv->sdvo_mappings[1];
  1705. } else {
  1706. my_mapping = &dev_priv->sdvo_mappings[1];
  1707. other_mapping = &dev_priv->sdvo_mappings[0];
  1708. }
  1709. /* If the BIOS described our SDVO device, take advantage of it. */
  1710. if (my_mapping->slave_addr)
  1711. return my_mapping->slave_addr;
  1712. /* If the BIOS only described a different SDVO device, use the
  1713. * address that it isn't using.
  1714. */
  1715. if (other_mapping->slave_addr) {
  1716. if (other_mapping->slave_addr == 0x70)
  1717. return 0x72;
  1718. else
  1719. return 0x70;
  1720. }
  1721. /* No SDVO device info is found for another DVO port,
  1722. * so use mapping assumption we had before BIOS parsing.
  1723. */
  1724. if (IS_SDVOB(sdvo_reg))
  1725. return 0x70;
  1726. else
  1727. return 0x72;
  1728. }
  1729. static void
  1730. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1731. struct intel_sdvo *encoder)
  1732. {
  1733. drm_connector_init(encoder->base.base.dev,
  1734. &connector->base.base,
  1735. &intel_sdvo_connector_funcs,
  1736. connector->base.base.connector_type);
  1737. drm_connector_helper_add(&connector->base.base,
  1738. &intel_sdvo_connector_helper_funcs);
  1739. connector->base.base.interlace_allowed = 0;
  1740. connector->base.base.doublescan_allowed = 0;
  1741. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1742. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1743. drm_sysfs_connector_add(&connector->base.base);
  1744. }
  1745. static void
  1746. intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
  1747. {
  1748. struct drm_device *dev = connector->base.base.dev;
  1749. connector->force_audio_property =
  1750. drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2);
  1751. if (connector->force_audio_property) {
  1752. connector->force_audio_property->values[0] = -1;
  1753. connector->force_audio_property->values[1] = 1;
  1754. drm_connector_attach_property(&connector->base.base,
  1755. connector->force_audio_property, 0);
  1756. }
  1757. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
  1758. intel_attach_broadcast_rgb_property(&connector->base.base);
  1759. }
  1760. static bool
  1761. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1762. {
  1763. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1764. struct drm_connector *connector;
  1765. struct intel_connector *intel_connector;
  1766. struct intel_sdvo_connector *intel_sdvo_connector;
  1767. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1768. if (!intel_sdvo_connector)
  1769. return false;
  1770. if (device == 0) {
  1771. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1772. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1773. } else if (device == 1) {
  1774. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1775. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1776. }
  1777. intel_connector = &intel_sdvo_connector->base;
  1778. connector = &intel_connector->base;
  1779. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1780. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1781. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1782. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1783. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1784. intel_sdvo->is_hdmi = true;
  1785. }
  1786. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1787. (1 << INTEL_ANALOG_CLONE_BIT));
  1788. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1789. if (intel_sdvo->is_hdmi)
  1790. intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
  1791. return true;
  1792. }
  1793. static bool
  1794. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1795. {
  1796. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1797. struct drm_connector *connector;
  1798. struct intel_connector *intel_connector;
  1799. struct intel_sdvo_connector *intel_sdvo_connector;
  1800. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1801. if (!intel_sdvo_connector)
  1802. return false;
  1803. intel_connector = &intel_sdvo_connector->base;
  1804. connector = &intel_connector->base;
  1805. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1806. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1807. intel_sdvo->controlled_output |= type;
  1808. intel_sdvo_connector->output_flag = type;
  1809. intel_sdvo->is_tv = true;
  1810. intel_sdvo->base.needs_tv_clock = true;
  1811. intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1812. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1813. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1814. goto err;
  1815. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1816. goto err;
  1817. return true;
  1818. err:
  1819. intel_sdvo_destroy(connector);
  1820. return false;
  1821. }
  1822. static bool
  1823. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1824. {
  1825. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1826. struct drm_connector *connector;
  1827. struct intel_connector *intel_connector;
  1828. struct intel_sdvo_connector *intel_sdvo_connector;
  1829. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1830. if (!intel_sdvo_connector)
  1831. return false;
  1832. intel_connector = &intel_sdvo_connector->base;
  1833. connector = &intel_connector->base;
  1834. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1835. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1836. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1837. if (device == 0) {
  1838. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1839. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1840. } else if (device == 1) {
  1841. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1842. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1843. }
  1844. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1845. (1 << INTEL_ANALOG_CLONE_BIT));
  1846. intel_sdvo_connector_init(intel_sdvo_connector,
  1847. intel_sdvo);
  1848. return true;
  1849. }
  1850. static bool
  1851. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  1852. {
  1853. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1854. struct drm_connector *connector;
  1855. struct intel_connector *intel_connector;
  1856. struct intel_sdvo_connector *intel_sdvo_connector;
  1857. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1858. if (!intel_sdvo_connector)
  1859. return false;
  1860. intel_connector = &intel_sdvo_connector->base;
  1861. connector = &intel_connector->base;
  1862. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1863. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1864. if (device == 0) {
  1865. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1866. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1867. } else if (device == 1) {
  1868. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1869. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1870. }
  1871. intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1872. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1873. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1874. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1875. goto err;
  1876. return true;
  1877. err:
  1878. intel_sdvo_destroy(connector);
  1879. return false;
  1880. }
  1881. static bool
  1882. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  1883. {
  1884. intel_sdvo->is_tv = false;
  1885. intel_sdvo->base.needs_tv_clock = false;
  1886. intel_sdvo->is_lvds = false;
  1887. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1888. if (flags & SDVO_OUTPUT_TMDS0)
  1889. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  1890. return false;
  1891. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1892. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  1893. return false;
  1894. /* TV has no XXX1 function block */
  1895. if (flags & SDVO_OUTPUT_SVID0)
  1896. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  1897. return false;
  1898. if (flags & SDVO_OUTPUT_CVBS0)
  1899. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  1900. return false;
  1901. if (flags & SDVO_OUTPUT_RGB0)
  1902. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  1903. return false;
  1904. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1905. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  1906. return false;
  1907. if (flags & SDVO_OUTPUT_LVDS0)
  1908. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  1909. return false;
  1910. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1911. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  1912. return false;
  1913. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1914. unsigned char bytes[2];
  1915. intel_sdvo->controlled_output = 0;
  1916. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  1917. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1918. SDVO_NAME(intel_sdvo),
  1919. bytes[0], bytes[1]);
  1920. return false;
  1921. }
  1922. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
  1923. return true;
  1924. }
  1925. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  1926. struct intel_sdvo_connector *intel_sdvo_connector,
  1927. int type)
  1928. {
  1929. struct drm_device *dev = intel_sdvo->base.base.dev;
  1930. struct intel_sdvo_tv_format format;
  1931. uint32_t format_map, i;
  1932. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  1933. return false;
  1934. BUILD_BUG_ON(sizeof(format) != 6);
  1935. if (!intel_sdvo_get_value(intel_sdvo,
  1936. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1937. &format, sizeof(format)))
  1938. return false;
  1939. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1940. if (format_map == 0)
  1941. return false;
  1942. intel_sdvo_connector->format_supported_num = 0;
  1943. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1944. if (format_map & (1 << i))
  1945. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  1946. intel_sdvo_connector->tv_format =
  1947. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1948. "mode", intel_sdvo_connector->format_supported_num);
  1949. if (!intel_sdvo_connector->tv_format)
  1950. return false;
  1951. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  1952. drm_property_add_enum(
  1953. intel_sdvo_connector->tv_format, i,
  1954. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  1955. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  1956. drm_connector_attach_property(&intel_sdvo_connector->base.base,
  1957. intel_sdvo_connector->tv_format, 0);
  1958. return true;
  1959. }
  1960. #define ENHANCEMENT(name, NAME) do { \
  1961. if (enhancements.name) { \
  1962. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1963. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1964. return false; \
  1965. intel_sdvo_connector->max_##name = data_value[0]; \
  1966. intel_sdvo_connector->cur_##name = response; \
  1967. intel_sdvo_connector->name = \
  1968. drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
  1969. if (!intel_sdvo_connector->name) return false; \
  1970. intel_sdvo_connector->name->values[0] = 0; \
  1971. intel_sdvo_connector->name->values[1] = data_value[0]; \
  1972. drm_connector_attach_property(connector, \
  1973. intel_sdvo_connector->name, \
  1974. intel_sdvo_connector->cur_##name); \
  1975. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1976. data_value[0], data_value[1], response); \
  1977. } \
  1978. } while(0)
  1979. static bool
  1980. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  1981. struct intel_sdvo_connector *intel_sdvo_connector,
  1982. struct intel_sdvo_enhancements_reply enhancements)
  1983. {
  1984. struct drm_device *dev = intel_sdvo->base.base.dev;
  1985. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  1986. uint16_t response, data_value[2];
  1987. /* when horizontal overscan is supported, Add the left/right property */
  1988. if (enhancements.overscan_h) {
  1989. if (!intel_sdvo_get_value(intel_sdvo,
  1990. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1991. &data_value, 4))
  1992. return false;
  1993. if (!intel_sdvo_get_value(intel_sdvo,
  1994. SDVO_CMD_GET_OVERSCAN_H,
  1995. &response, 2))
  1996. return false;
  1997. intel_sdvo_connector->max_hscan = data_value[0];
  1998. intel_sdvo_connector->left_margin = data_value[0] - response;
  1999. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2000. intel_sdvo_connector->left =
  2001. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2002. "left_margin", 2);
  2003. if (!intel_sdvo_connector->left)
  2004. return false;
  2005. intel_sdvo_connector->left->values[0] = 0;
  2006. intel_sdvo_connector->left->values[1] = data_value[0];
  2007. drm_connector_attach_property(connector,
  2008. intel_sdvo_connector->left,
  2009. intel_sdvo_connector->left_margin);
  2010. intel_sdvo_connector->right =
  2011. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2012. "right_margin", 2);
  2013. if (!intel_sdvo_connector->right)
  2014. return false;
  2015. intel_sdvo_connector->right->values[0] = 0;
  2016. intel_sdvo_connector->right->values[1] = data_value[0];
  2017. drm_connector_attach_property(connector,
  2018. intel_sdvo_connector->right,
  2019. intel_sdvo_connector->right_margin);
  2020. DRM_DEBUG_KMS("h_overscan: max %d, "
  2021. "default %d, current %d\n",
  2022. data_value[0], data_value[1], response);
  2023. }
  2024. if (enhancements.overscan_v) {
  2025. if (!intel_sdvo_get_value(intel_sdvo,
  2026. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2027. &data_value, 4))
  2028. return false;
  2029. if (!intel_sdvo_get_value(intel_sdvo,
  2030. SDVO_CMD_GET_OVERSCAN_V,
  2031. &response, 2))
  2032. return false;
  2033. intel_sdvo_connector->max_vscan = data_value[0];
  2034. intel_sdvo_connector->top_margin = data_value[0] - response;
  2035. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2036. intel_sdvo_connector->top =
  2037. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2038. "top_margin", 2);
  2039. if (!intel_sdvo_connector->top)
  2040. return false;
  2041. intel_sdvo_connector->top->values[0] = 0;
  2042. intel_sdvo_connector->top->values[1] = data_value[0];
  2043. drm_connector_attach_property(connector,
  2044. intel_sdvo_connector->top,
  2045. intel_sdvo_connector->top_margin);
  2046. intel_sdvo_connector->bottom =
  2047. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2048. "bottom_margin", 2);
  2049. if (!intel_sdvo_connector->bottom)
  2050. return false;
  2051. intel_sdvo_connector->bottom->values[0] = 0;
  2052. intel_sdvo_connector->bottom->values[1] = data_value[0];
  2053. drm_connector_attach_property(connector,
  2054. intel_sdvo_connector->bottom,
  2055. intel_sdvo_connector->bottom_margin);
  2056. DRM_DEBUG_KMS("v_overscan: max %d, "
  2057. "default %d, current %d\n",
  2058. data_value[0], data_value[1], response);
  2059. }
  2060. ENHANCEMENT(hpos, HPOS);
  2061. ENHANCEMENT(vpos, VPOS);
  2062. ENHANCEMENT(saturation, SATURATION);
  2063. ENHANCEMENT(contrast, CONTRAST);
  2064. ENHANCEMENT(hue, HUE);
  2065. ENHANCEMENT(sharpness, SHARPNESS);
  2066. ENHANCEMENT(brightness, BRIGHTNESS);
  2067. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2068. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2069. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2070. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2071. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2072. if (enhancements.dot_crawl) {
  2073. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2074. return false;
  2075. intel_sdvo_connector->max_dot_crawl = 1;
  2076. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2077. intel_sdvo_connector->dot_crawl =
  2078. drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
  2079. if (!intel_sdvo_connector->dot_crawl)
  2080. return false;
  2081. intel_sdvo_connector->dot_crawl->values[0] = 0;
  2082. intel_sdvo_connector->dot_crawl->values[1] = 1;
  2083. drm_connector_attach_property(connector,
  2084. intel_sdvo_connector->dot_crawl,
  2085. intel_sdvo_connector->cur_dot_crawl);
  2086. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2087. }
  2088. return true;
  2089. }
  2090. static bool
  2091. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2092. struct intel_sdvo_connector *intel_sdvo_connector,
  2093. struct intel_sdvo_enhancements_reply enhancements)
  2094. {
  2095. struct drm_device *dev = intel_sdvo->base.base.dev;
  2096. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2097. uint16_t response, data_value[2];
  2098. ENHANCEMENT(brightness, BRIGHTNESS);
  2099. return true;
  2100. }
  2101. #undef ENHANCEMENT
  2102. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2103. struct intel_sdvo_connector *intel_sdvo_connector)
  2104. {
  2105. union {
  2106. struct intel_sdvo_enhancements_reply reply;
  2107. uint16_t response;
  2108. } enhancements;
  2109. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2110. enhancements.response = 0;
  2111. intel_sdvo_get_value(intel_sdvo,
  2112. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2113. &enhancements, sizeof(enhancements));
  2114. if (enhancements.response == 0) {
  2115. DRM_DEBUG_KMS("No enhancement is supported\n");
  2116. return true;
  2117. }
  2118. if (IS_TV(intel_sdvo_connector))
  2119. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2120. else if(IS_LVDS(intel_sdvo_connector))
  2121. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2122. else
  2123. return true;
  2124. }
  2125. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2126. struct i2c_msg *msgs,
  2127. int num)
  2128. {
  2129. struct intel_sdvo *sdvo = adapter->algo_data;
  2130. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2131. return -EIO;
  2132. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2133. }
  2134. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2135. {
  2136. struct intel_sdvo *sdvo = adapter->algo_data;
  2137. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2138. }
  2139. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2140. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2141. .functionality = intel_sdvo_ddc_proxy_func
  2142. };
  2143. static bool
  2144. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2145. struct drm_device *dev)
  2146. {
  2147. sdvo->ddc.owner = THIS_MODULE;
  2148. sdvo->ddc.class = I2C_CLASS_DDC;
  2149. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2150. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2151. sdvo->ddc.algo_data = sdvo;
  2152. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2153. return i2c_add_adapter(&sdvo->ddc) == 0;
  2154. }
  2155. bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2156. {
  2157. struct drm_i915_private *dev_priv = dev->dev_private;
  2158. struct intel_encoder *intel_encoder;
  2159. struct intel_sdvo *intel_sdvo;
  2160. int i;
  2161. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2162. if (!intel_sdvo)
  2163. return false;
  2164. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
  2165. kfree(intel_sdvo);
  2166. return false;
  2167. }
  2168. intel_sdvo->sdvo_reg = sdvo_reg;
  2169. intel_encoder = &intel_sdvo->base;
  2170. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2171. /* encoder type will be decided later */
  2172. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2173. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2174. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2175. /* Read the regs to test if we can talk to the device */
  2176. for (i = 0; i < 0x40; i++) {
  2177. u8 byte;
  2178. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2179. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2180. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2181. goto err;
  2182. }
  2183. }
  2184. if (IS_SDVOB(sdvo_reg))
  2185. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2186. else
  2187. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2188. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2189. /* In default case sdvo lvds is false */
  2190. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2191. goto err;
  2192. if (intel_sdvo_output_setup(intel_sdvo,
  2193. intel_sdvo->caps.output_flags) != true) {
  2194. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2195. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2196. goto err;
  2197. }
  2198. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2199. /* Set the input timing to the screen. Assume always input 0. */
  2200. if (!intel_sdvo_set_target_input(intel_sdvo))
  2201. goto err;
  2202. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2203. &intel_sdvo->pixel_clock_min,
  2204. &intel_sdvo->pixel_clock_max))
  2205. goto err;
  2206. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2207. "clock range %dMHz - %dMHz, "
  2208. "input 1: %c, input 2: %c, "
  2209. "output 1: %c, output 2: %c\n",
  2210. SDVO_NAME(intel_sdvo),
  2211. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2212. intel_sdvo->caps.device_rev_id,
  2213. intel_sdvo->pixel_clock_min / 1000,
  2214. intel_sdvo->pixel_clock_max / 1000,
  2215. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2216. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2217. /* check currently supported outputs */
  2218. intel_sdvo->caps.output_flags &
  2219. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2220. intel_sdvo->caps.output_flags &
  2221. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2222. return true;
  2223. err:
  2224. drm_encoder_cleanup(&intel_encoder->base);
  2225. i2c_del_adapter(&intel_sdvo->ddc);
  2226. kfree(intel_sdvo);
  2227. return false;
  2228. }