intel_ringbuffer.h 5.8 KB

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  1. #ifndef _INTEL_RINGBUFFER_H_
  2. #define _INTEL_RINGBUFFER_H_
  3. enum {
  4. RCS = 0x0,
  5. VCS,
  6. BCS,
  7. I915_NUM_RINGS,
  8. };
  9. struct intel_hw_status_page {
  10. u32 __iomem *page_addr;
  11. unsigned int gfx_addr;
  12. struct drm_i915_gem_object *obj;
  13. };
  14. #define I915_RING_READ(reg) i915_gt_read(dev_priv, reg)
  15. #define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val)
  16. #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
  17. #define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val)
  18. #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
  19. #define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val)
  20. #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base))
  21. #define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val)
  22. #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
  23. #define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val)
  24. #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
  25. #define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val)
  26. #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
  27. #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
  28. #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
  29. struct intel_ring_buffer {
  30. const char *name;
  31. enum intel_ring_id {
  32. RING_RENDER = 0x1,
  33. RING_BSD = 0x2,
  34. RING_BLT = 0x4,
  35. } id;
  36. u32 mmio_base;
  37. void __iomem *virtual_start;
  38. struct drm_device *dev;
  39. struct drm_i915_gem_object *obj;
  40. u32 head;
  41. u32 tail;
  42. int space;
  43. int size;
  44. int effective_size;
  45. struct intel_hw_status_page status_page;
  46. spinlock_t irq_lock;
  47. u32 irq_refcount;
  48. u32 irq_mask;
  49. u32 irq_seqno; /* last seq seem at irq time */
  50. u32 trace_irq_seqno;
  51. u32 waiting_seqno;
  52. u32 sync_seqno[I915_NUM_RINGS-1];
  53. bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  54. void (*irq_put)(struct intel_ring_buffer *ring);
  55. int (*init)(struct intel_ring_buffer *ring);
  56. void (*write_tail)(struct intel_ring_buffer *ring,
  57. u32 value);
  58. int __must_check (*flush)(struct intel_ring_buffer *ring,
  59. u32 invalidate_domains,
  60. u32 flush_domains);
  61. int (*add_request)(struct intel_ring_buffer *ring,
  62. u32 *seqno);
  63. u32 (*get_seqno)(struct intel_ring_buffer *ring);
  64. int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
  65. u32 offset, u32 length);
  66. void (*cleanup)(struct intel_ring_buffer *ring);
  67. /**
  68. * List of objects currently involved in rendering from the
  69. * ringbuffer.
  70. *
  71. * Includes buffers having the contents of their GPU caches
  72. * flushed, not necessarily primitives. last_rendering_seqno
  73. * represents when the rendering involved will be completed.
  74. *
  75. * A reference is held on the buffer while on this list.
  76. */
  77. struct list_head active_list;
  78. /**
  79. * List of breadcrumbs associated with GPU requests currently
  80. * outstanding.
  81. */
  82. struct list_head request_list;
  83. /**
  84. * List of objects currently pending a GPU write flush.
  85. *
  86. * All elements on this list will belong to either the
  87. * active_list or flushing_list, last_rendering_seqno can
  88. * be used to differentiate between the two elements.
  89. */
  90. struct list_head gpu_write_list;
  91. /**
  92. * Do we have some not yet emitted requests outstanding?
  93. */
  94. u32 outstanding_lazy_request;
  95. wait_queue_head_t irq_queue;
  96. drm_local_map_t map;
  97. void *private;
  98. };
  99. static inline u32
  100. intel_ring_sync_index(struct intel_ring_buffer *ring,
  101. struct intel_ring_buffer *other)
  102. {
  103. int idx;
  104. /*
  105. * cs -> 0 = vcs, 1 = bcs
  106. * vcs -> 0 = bcs, 1 = cs,
  107. * bcs -> 0 = cs, 1 = vcs.
  108. */
  109. idx = (other - ring) - 1;
  110. if (idx < 0)
  111. idx += I915_NUM_RINGS;
  112. return idx;
  113. }
  114. static inline u32
  115. intel_read_status_page(struct intel_ring_buffer *ring,
  116. int reg)
  117. {
  118. return ioread32(ring->status_page.page_addr + reg);
  119. }
  120. /**
  121. * Reads a dword out of the status page, which is written to from the command
  122. * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
  123. * MI_STORE_DATA_IMM.
  124. *
  125. * The following dwords have a reserved meaning:
  126. * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
  127. * 0x04: ring 0 head pointer
  128. * 0x05: ring 1 head pointer (915-class)
  129. * 0x06: ring 2 head pointer (915-class)
  130. * 0x10-0x1b: Context status DWords (GM45)
  131. * 0x1f: Last written status offset. (GM45)
  132. *
  133. * The area from dword 0x20 to 0x3ff is available for driver usage.
  134. */
  135. #define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
  136. #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  137. #define I915_GEM_HWS_INDEX 0x20
  138. #define I915_BREADCRUMB_INDEX 0x21
  139. void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
  140. int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
  141. int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
  142. static inline void intel_ring_emit(struct intel_ring_buffer *ring,
  143. u32 data)
  144. {
  145. iowrite32(data, ring->virtual_start + ring->tail);
  146. ring->tail += 4;
  147. }
  148. void intel_ring_advance(struct intel_ring_buffer *ring);
  149. u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
  150. int intel_ring_sync(struct intel_ring_buffer *ring,
  151. struct intel_ring_buffer *to,
  152. u32 seqno);
  153. int intel_init_render_ring_buffer(struct drm_device *dev);
  154. int intel_init_bsd_ring_buffer(struct drm_device *dev);
  155. int intel_init_blt_ring_buffer(struct drm_device *dev);
  156. u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
  157. void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
  158. static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
  159. {
  160. if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
  161. ring->trace_irq_seqno = seqno;
  162. }
  163. /* DRI warts */
  164. int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
  165. #endif /* _INTEL_RINGBUFFER_H_ */