ml_ioh_gpio.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/pci.h>
  19. #include <linux/gpio.h>
  20. #define PCI_VENDOR_ID_ROHM 0x10DB
  21. struct ioh_reg_comn {
  22. u32 ien;
  23. u32 istatus;
  24. u32 idisp;
  25. u32 iclr;
  26. u32 imask;
  27. u32 imaskclr;
  28. u32 po;
  29. u32 pi;
  30. u32 pm;
  31. u32 im_0;
  32. u32 im_1;
  33. u32 reserved;
  34. };
  35. struct ioh_regs {
  36. struct ioh_reg_comn regs[8];
  37. u32 reserve1[16];
  38. u32 ioh_sel_reg[4];
  39. u32 reserve2[11];
  40. u32 srst;
  41. };
  42. /**
  43. * struct ioh_gpio_reg_data - The register store data.
  44. * @po_reg: To store contents of PO register.
  45. * @pm_reg: To store contents of PM register.
  46. */
  47. struct ioh_gpio_reg_data {
  48. u32 po_reg;
  49. u32 pm_reg;
  50. };
  51. /**
  52. * struct ioh_gpio - GPIO private data structure.
  53. * @base: PCI base address of Memory mapped I/O register.
  54. * @reg: Memory mapped IOH GPIO register list.
  55. * @dev: Pointer to device structure.
  56. * @gpio: Data for GPIO infrastructure.
  57. * @ioh_gpio_reg: Memory mapped Register data is saved here
  58. * when suspend.
  59. * @ch: Indicate GPIO channel
  60. */
  61. struct ioh_gpio {
  62. void __iomem *base;
  63. struct ioh_regs __iomem *reg;
  64. struct device *dev;
  65. struct gpio_chip gpio;
  66. struct ioh_gpio_reg_data ioh_gpio_reg;
  67. struct mutex lock;
  68. int ch;
  69. };
  70. static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
  71. static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
  72. {
  73. u32 reg_val;
  74. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  75. mutex_lock(&chip->lock);
  76. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  77. if (val)
  78. reg_val |= (1 << nr);
  79. else
  80. reg_val &= ~(1 << nr);
  81. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  82. mutex_unlock(&chip->lock);
  83. }
  84. static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
  85. {
  86. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  87. return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
  88. }
  89. static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
  90. int val)
  91. {
  92. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  93. u32 pm;
  94. u32 reg_val;
  95. mutex_lock(&chip->lock);
  96. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  97. ((1 << num_ports[chip->ch]) - 1);
  98. pm |= (1 << nr);
  99. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  100. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  101. if (val)
  102. reg_val |= (1 << nr);
  103. else
  104. reg_val &= ~(1 << nr);
  105. mutex_unlock(&chip->lock);
  106. return 0;
  107. }
  108. static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  109. {
  110. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  111. u32 pm;
  112. mutex_lock(&chip->lock);
  113. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  114. ((1 << num_ports[chip->ch]) - 1);
  115. pm &= ~(1 << nr);
  116. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  117. mutex_unlock(&chip->lock);
  118. return 0;
  119. }
  120. /*
  121. * Save register configuration and disable interrupts.
  122. */
  123. static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
  124. {
  125. chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
  126. chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
  127. }
  128. /*
  129. * This function restores the register configuration of the GPIO device.
  130. */
  131. static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
  132. {
  133. /* to store contents of PO register */
  134. iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
  135. /* to store contents of PM register */
  136. iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
  137. }
  138. static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
  139. {
  140. struct gpio_chip *gpio = &chip->gpio;
  141. gpio->label = dev_name(chip->dev);
  142. gpio->owner = THIS_MODULE;
  143. gpio->direction_input = ioh_gpio_direction_input;
  144. gpio->get = ioh_gpio_get;
  145. gpio->direction_output = ioh_gpio_direction_output;
  146. gpio->set = ioh_gpio_set;
  147. gpio->dbg_show = NULL;
  148. gpio->base = -1;
  149. gpio->ngpio = num_port;
  150. gpio->can_sleep = 0;
  151. }
  152. static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
  153. const struct pci_device_id *id)
  154. {
  155. int ret;
  156. int i;
  157. struct ioh_gpio *chip;
  158. void __iomem *base;
  159. void __iomem *chip_save;
  160. ret = pci_enable_device(pdev);
  161. if (ret) {
  162. dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
  163. goto err_pci_enable;
  164. }
  165. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  166. if (ret) {
  167. dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
  168. goto err_request_regions;
  169. }
  170. base = pci_iomap(pdev, 1, 0);
  171. if (base == 0) {
  172. dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
  173. ret = -ENOMEM;
  174. goto err_iomap;
  175. }
  176. chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
  177. if (chip_save == NULL) {
  178. dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
  179. ret = -ENOMEM;
  180. goto err_kzalloc;
  181. }
  182. chip = chip_save;
  183. for (i = 0; i < 8; i++, chip++) {
  184. chip->dev = &pdev->dev;
  185. chip->base = base;
  186. chip->reg = chip->base;
  187. chip->ch = i;
  188. mutex_init(&chip->lock);
  189. ioh_gpio_setup(chip, num_ports[i]);
  190. ret = gpiochip_add(&chip->gpio);
  191. if (ret) {
  192. dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
  193. goto err_gpiochip_add;
  194. }
  195. }
  196. chip = chip_save;
  197. pci_set_drvdata(pdev, chip);
  198. return 0;
  199. err_gpiochip_add:
  200. for (; i != 0; i--) {
  201. chip--;
  202. ret = gpiochip_remove(&chip->gpio);
  203. if (ret)
  204. dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
  205. }
  206. kfree(chip_save);
  207. err_kzalloc:
  208. pci_iounmap(pdev, base);
  209. err_iomap:
  210. pci_release_regions(pdev);
  211. err_request_regions:
  212. pci_disable_device(pdev);
  213. err_pci_enable:
  214. dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
  215. return ret;
  216. }
  217. static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
  218. {
  219. int err;
  220. int i;
  221. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  222. void __iomem *chip_save;
  223. chip_save = chip;
  224. for (i = 0; i < 8; i++, chip++) {
  225. err = gpiochip_remove(&chip->gpio);
  226. if (err)
  227. dev_err(&pdev->dev, "Failed gpiochip_remove\n");
  228. }
  229. chip = chip_save;
  230. pci_iounmap(pdev, chip->base);
  231. pci_release_regions(pdev);
  232. pci_disable_device(pdev);
  233. kfree(chip);
  234. }
  235. #ifdef CONFIG_PM
  236. static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
  237. {
  238. s32 ret;
  239. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  240. ioh_gpio_save_reg_conf(chip);
  241. ioh_gpio_restore_reg_conf(chip);
  242. ret = pci_save_state(pdev);
  243. if (ret) {
  244. dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
  245. return ret;
  246. }
  247. pci_disable_device(pdev);
  248. pci_set_power_state(pdev, PCI_D0);
  249. ret = pci_enable_wake(pdev, PCI_D0, 1);
  250. if (ret)
  251. dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
  252. return 0;
  253. }
  254. static int ioh_gpio_resume(struct pci_dev *pdev)
  255. {
  256. s32 ret;
  257. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  258. ret = pci_enable_wake(pdev, PCI_D0, 0);
  259. pci_set_power_state(pdev, PCI_D0);
  260. ret = pci_enable_device(pdev);
  261. if (ret) {
  262. dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
  263. return ret;
  264. }
  265. pci_restore_state(pdev);
  266. iowrite32(0x01, &chip->reg->srst);
  267. iowrite32(0x00, &chip->reg->srst);
  268. ioh_gpio_restore_reg_conf(chip);
  269. return 0;
  270. }
  271. #else
  272. #define ioh_gpio_suspend NULL
  273. #define ioh_gpio_resume NULL
  274. #endif
  275. static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
  276. { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
  277. { 0, }
  278. };
  279. MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
  280. static struct pci_driver ioh_gpio_driver = {
  281. .name = "ml_ioh_gpio",
  282. .id_table = ioh_gpio_pcidev_id,
  283. .probe = ioh_gpio_probe,
  284. .remove = __devexit_p(ioh_gpio_remove),
  285. .suspend = ioh_gpio_suspend,
  286. .resume = ioh_gpio_resume
  287. };
  288. static int __init ioh_gpio_pci_init(void)
  289. {
  290. return pci_register_driver(&ioh_gpio_driver);
  291. }
  292. module_init(ioh_gpio_pci_init);
  293. static void __exit ioh_gpio_pci_exit(void)
  294. {
  295. pci_unregister_driver(&ioh_gpio_driver);
  296. }
  297. module_exit(ioh_gpio_pci_exit);
  298. MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
  299. MODULE_LICENSE("GPL");