umem.c 29 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123
  1. /*
  2. * mm.c - Micro Memory(tm) PCI memory board block device driver - v2.3
  3. *
  4. * (C) 2001 San Mehat <nettwerk@valinux.com>
  5. * (C) 2001 Johannes Erdfelt <jerdfelt@valinux.com>
  6. * (C) 2001 NeilBrown <neilb@cse.unsw.edu.au>
  7. *
  8. * This driver for the Micro Memory PCI Memory Module with Battery Backup
  9. * is Copyright Micro Memory Inc 2001-2002. All rights reserved.
  10. *
  11. * This driver is released to the public under the terms of the
  12. * GNU GENERAL PUBLIC LICENSE version 2
  13. * See the file COPYING for details.
  14. *
  15. * This driver provides a standard block device interface for Micro Memory(tm)
  16. * PCI based RAM boards.
  17. * 10/05/01: Phap Nguyen - Rebuilt the driver
  18. * 10/22/01: Phap Nguyen - v2.1 Added disk partitioning
  19. * 29oct2001:NeilBrown - Use make_request_fn instead of request_fn
  20. * - use stand disk partitioning (so fdisk works).
  21. * 08nov2001:NeilBrown - change driver name from "mm" to "umem"
  22. * - incorporate into main kernel
  23. * 08apr2002:NeilBrown - Move some of interrupt handle to tasklet
  24. * - use spin_lock_bh instead of _irq
  25. * - Never block on make_request. queue
  26. * bh's instead.
  27. * - unregister umem from devfs at mod unload
  28. * - Change version to 2.3
  29. * 07Nov2001:Phap Nguyen - Select pci read command: 06, 12, 15 (Decimal)
  30. * 07Jan2002: P. Nguyen - Used PCI Memory Write & Invalidate for DMA
  31. * 15May2002:NeilBrown - convert to bio for 2.5
  32. * 17May2002:NeilBrown - remove init_mem initialisation. Instead detect
  33. * - a sequence of writes that cover the card, and
  34. * - set initialised bit then.
  35. */
  36. #undef DEBUG /* #define DEBUG if you want debugging info (pr_debug) */
  37. #include <linux/fs.h>
  38. #include <linux/bio.h>
  39. #include <linux/kernel.h>
  40. #include <linux/mm.h>
  41. #include <linux/mman.h>
  42. #include <linux/gfp.h>
  43. #include <linux/ioctl.h>
  44. #include <linux/module.h>
  45. #include <linux/init.h>
  46. #include <linux/interrupt.h>
  47. #include <linux/timer.h>
  48. #include <linux/pci.h>
  49. #include <linux/dma-mapping.h>
  50. #include <linux/fcntl.h> /* O_ACCMODE */
  51. #include <linux/hdreg.h> /* HDIO_GETGEO */
  52. #include "umem.h"
  53. #include <asm/uaccess.h>
  54. #include <asm/io.h>
  55. #define MM_MAXCARDS 4
  56. #define MM_RAHEAD 2 /* two sectors */
  57. #define MM_BLKSIZE 1024 /* 1k blocks */
  58. #define MM_HARDSECT 512 /* 512-byte hardware sectors */
  59. #define MM_SHIFT 6 /* max 64 partitions on 4 cards */
  60. /*
  61. * Version Information
  62. */
  63. #define DRIVER_NAME "umem"
  64. #define DRIVER_VERSION "v2.3"
  65. #define DRIVER_AUTHOR "San Mehat, Johannes Erdfelt, NeilBrown"
  66. #define DRIVER_DESC "Micro Memory(tm) PCI memory board block driver"
  67. static int debug;
  68. /* #define HW_TRACE(x) writeb(x,cards[0].csr_remap + MEMCTRLSTATUS_MAGIC) */
  69. #define HW_TRACE(x)
  70. #define DEBUG_LED_ON_TRANSFER 0x01
  71. #define DEBUG_BATTERY_POLLING 0x02
  72. module_param(debug, int, 0644);
  73. MODULE_PARM_DESC(debug, "Debug bitmask");
  74. static int pci_read_cmd = 0x0C; /* Read Multiple */
  75. module_param(pci_read_cmd, int, 0);
  76. MODULE_PARM_DESC(pci_read_cmd, "PCI read command");
  77. static int pci_write_cmd = 0x0F; /* Write and Invalidate */
  78. module_param(pci_write_cmd, int, 0);
  79. MODULE_PARM_DESC(pci_write_cmd, "PCI write command");
  80. static int pci_cmds;
  81. static int major_nr;
  82. #include <linux/blkdev.h>
  83. #include <linux/blkpg.h>
  84. struct cardinfo {
  85. struct pci_dev *dev;
  86. unsigned char __iomem *csr_remap;
  87. unsigned int mm_size; /* size in kbytes */
  88. unsigned int init_size; /* initial segment, in sectors,
  89. * that we know to
  90. * have been written
  91. */
  92. struct bio *bio, *currentbio, **biotail;
  93. int current_idx;
  94. sector_t current_sector;
  95. struct request_queue *queue;
  96. struct mm_page {
  97. dma_addr_t page_dma;
  98. struct mm_dma_desc *desc;
  99. int cnt, headcnt;
  100. struct bio *bio, **biotail;
  101. int idx;
  102. } mm_pages[2];
  103. #define DESC_PER_PAGE ((PAGE_SIZE*2)/sizeof(struct mm_dma_desc))
  104. int Active, Ready;
  105. struct tasklet_struct tasklet;
  106. unsigned int dma_status;
  107. struct {
  108. int good;
  109. int warned;
  110. unsigned long last_change;
  111. } battery[2];
  112. spinlock_t lock;
  113. int check_batteries;
  114. int flags;
  115. };
  116. static struct cardinfo cards[MM_MAXCARDS];
  117. static struct timer_list battery_timer;
  118. static int num_cards;
  119. static struct gendisk *mm_gendisk[MM_MAXCARDS];
  120. static void check_batteries(struct cardinfo *card);
  121. static int get_userbit(struct cardinfo *card, int bit)
  122. {
  123. unsigned char led;
  124. led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
  125. return led & bit;
  126. }
  127. static int set_userbit(struct cardinfo *card, int bit, unsigned char state)
  128. {
  129. unsigned char led;
  130. led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
  131. if (state)
  132. led |= bit;
  133. else
  134. led &= ~bit;
  135. writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL);
  136. return 0;
  137. }
  138. /*
  139. * NOTE: For the power LED, use the LED_POWER_* macros since they differ
  140. */
  141. static void set_led(struct cardinfo *card, int shift, unsigned char state)
  142. {
  143. unsigned char led;
  144. led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
  145. if (state == LED_FLIP)
  146. led ^= (1<<shift);
  147. else {
  148. led &= ~(0x03 << shift);
  149. led |= (state << shift);
  150. }
  151. writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL);
  152. }
  153. #ifdef MM_DIAG
  154. static void dump_regs(struct cardinfo *card)
  155. {
  156. unsigned char *p;
  157. int i, i1;
  158. p = card->csr_remap;
  159. for (i = 0; i < 8; i++) {
  160. printk(KERN_DEBUG "%p ", p);
  161. for (i1 = 0; i1 < 16; i1++)
  162. printk("%02x ", *p++);
  163. printk("\n");
  164. }
  165. }
  166. #endif
  167. static void dump_dmastat(struct cardinfo *card, unsigned int dmastat)
  168. {
  169. dev_printk(KERN_DEBUG, &card->dev->dev, "DMAstat - ");
  170. if (dmastat & DMASCR_ANY_ERR)
  171. printk(KERN_CONT "ANY_ERR ");
  172. if (dmastat & DMASCR_MBE_ERR)
  173. printk(KERN_CONT "MBE_ERR ");
  174. if (dmastat & DMASCR_PARITY_ERR_REP)
  175. printk(KERN_CONT "PARITY_ERR_REP ");
  176. if (dmastat & DMASCR_PARITY_ERR_DET)
  177. printk(KERN_CONT "PARITY_ERR_DET ");
  178. if (dmastat & DMASCR_SYSTEM_ERR_SIG)
  179. printk(KERN_CONT "SYSTEM_ERR_SIG ");
  180. if (dmastat & DMASCR_TARGET_ABT)
  181. printk(KERN_CONT "TARGET_ABT ");
  182. if (dmastat & DMASCR_MASTER_ABT)
  183. printk(KERN_CONT "MASTER_ABT ");
  184. if (dmastat & DMASCR_CHAIN_COMPLETE)
  185. printk(KERN_CONT "CHAIN_COMPLETE ");
  186. if (dmastat & DMASCR_DMA_COMPLETE)
  187. printk(KERN_CONT "DMA_COMPLETE ");
  188. printk("\n");
  189. }
  190. /*
  191. * Theory of request handling
  192. *
  193. * Each bio is assigned to one mm_dma_desc - which may not be enough FIXME
  194. * We have two pages of mm_dma_desc, holding about 64 descriptors
  195. * each. These are allocated at init time.
  196. * One page is "Ready" and is either full, or can have request added.
  197. * The other page might be "Active", which DMA is happening on it.
  198. *
  199. * Whenever IO on the active page completes, the Ready page is activated
  200. * and the ex-Active page is clean out and made Ready.
  201. * Otherwise the Ready page is only activated when it becomes full.
  202. *
  203. * If a request arrives while both pages a full, it is queued, and b_rdev is
  204. * overloaded to record whether it was a read or a write.
  205. *
  206. * The interrupt handler only polls the device to clear the interrupt.
  207. * The processing of the result is done in a tasklet.
  208. */
  209. static void mm_start_io(struct cardinfo *card)
  210. {
  211. /* we have the lock, we know there is
  212. * no IO active, and we know that card->Active
  213. * is set
  214. */
  215. struct mm_dma_desc *desc;
  216. struct mm_page *page;
  217. int offset;
  218. /* make the last descriptor end the chain */
  219. page = &card->mm_pages[card->Active];
  220. pr_debug("start_io: %d %d->%d\n",
  221. card->Active, page->headcnt, page->cnt - 1);
  222. desc = &page->desc[page->cnt-1];
  223. desc->control_bits |= cpu_to_le32(DMASCR_CHAIN_COMP_EN);
  224. desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN);
  225. desc->sem_control_bits = desc->control_bits;
  226. if (debug & DEBUG_LED_ON_TRANSFER)
  227. set_led(card, LED_REMOVE, LED_ON);
  228. desc = &page->desc[page->headcnt];
  229. writel(0, card->csr_remap + DMA_PCI_ADDR);
  230. writel(0, card->csr_remap + DMA_PCI_ADDR + 4);
  231. writel(0, card->csr_remap + DMA_LOCAL_ADDR);
  232. writel(0, card->csr_remap + DMA_LOCAL_ADDR + 4);
  233. writel(0, card->csr_remap + DMA_TRANSFER_SIZE);
  234. writel(0, card->csr_remap + DMA_TRANSFER_SIZE + 4);
  235. writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR);
  236. writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR + 4);
  237. offset = ((char *)desc) - ((char *)page->desc);
  238. writel(cpu_to_le32((page->page_dma+offset) & 0xffffffff),
  239. card->csr_remap + DMA_DESCRIPTOR_ADDR);
  240. /* Force the value to u64 before shifting otherwise >> 32 is undefined C
  241. * and on some ports will do nothing ! */
  242. writel(cpu_to_le32(((u64)page->page_dma)>>32),
  243. card->csr_remap + DMA_DESCRIPTOR_ADDR + 4);
  244. /* Go, go, go */
  245. writel(cpu_to_le32(DMASCR_GO | DMASCR_CHAIN_EN | pci_cmds),
  246. card->csr_remap + DMA_STATUS_CTRL);
  247. }
  248. static int add_bio(struct cardinfo *card);
  249. static void activate(struct cardinfo *card)
  250. {
  251. /* if No page is Active, and Ready is
  252. * not empty, then switch Ready page
  253. * to active and start IO.
  254. * Then add any bh's that are available to Ready
  255. */
  256. do {
  257. while (add_bio(card))
  258. ;
  259. if (card->Active == -1 &&
  260. card->mm_pages[card->Ready].cnt > 0) {
  261. card->Active = card->Ready;
  262. card->Ready = 1-card->Ready;
  263. mm_start_io(card);
  264. }
  265. } while (card->Active == -1 && add_bio(card));
  266. }
  267. static inline void reset_page(struct mm_page *page)
  268. {
  269. page->cnt = 0;
  270. page->headcnt = 0;
  271. page->bio = NULL;
  272. page->biotail = &page->bio;
  273. }
  274. /*
  275. * If there is room on Ready page, take
  276. * one bh off list and add it.
  277. * return 1 if there was room, else 0.
  278. */
  279. static int add_bio(struct cardinfo *card)
  280. {
  281. struct mm_page *p;
  282. struct mm_dma_desc *desc;
  283. dma_addr_t dma_handle;
  284. int offset;
  285. struct bio *bio;
  286. struct bio_vec *vec;
  287. int idx;
  288. int rw;
  289. int len;
  290. bio = card->currentbio;
  291. if (!bio && card->bio) {
  292. card->currentbio = card->bio;
  293. card->current_idx = card->bio->bi_idx;
  294. card->current_sector = card->bio->bi_sector;
  295. card->bio = card->bio->bi_next;
  296. if (card->bio == NULL)
  297. card->biotail = &card->bio;
  298. card->currentbio->bi_next = NULL;
  299. return 1;
  300. }
  301. if (!bio)
  302. return 0;
  303. idx = card->current_idx;
  304. rw = bio_rw(bio);
  305. if (card->mm_pages[card->Ready].cnt >= DESC_PER_PAGE)
  306. return 0;
  307. vec = bio_iovec_idx(bio, idx);
  308. len = vec->bv_len;
  309. dma_handle = pci_map_page(card->dev,
  310. vec->bv_page,
  311. vec->bv_offset,
  312. len,
  313. (rw == READ) ?
  314. PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
  315. p = &card->mm_pages[card->Ready];
  316. desc = &p->desc[p->cnt];
  317. p->cnt++;
  318. if (p->bio == NULL)
  319. p->idx = idx;
  320. if ((p->biotail) != &bio->bi_next) {
  321. *(p->biotail) = bio;
  322. p->biotail = &(bio->bi_next);
  323. bio->bi_next = NULL;
  324. }
  325. desc->data_dma_handle = dma_handle;
  326. desc->pci_addr = cpu_to_le64((u64)desc->data_dma_handle);
  327. desc->local_addr = cpu_to_le64(card->current_sector << 9);
  328. desc->transfer_size = cpu_to_le32(len);
  329. offset = (((char *)&desc->sem_control_bits) - ((char *)p->desc));
  330. desc->sem_addr = cpu_to_le64((u64)(p->page_dma+offset));
  331. desc->zero1 = desc->zero2 = 0;
  332. offset = (((char *)(desc+1)) - ((char *)p->desc));
  333. desc->next_desc_addr = cpu_to_le64(p->page_dma+offset);
  334. desc->control_bits = cpu_to_le32(DMASCR_GO|DMASCR_ERR_INT_EN|
  335. DMASCR_PARITY_INT_EN|
  336. DMASCR_CHAIN_EN |
  337. DMASCR_SEM_EN |
  338. pci_cmds);
  339. if (rw == WRITE)
  340. desc->control_bits |= cpu_to_le32(DMASCR_TRANSFER_READ);
  341. desc->sem_control_bits = desc->control_bits;
  342. card->current_sector += (len >> 9);
  343. idx++;
  344. card->current_idx = idx;
  345. if (idx >= bio->bi_vcnt)
  346. card->currentbio = NULL;
  347. return 1;
  348. }
  349. static void process_page(unsigned long data)
  350. {
  351. /* check if any of the requests in the page are DMA_COMPLETE,
  352. * and deal with them appropriately.
  353. * If we find a descriptor without DMA_COMPLETE in the semaphore, then
  354. * dma must have hit an error on that descriptor, so use dma_status
  355. * instead and assume that all following descriptors must be re-tried.
  356. */
  357. struct mm_page *page;
  358. struct bio *return_bio = NULL;
  359. struct cardinfo *card = (struct cardinfo *)data;
  360. unsigned int dma_status = card->dma_status;
  361. spin_lock_bh(&card->lock);
  362. if (card->Active < 0)
  363. goto out_unlock;
  364. page = &card->mm_pages[card->Active];
  365. while (page->headcnt < page->cnt) {
  366. struct bio *bio = page->bio;
  367. struct mm_dma_desc *desc = &page->desc[page->headcnt];
  368. int control = le32_to_cpu(desc->sem_control_bits);
  369. int last = 0;
  370. int idx;
  371. if (!(control & DMASCR_DMA_COMPLETE)) {
  372. control = dma_status;
  373. last = 1;
  374. }
  375. page->headcnt++;
  376. idx = page->idx;
  377. page->idx++;
  378. if (page->idx >= bio->bi_vcnt) {
  379. page->bio = bio->bi_next;
  380. if (page->bio)
  381. page->idx = page->bio->bi_idx;
  382. }
  383. pci_unmap_page(card->dev, desc->data_dma_handle,
  384. bio_iovec_idx(bio, idx)->bv_len,
  385. (control & DMASCR_TRANSFER_READ) ?
  386. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  387. if (control & DMASCR_HARD_ERROR) {
  388. /* error */
  389. clear_bit(BIO_UPTODATE, &bio->bi_flags);
  390. dev_printk(KERN_WARNING, &card->dev->dev,
  391. "I/O error on sector %d/%d\n",
  392. le32_to_cpu(desc->local_addr)>>9,
  393. le32_to_cpu(desc->transfer_size));
  394. dump_dmastat(card, control);
  395. } else if ((bio->bi_rw & REQ_WRITE) &&
  396. le32_to_cpu(desc->local_addr) >> 9 ==
  397. card->init_size) {
  398. card->init_size += le32_to_cpu(desc->transfer_size) >> 9;
  399. if (card->init_size >> 1 >= card->mm_size) {
  400. dev_printk(KERN_INFO, &card->dev->dev,
  401. "memory now initialised\n");
  402. set_userbit(card, MEMORY_INITIALIZED, 1);
  403. }
  404. }
  405. if (bio != page->bio) {
  406. bio->bi_next = return_bio;
  407. return_bio = bio;
  408. }
  409. if (last)
  410. break;
  411. }
  412. if (debug & DEBUG_LED_ON_TRANSFER)
  413. set_led(card, LED_REMOVE, LED_OFF);
  414. if (card->check_batteries) {
  415. card->check_batteries = 0;
  416. check_batteries(card);
  417. }
  418. if (page->headcnt >= page->cnt) {
  419. reset_page(page);
  420. card->Active = -1;
  421. activate(card);
  422. } else {
  423. /* haven't finished with this one yet */
  424. pr_debug("do some more\n");
  425. mm_start_io(card);
  426. }
  427. out_unlock:
  428. spin_unlock_bh(&card->lock);
  429. while (return_bio) {
  430. struct bio *bio = return_bio;
  431. return_bio = bio->bi_next;
  432. bio->bi_next = NULL;
  433. bio_endio(bio, 0);
  434. }
  435. }
  436. static int mm_make_request(struct request_queue *q, struct bio *bio)
  437. {
  438. struct cardinfo *card = q->queuedata;
  439. pr_debug("mm_make_request %llu %u\n",
  440. (unsigned long long)bio->bi_sector, bio->bi_size);
  441. spin_lock_irq(&card->lock);
  442. *card->biotail = bio;
  443. bio->bi_next = NULL;
  444. card->biotail = &bio->bi_next;
  445. spin_unlock_irq(&card->lock);
  446. return 0;
  447. }
  448. static irqreturn_t mm_interrupt(int irq, void *__card)
  449. {
  450. struct cardinfo *card = (struct cardinfo *) __card;
  451. unsigned int dma_status;
  452. unsigned short cfg_status;
  453. HW_TRACE(0x30);
  454. dma_status = le32_to_cpu(readl(card->csr_remap + DMA_STATUS_CTRL));
  455. if (!(dma_status & (DMASCR_ERROR_MASK | DMASCR_CHAIN_COMPLETE))) {
  456. /* interrupt wasn't for me ... */
  457. return IRQ_NONE;
  458. }
  459. /* clear COMPLETION interrupts */
  460. if (card->flags & UM_FLAG_NO_BYTE_STATUS)
  461. writel(cpu_to_le32(DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE),
  462. card->csr_remap + DMA_STATUS_CTRL);
  463. else
  464. writeb((DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE) >> 16,
  465. card->csr_remap + DMA_STATUS_CTRL + 2);
  466. /* log errors and clear interrupt status */
  467. if (dma_status & DMASCR_ANY_ERR) {
  468. unsigned int data_log1, data_log2;
  469. unsigned int addr_log1, addr_log2;
  470. unsigned char stat, count, syndrome, check;
  471. stat = readb(card->csr_remap + MEMCTRLCMD_ERRSTATUS);
  472. data_log1 = le32_to_cpu(readl(card->csr_remap +
  473. ERROR_DATA_LOG));
  474. data_log2 = le32_to_cpu(readl(card->csr_remap +
  475. ERROR_DATA_LOG + 4));
  476. addr_log1 = le32_to_cpu(readl(card->csr_remap +
  477. ERROR_ADDR_LOG));
  478. addr_log2 = readb(card->csr_remap + ERROR_ADDR_LOG + 4);
  479. count = readb(card->csr_remap + ERROR_COUNT);
  480. syndrome = readb(card->csr_remap + ERROR_SYNDROME);
  481. check = readb(card->csr_remap + ERROR_CHECK);
  482. dump_dmastat(card, dma_status);
  483. if (stat & 0x01)
  484. dev_printk(KERN_ERR, &card->dev->dev,
  485. "Memory access error detected (err count %d)\n",
  486. count);
  487. if (stat & 0x02)
  488. dev_printk(KERN_ERR, &card->dev->dev,
  489. "Multi-bit EDC error\n");
  490. dev_printk(KERN_ERR, &card->dev->dev,
  491. "Fault Address 0x%02x%08x, Fault Data 0x%08x%08x\n",
  492. addr_log2, addr_log1, data_log2, data_log1);
  493. dev_printk(KERN_ERR, &card->dev->dev,
  494. "Fault Check 0x%02x, Fault Syndrome 0x%02x\n",
  495. check, syndrome);
  496. writeb(0, card->csr_remap + ERROR_COUNT);
  497. }
  498. if (dma_status & DMASCR_PARITY_ERR_REP) {
  499. dev_printk(KERN_ERR, &card->dev->dev,
  500. "PARITY ERROR REPORTED\n");
  501. pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
  502. pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
  503. }
  504. if (dma_status & DMASCR_PARITY_ERR_DET) {
  505. dev_printk(KERN_ERR, &card->dev->dev,
  506. "PARITY ERROR DETECTED\n");
  507. pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
  508. pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
  509. }
  510. if (dma_status & DMASCR_SYSTEM_ERR_SIG) {
  511. dev_printk(KERN_ERR, &card->dev->dev, "SYSTEM ERROR\n");
  512. pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
  513. pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
  514. }
  515. if (dma_status & DMASCR_TARGET_ABT) {
  516. dev_printk(KERN_ERR, &card->dev->dev, "TARGET ABORT\n");
  517. pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
  518. pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
  519. }
  520. if (dma_status & DMASCR_MASTER_ABT) {
  521. dev_printk(KERN_ERR, &card->dev->dev, "MASTER ABORT\n");
  522. pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
  523. pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
  524. }
  525. /* and process the DMA descriptors */
  526. card->dma_status = dma_status;
  527. tasklet_schedule(&card->tasklet);
  528. HW_TRACE(0x36);
  529. return IRQ_HANDLED;
  530. }
  531. /*
  532. * If both batteries are good, no LED
  533. * If either battery has been warned, solid LED
  534. * If both batteries are bad, flash the LED quickly
  535. * If either battery is bad, flash the LED semi quickly
  536. */
  537. static void set_fault_to_battery_status(struct cardinfo *card)
  538. {
  539. if (card->battery[0].good && card->battery[1].good)
  540. set_led(card, LED_FAULT, LED_OFF);
  541. else if (card->battery[0].warned || card->battery[1].warned)
  542. set_led(card, LED_FAULT, LED_ON);
  543. else if (!card->battery[0].good && !card->battery[1].good)
  544. set_led(card, LED_FAULT, LED_FLASH_7_0);
  545. else
  546. set_led(card, LED_FAULT, LED_FLASH_3_5);
  547. }
  548. static void init_battery_timer(void);
  549. static int check_battery(struct cardinfo *card, int battery, int status)
  550. {
  551. if (status != card->battery[battery].good) {
  552. card->battery[battery].good = !card->battery[battery].good;
  553. card->battery[battery].last_change = jiffies;
  554. if (card->battery[battery].good) {
  555. dev_printk(KERN_ERR, &card->dev->dev,
  556. "Battery %d now good\n", battery + 1);
  557. card->battery[battery].warned = 0;
  558. } else
  559. dev_printk(KERN_ERR, &card->dev->dev,
  560. "Battery %d now FAILED\n", battery + 1);
  561. return 1;
  562. } else if (!card->battery[battery].good &&
  563. !card->battery[battery].warned &&
  564. time_after_eq(jiffies, card->battery[battery].last_change +
  565. (HZ * 60 * 60 * 5))) {
  566. dev_printk(KERN_ERR, &card->dev->dev,
  567. "Battery %d still FAILED after 5 hours\n", battery + 1);
  568. card->battery[battery].warned = 1;
  569. return 1;
  570. }
  571. return 0;
  572. }
  573. static void check_batteries(struct cardinfo *card)
  574. {
  575. /* NOTE: this must *never* be called while the card
  576. * is doing (bus-to-card) DMA, or you will need the
  577. * reset switch
  578. */
  579. unsigned char status;
  580. int ret1, ret2;
  581. status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY);
  582. if (debug & DEBUG_BATTERY_POLLING)
  583. dev_printk(KERN_DEBUG, &card->dev->dev,
  584. "checking battery status, 1 = %s, 2 = %s\n",
  585. (status & BATTERY_1_FAILURE) ? "FAILURE" : "OK",
  586. (status & BATTERY_2_FAILURE) ? "FAILURE" : "OK");
  587. ret1 = check_battery(card, 0, !(status & BATTERY_1_FAILURE));
  588. ret2 = check_battery(card, 1, !(status & BATTERY_2_FAILURE));
  589. if (ret1 || ret2)
  590. set_fault_to_battery_status(card);
  591. }
  592. static void check_all_batteries(unsigned long ptr)
  593. {
  594. int i;
  595. for (i = 0; i < num_cards; i++)
  596. if (!(cards[i].flags & UM_FLAG_NO_BATT)) {
  597. struct cardinfo *card = &cards[i];
  598. spin_lock_bh(&card->lock);
  599. if (card->Active >= 0)
  600. card->check_batteries = 1;
  601. else
  602. check_batteries(card);
  603. spin_unlock_bh(&card->lock);
  604. }
  605. init_battery_timer();
  606. }
  607. static void init_battery_timer(void)
  608. {
  609. init_timer(&battery_timer);
  610. battery_timer.function = check_all_batteries;
  611. battery_timer.expires = jiffies + (HZ * 60);
  612. add_timer(&battery_timer);
  613. }
  614. static void del_battery_timer(void)
  615. {
  616. del_timer(&battery_timer);
  617. }
  618. /*
  619. * Note no locks taken out here. In a worst case scenario, we could drop
  620. * a chunk of system memory. But that should never happen, since validation
  621. * happens at open or mount time, when locks are held.
  622. *
  623. * That's crap, since doing that while some partitions are opened
  624. * or mounted will give you really nasty results.
  625. */
  626. static int mm_revalidate(struct gendisk *disk)
  627. {
  628. struct cardinfo *card = disk->private_data;
  629. set_capacity(disk, card->mm_size << 1);
  630. return 0;
  631. }
  632. static int mm_getgeo(struct block_device *bdev, struct hd_geometry *geo)
  633. {
  634. struct cardinfo *card = bdev->bd_disk->private_data;
  635. int size = card->mm_size * (1024 / MM_HARDSECT);
  636. /*
  637. * get geometry: we have to fake one... trim the size to a
  638. * multiple of 2048 (1M): tell we have 32 sectors, 64 heads,
  639. * whatever cylinders.
  640. */
  641. geo->heads = 64;
  642. geo->sectors = 32;
  643. geo->cylinders = size / (geo->heads * geo->sectors);
  644. return 0;
  645. }
  646. static const struct block_device_operations mm_fops = {
  647. .owner = THIS_MODULE,
  648. .getgeo = mm_getgeo,
  649. .revalidate_disk = mm_revalidate,
  650. };
  651. static int __devinit mm_pci_probe(struct pci_dev *dev,
  652. const struct pci_device_id *id)
  653. {
  654. int ret = -ENODEV;
  655. struct cardinfo *card = &cards[num_cards];
  656. unsigned char mem_present;
  657. unsigned char batt_status;
  658. unsigned int saved_bar, data;
  659. unsigned long csr_base;
  660. unsigned long csr_len;
  661. int magic_number;
  662. static int printed_version;
  663. if (!printed_version++)
  664. printk(KERN_INFO DRIVER_VERSION " : " DRIVER_DESC "\n");
  665. ret = pci_enable_device(dev);
  666. if (ret)
  667. return ret;
  668. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF8);
  669. pci_set_master(dev);
  670. card->dev = dev;
  671. csr_base = pci_resource_start(dev, 0);
  672. csr_len = pci_resource_len(dev, 0);
  673. if (!csr_base || !csr_len)
  674. return -ENODEV;
  675. dev_printk(KERN_INFO, &dev->dev,
  676. "Micro Memory(tm) controller found (PCI Mem Module (Battery Backup))\n");
  677. if (pci_set_dma_mask(dev, DMA_BIT_MASK(64)) &&
  678. pci_set_dma_mask(dev, DMA_BIT_MASK(32))) {
  679. dev_printk(KERN_WARNING, &dev->dev, "NO suitable DMA found\n");
  680. return -ENOMEM;
  681. }
  682. ret = pci_request_regions(dev, DRIVER_NAME);
  683. if (ret) {
  684. dev_printk(KERN_ERR, &card->dev->dev,
  685. "Unable to request memory region\n");
  686. goto failed_req_csr;
  687. }
  688. card->csr_remap = ioremap_nocache(csr_base, csr_len);
  689. if (!card->csr_remap) {
  690. dev_printk(KERN_ERR, &card->dev->dev,
  691. "Unable to remap memory region\n");
  692. ret = -ENOMEM;
  693. goto failed_remap_csr;
  694. }
  695. dev_printk(KERN_INFO, &card->dev->dev,
  696. "CSR 0x%08lx -> 0x%p (0x%lx)\n",
  697. csr_base, card->csr_remap, csr_len);
  698. switch (card->dev->device) {
  699. case 0x5415:
  700. card->flags |= UM_FLAG_NO_BYTE_STATUS | UM_FLAG_NO_BATTREG;
  701. magic_number = 0x59;
  702. break;
  703. case 0x5425:
  704. card->flags |= UM_FLAG_NO_BYTE_STATUS;
  705. magic_number = 0x5C;
  706. break;
  707. case 0x6155:
  708. card->flags |= UM_FLAG_NO_BYTE_STATUS |
  709. UM_FLAG_NO_BATTREG | UM_FLAG_NO_BATT;
  710. magic_number = 0x99;
  711. break;
  712. default:
  713. magic_number = 0x100;
  714. break;
  715. }
  716. if (readb(card->csr_remap + MEMCTRLSTATUS_MAGIC) != magic_number) {
  717. dev_printk(KERN_ERR, &card->dev->dev, "Magic number invalid\n");
  718. ret = -ENOMEM;
  719. goto failed_magic;
  720. }
  721. card->mm_pages[0].desc = pci_alloc_consistent(card->dev,
  722. PAGE_SIZE * 2,
  723. &card->mm_pages[0].page_dma);
  724. card->mm_pages[1].desc = pci_alloc_consistent(card->dev,
  725. PAGE_SIZE * 2,
  726. &card->mm_pages[1].page_dma);
  727. if (card->mm_pages[0].desc == NULL ||
  728. card->mm_pages[1].desc == NULL) {
  729. dev_printk(KERN_ERR, &card->dev->dev, "alloc failed\n");
  730. goto failed_alloc;
  731. }
  732. reset_page(&card->mm_pages[0]);
  733. reset_page(&card->mm_pages[1]);
  734. card->Ready = 0; /* page 0 is ready */
  735. card->Active = -1; /* no page is active */
  736. card->bio = NULL;
  737. card->biotail = &card->bio;
  738. card->queue = blk_alloc_queue(GFP_KERNEL);
  739. if (!card->queue)
  740. goto failed_alloc;
  741. blk_queue_make_request(card->queue, mm_make_request);
  742. card->queue->queue_lock = &card->lock;
  743. card->queue->queuedata = card;
  744. tasklet_init(&card->tasklet, process_page, (unsigned long)card);
  745. card->check_batteries = 0;
  746. mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY);
  747. switch (mem_present) {
  748. case MEM_128_MB:
  749. card->mm_size = 1024 * 128;
  750. break;
  751. case MEM_256_MB:
  752. card->mm_size = 1024 * 256;
  753. break;
  754. case MEM_512_MB:
  755. card->mm_size = 1024 * 512;
  756. break;
  757. case MEM_1_GB:
  758. card->mm_size = 1024 * 1024;
  759. break;
  760. case MEM_2_GB:
  761. card->mm_size = 1024 * 2048;
  762. break;
  763. default:
  764. card->mm_size = 0;
  765. break;
  766. }
  767. /* Clear the LED's we control */
  768. set_led(card, LED_REMOVE, LED_OFF);
  769. set_led(card, LED_FAULT, LED_OFF);
  770. batt_status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY);
  771. card->battery[0].good = !(batt_status & BATTERY_1_FAILURE);
  772. card->battery[1].good = !(batt_status & BATTERY_2_FAILURE);
  773. card->battery[0].last_change = card->battery[1].last_change = jiffies;
  774. if (card->flags & UM_FLAG_NO_BATT)
  775. dev_printk(KERN_INFO, &card->dev->dev,
  776. "Size %d KB\n", card->mm_size);
  777. else {
  778. dev_printk(KERN_INFO, &card->dev->dev,
  779. "Size %d KB, Battery 1 %s (%s), Battery 2 %s (%s)\n",
  780. card->mm_size,
  781. batt_status & BATTERY_1_DISABLED ? "Disabled" : "Enabled",
  782. card->battery[0].good ? "OK" : "FAILURE",
  783. batt_status & BATTERY_2_DISABLED ? "Disabled" : "Enabled",
  784. card->battery[1].good ? "OK" : "FAILURE");
  785. set_fault_to_battery_status(card);
  786. }
  787. pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &saved_bar);
  788. data = 0xffffffff;
  789. pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, data);
  790. pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &data);
  791. pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, saved_bar);
  792. data &= 0xfffffff0;
  793. data = ~data;
  794. data += 1;
  795. if (request_irq(dev->irq, mm_interrupt, IRQF_SHARED, DRIVER_NAME,
  796. card)) {
  797. dev_printk(KERN_ERR, &card->dev->dev,
  798. "Unable to allocate IRQ\n");
  799. ret = -ENODEV;
  800. goto failed_req_irq;
  801. }
  802. dev_printk(KERN_INFO, &card->dev->dev,
  803. "Window size %d bytes, IRQ %d\n", data, dev->irq);
  804. spin_lock_init(&card->lock);
  805. pci_set_drvdata(dev, card);
  806. if (pci_write_cmd != 0x0F) /* If not Memory Write & Invalidate */
  807. pci_write_cmd = 0x07; /* then Memory Write command */
  808. if (pci_write_cmd & 0x08) { /* use Memory Write and Invalidate */
  809. unsigned short cfg_command;
  810. pci_read_config_word(dev, PCI_COMMAND, &cfg_command);
  811. cfg_command |= 0x10; /* Memory Write & Invalidate Enable */
  812. pci_write_config_word(dev, PCI_COMMAND, cfg_command);
  813. }
  814. pci_cmds = (pci_read_cmd << 28) | (pci_write_cmd << 24);
  815. num_cards++;
  816. if (!get_userbit(card, MEMORY_INITIALIZED)) {
  817. dev_printk(KERN_INFO, &card->dev->dev,
  818. "memory NOT initialized. Consider over-writing whole device.\n");
  819. card->init_size = 0;
  820. } else {
  821. dev_printk(KERN_INFO, &card->dev->dev,
  822. "memory already initialized\n");
  823. card->init_size = card->mm_size;
  824. }
  825. /* Enable ECC */
  826. writeb(EDC_STORE_CORRECT, card->csr_remap + MEMCTRLCMD_ERRCTRL);
  827. return 0;
  828. failed_req_irq:
  829. failed_alloc:
  830. if (card->mm_pages[0].desc)
  831. pci_free_consistent(card->dev, PAGE_SIZE*2,
  832. card->mm_pages[0].desc,
  833. card->mm_pages[0].page_dma);
  834. if (card->mm_pages[1].desc)
  835. pci_free_consistent(card->dev, PAGE_SIZE*2,
  836. card->mm_pages[1].desc,
  837. card->mm_pages[1].page_dma);
  838. failed_magic:
  839. iounmap(card->csr_remap);
  840. failed_remap_csr:
  841. pci_release_regions(dev);
  842. failed_req_csr:
  843. return ret;
  844. }
  845. static void mm_pci_remove(struct pci_dev *dev)
  846. {
  847. struct cardinfo *card = pci_get_drvdata(dev);
  848. tasklet_kill(&card->tasklet);
  849. free_irq(dev->irq, card);
  850. iounmap(card->csr_remap);
  851. if (card->mm_pages[0].desc)
  852. pci_free_consistent(card->dev, PAGE_SIZE*2,
  853. card->mm_pages[0].desc,
  854. card->mm_pages[0].page_dma);
  855. if (card->mm_pages[1].desc)
  856. pci_free_consistent(card->dev, PAGE_SIZE*2,
  857. card->mm_pages[1].desc,
  858. card->mm_pages[1].page_dma);
  859. blk_cleanup_queue(card->queue);
  860. pci_release_regions(dev);
  861. pci_disable_device(dev);
  862. }
  863. static const struct pci_device_id mm_pci_ids[] = {
  864. {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5415CN)},
  865. {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5425CN)},
  866. {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_6155)},
  867. {
  868. .vendor = 0x8086,
  869. .device = 0xB555,
  870. .subvendor = 0x1332,
  871. .subdevice = 0x5460,
  872. .class = 0x050000,
  873. .class_mask = 0,
  874. }, { /* end: all zeroes */ }
  875. };
  876. MODULE_DEVICE_TABLE(pci, mm_pci_ids);
  877. static struct pci_driver mm_pci_driver = {
  878. .name = DRIVER_NAME,
  879. .id_table = mm_pci_ids,
  880. .probe = mm_pci_probe,
  881. .remove = mm_pci_remove,
  882. };
  883. static int __init mm_init(void)
  884. {
  885. int retval, i;
  886. int err;
  887. retval = pci_register_driver(&mm_pci_driver);
  888. if (retval)
  889. return -ENOMEM;
  890. err = major_nr = register_blkdev(0, DRIVER_NAME);
  891. if (err < 0) {
  892. pci_unregister_driver(&mm_pci_driver);
  893. return -EIO;
  894. }
  895. for (i = 0; i < num_cards; i++) {
  896. mm_gendisk[i] = alloc_disk(1 << MM_SHIFT);
  897. if (!mm_gendisk[i])
  898. goto out;
  899. }
  900. for (i = 0; i < num_cards; i++) {
  901. struct gendisk *disk = mm_gendisk[i];
  902. sprintf(disk->disk_name, "umem%c", 'a'+i);
  903. spin_lock_init(&cards[i].lock);
  904. disk->major = major_nr;
  905. disk->first_minor = i << MM_SHIFT;
  906. disk->fops = &mm_fops;
  907. disk->private_data = &cards[i];
  908. disk->queue = cards[i].queue;
  909. set_capacity(disk, cards[i].mm_size << 1);
  910. add_disk(disk);
  911. }
  912. init_battery_timer();
  913. printk(KERN_INFO "MM: desc_per_page = %ld\n", DESC_PER_PAGE);
  914. /* printk("mm_init: Done. 10-19-01 9:00\n"); */
  915. return 0;
  916. out:
  917. pci_unregister_driver(&mm_pci_driver);
  918. unregister_blkdev(major_nr, DRIVER_NAME);
  919. while (i--)
  920. put_disk(mm_gendisk[i]);
  921. return -ENOMEM;
  922. }
  923. static void __exit mm_cleanup(void)
  924. {
  925. int i;
  926. del_battery_timer();
  927. for (i = 0; i < num_cards ; i++) {
  928. del_gendisk(mm_gendisk[i]);
  929. put_disk(mm_gendisk[i]);
  930. }
  931. pci_unregister_driver(&mm_pci_driver);
  932. unregister_blkdev(major_nr, DRIVER_NAME);
  933. }
  934. module_init(mm_init);
  935. module_exit(mm_cleanup);
  936. MODULE_AUTHOR(DRIVER_AUTHOR);
  937. MODULE_DESCRIPTION(DRIVER_DESC);
  938. MODULE_LICENSE("GPL");