therm_throt.c 14 KB

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  1. /*
  2. * Thermal throttle event support code (such as syslog messaging and rate
  3. * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
  4. *
  5. * This allows consistent reporting of CPU thermal throttle events.
  6. *
  7. * Maintains a counter in /sys that keeps track of the number of thermal
  8. * events, such that the user knows how bad the thermal problem might be
  9. * (since the logging to syslog and mcelog is rate limited).
  10. *
  11. * Author: Dmitriy Zavin (dmitriyz@google.com)
  12. *
  13. * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
  14. * Inspired by Ross Biro's and Al Borchers' counter code.
  15. */
  16. #include <linux/interrupt.h>
  17. #include <linux/notifier.h>
  18. #include <linux/jiffies.h>
  19. #include <linux/kernel.h>
  20. #include <linux/percpu.h>
  21. #include <linux/sysdev.h>
  22. #include <linux/types.h>
  23. #include <linux/init.h>
  24. #include <linux/smp.h>
  25. #include <linux/cpu.h>
  26. #include <asm/processor.h>
  27. #include <asm/system.h>
  28. #include <asm/apic.h>
  29. #include <asm/idle.h>
  30. #include <asm/mce.h>
  31. #include <asm/msr.h>
  32. /* How long to wait between reporting thermal events */
  33. #define CHECK_INTERVAL (300 * HZ)
  34. #define THERMAL_THROTTLING_EVENT 0
  35. #define POWER_LIMIT_EVENT 1
  36. /*
  37. * Current thermal event state:
  38. */
  39. struct _thermal_state {
  40. bool new_event;
  41. int event;
  42. u64 next_check;
  43. unsigned long count;
  44. unsigned long last_count;
  45. };
  46. struct thermal_state {
  47. struct _thermal_state core_throttle;
  48. struct _thermal_state core_power_limit;
  49. struct _thermal_state package_throttle;
  50. struct _thermal_state package_power_limit;
  51. struct _thermal_state core_thresh0;
  52. struct _thermal_state core_thresh1;
  53. };
  54. /* Callback to handle core threshold interrupts */
  55. int (*platform_thermal_notify)(__u64 msr_val);
  56. EXPORT_SYMBOL(platform_thermal_notify);
  57. static DEFINE_PER_CPU(struct thermal_state, thermal_state);
  58. static atomic_t therm_throt_en = ATOMIC_INIT(0);
  59. static u32 lvtthmr_init __read_mostly;
  60. #ifdef CONFIG_SYSFS
  61. #define define_therm_throt_sysdev_one_ro(_name) \
  62. static SYSDEV_ATTR(_name, 0444, \
  63. therm_throt_sysdev_show_##_name, \
  64. NULL) \
  65. #define define_therm_throt_sysdev_show_func(event, name) \
  66. \
  67. static ssize_t therm_throt_sysdev_show_##event##_##name( \
  68. struct sys_device *dev, \
  69. struct sysdev_attribute *attr, \
  70. char *buf) \
  71. { \
  72. unsigned int cpu = dev->id; \
  73. ssize_t ret; \
  74. \
  75. preempt_disable(); /* CPU hotplug */ \
  76. if (cpu_online(cpu)) { \
  77. ret = sprintf(buf, "%lu\n", \
  78. per_cpu(thermal_state, cpu).event.name); \
  79. } else \
  80. ret = 0; \
  81. preempt_enable(); \
  82. \
  83. return ret; \
  84. }
  85. define_therm_throt_sysdev_show_func(core_throttle, count);
  86. define_therm_throt_sysdev_one_ro(core_throttle_count);
  87. define_therm_throt_sysdev_show_func(core_power_limit, count);
  88. define_therm_throt_sysdev_one_ro(core_power_limit_count);
  89. define_therm_throt_sysdev_show_func(package_throttle, count);
  90. define_therm_throt_sysdev_one_ro(package_throttle_count);
  91. define_therm_throt_sysdev_show_func(package_power_limit, count);
  92. define_therm_throt_sysdev_one_ro(package_power_limit_count);
  93. static struct attribute *thermal_throttle_attrs[] = {
  94. &attr_core_throttle_count.attr,
  95. NULL
  96. };
  97. static struct attribute_group thermal_attr_group = {
  98. .attrs = thermal_throttle_attrs,
  99. .name = "thermal_throttle"
  100. };
  101. #endif /* CONFIG_SYSFS */
  102. #define CORE_LEVEL 0
  103. #define PACKAGE_LEVEL 1
  104. /***
  105. * therm_throt_process - Process thermal throttling event from interrupt
  106. * @curr: Whether the condition is current or not (boolean), since the
  107. * thermal interrupt normally gets called both when the thermal
  108. * event begins and once the event has ended.
  109. *
  110. * This function is called by the thermal interrupt after the
  111. * IRQ has been acknowledged.
  112. *
  113. * It will take care of rate limiting and printing messages to the syslog.
  114. *
  115. * Returns: 0 : Event should NOT be further logged, i.e. still in
  116. * "timeout" from previous log message.
  117. * 1 : Event should be logged further, and a message has been
  118. * printed to the syslog.
  119. */
  120. static int therm_throt_process(bool new_event, int event, int level)
  121. {
  122. struct _thermal_state *state;
  123. unsigned int this_cpu = smp_processor_id();
  124. bool old_event;
  125. u64 now;
  126. struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
  127. now = get_jiffies_64();
  128. if (level == CORE_LEVEL) {
  129. if (event == THERMAL_THROTTLING_EVENT)
  130. state = &pstate->core_throttle;
  131. else if (event == POWER_LIMIT_EVENT)
  132. state = &pstate->core_power_limit;
  133. else
  134. return 0;
  135. } else if (level == PACKAGE_LEVEL) {
  136. if (event == THERMAL_THROTTLING_EVENT)
  137. state = &pstate->package_throttle;
  138. else if (event == POWER_LIMIT_EVENT)
  139. state = &pstate->package_power_limit;
  140. else
  141. return 0;
  142. } else
  143. return 0;
  144. old_event = state->new_event;
  145. state->new_event = new_event;
  146. if (new_event)
  147. state->count++;
  148. if (time_before64(now, state->next_check) &&
  149. state->count != state->last_count)
  150. return 0;
  151. state->next_check = now + CHECK_INTERVAL;
  152. state->last_count = state->count;
  153. /* if we just entered the thermal event */
  154. if (new_event) {
  155. if (event == THERMAL_THROTTLING_EVENT)
  156. printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
  157. this_cpu,
  158. level == CORE_LEVEL ? "Core" : "Package",
  159. state->count);
  160. else
  161. printk(KERN_CRIT "CPU%d: %s power limit notification (total events = %lu)\n",
  162. this_cpu,
  163. level == CORE_LEVEL ? "Core" : "Package",
  164. state->count);
  165. add_taint(TAINT_MACHINE_CHECK);
  166. return 1;
  167. }
  168. if (old_event) {
  169. if (event == THERMAL_THROTTLING_EVENT)
  170. printk(KERN_INFO "CPU%d: %s temperature/speed normal\n",
  171. this_cpu,
  172. level == CORE_LEVEL ? "Core" : "Package");
  173. else
  174. printk(KERN_INFO "CPU%d: %s power limit normal\n",
  175. this_cpu,
  176. level == CORE_LEVEL ? "Core" : "Package");
  177. return 1;
  178. }
  179. return 0;
  180. }
  181. static int thresh_event_valid(int event)
  182. {
  183. struct _thermal_state *state;
  184. unsigned int this_cpu = smp_processor_id();
  185. struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
  186. u64 now = get_jiffies_64();
  187. state = (event == 0) ? &pstate->core_thresh0 : &pstate->core_thresh1;
  188. if (time_before64(now, state->next_check))
  189. return 0;
  190. state->next_check = now + CHECK_INTERVAL;
  191. return 1;
  192. }
  193. #ifdef CONFIG_SYSFS
  194. /* Add/Remove thermal_throttle interface for CPU device: */
  195. static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev,
  196. unsigned int cpu)
  197. {
  198. int err;
  199. struct cpuinfo_x86 *c = &cpu_data(cpu);
  200. err = sysfs_create_group(&sys_dev->kobj, &thermal_attr_group);
  201. if (err)
  202. return err;
  203. if (cpu_has(c, X86_FEATURE_PLN))
  204. err = sysfs_add_file_to_group(&sys_dev->kobj,
  205. &attr_core_power_limit_count.attr,
  206. thermal_attr_group.name);
  207. if (cpu_has(c, X86_FEATURE_PTS)) {
  208. err = sysfs_add_file_to_group(&sys_dev->kobj,
  209. &attr_package_throttle_count.attr,
  210. thermal_attr_group.name);
  211. if (cpu_has(c, X86_FEATURE_PLN))
  212. err = sysfs_add_file_to_group(&sys_dev->kobj,
  213. &attr_package_power_limit_count.attr,
  214. thermal_attr_group.name);
  215. }
  216. return err;
  217. }
  218. static __cpuinit void thermal_throttle_remove_dev(struct sys_device *sys_dev)
  219. {
  220. sysfs_remove_group(&sys_dev->kobj, &thermal_attr_group);
  221. }
  222. /* Mutex protecting device creation against CPU hotplug: */
  223. static DEFINE_MUTEX(therm_cpu_lock);
  224. /* Get notified when a cpu comes on/off. Be hotplug friendly. */
  225. static __cpuinit int
  226. thermal_throttle_cpu_callback(struct notifier_block *nfb,
  227. unsigned long action,
  228. void *hcpu)
  229. {
  230. unsigned int cpu = (unsigned long)hcpu;
  231. struct sys_device *sys_dev;
  232. int err = 0;
  233. sys_dev = get_cpu_sysdev(cpu);
  234. switch (action) {
  235. case CPU_UP_PREPARE:
  236. case CPU_UP_PREPARE_FROZEN:
  237. mutex_lock(&therm_cpu_lock);
  238. err = thermal_throttle_add_dev(sys_dev, cpu);
  239. mutex_unlock(&therm_cpu_lock);
  240. WARN_ON(err);
  241. break;
  242. case CPU_UP_CANCELED:
  243. case CPU_UP_CANCELED_FROZEN:
  244. case CPU_DEAD:
  245. case CPU_DEAD_FROZEN:
  246. mutex_lock(&therm_cpu_lock);
  247. thermal_throttle_remove_dev(sys_dev);
  248. mutex_unlock(&therm_cpu_lock);
  249. break;
  250. }
  251. return notifier_from_errno(err);
  252. }
  253. static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata =
  254. {
  255. .notifier_call = thermal_throttle_cpu_callback,
  256. };
  257. static __init int thermal_throttle_init_device(void)
  258. {
  259. unsigned int cpu = 0;
  260. int err;
  261. if (!atomic_read(&therm_throt_en))
  262. return 0;
  263. register_hotcpu_notifier(&thermal_throttle_cpu_notifier);
  264. #ifdef CONFIG_HOTPLUG_CPU
  265. mutex_lock(&therm_cpu_lock);
  266. #endif
  267. /* connect live CPUs to sysfs */
  268. for_each_online_cpu(cpu) {
  269. err = thermal_throttle_add_dev(get_cpu_sysdev(cpu), cpu);
  270. WARN_ON(err);
  271. }
  272. #ifdef CONFIG_HOTPLUG_CPU
  273. mutex_unlock(&therm_cpu_lock);
  274. #endif
  275. return 0;
  276. }
  277. device_initcall(thermal_throttle_init_device);
  278. #endif /* CONFIG_SYSFS */
  279. /*
  280. * Set up the most two significant bit to notify mce log that this thermal
  281. * event type.
  282. * This is a temp solution. May be changed in the future with mce log
  283. * infrasture.
  284. */
  285. #define CORE_THROTTLED (0)
  286. #define CORE_POWER_LIMIT ((__u64)1 << 62)
  287. #define PACKAGE_THROTTLED ((__u64)2 << 62)
  288. #define PACKAGE_POWER_LIMIT ((__u64)3 << 62)
  289. static void notify_thresholds(__u64 msr_val)
  290. {
  291. /* check whether the interrupt handler is defined;
  292. * otherwise simply return
  293. */
  294. if (!platform_thermal_notify)
  295. return;
  296. /* lower threshold reached */
  297. if ((msr_val & THERM_LOG_THRESHOLD0) && thresh_event_valid(0))
  298. platform_thermal_notify(msr_val);
  299. /* higher threshold reached */
  300. if ((msr_val & THERM_LOG_THRESHOLD1) && thresh_event_valid(1))
  301. platform_thermal_notify(msr_val);
  302. }
  303. /* Thermal transition interrupt handler */
  304. static void intel_thermal_interrupt(void)
  305. {
  306. __u64 msr_val;
  307. struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
  308. rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  309. /* Check for violation of core thermal thresholds*/
  310. notify_thresholds(msr_val);
  311. if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
  312. THERMAL_THROTTLING_EVENT,
  313. CORE_LEVEL) != 0)
  314. mce_log_therm_throt_event(CORE_THROTTLED | msr_val);
  315. if (cpu_has(c, X86_FEATURE_PLN))
  316. if (therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
  317. POWER_LIMIT_EVENT,
  318. CORE_LEVEL) != 0)
  319. mce_log_therm_throt_event(CORE_POWER_LIMIT | msr_val);
  320. if (cpu_has(c, X86_FEATURE_PTS)) {
  321. rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
  322. if (therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
  323. THERMAL_THROTTLING_EVENT,
  324. PACKAGE_LEVEL) != 0)
  325. mce_log_therm_throt_event(PACKAGE_THROTTLED | msr_val);
  326. if (cpu_has(c, X86_FEATURE_PLN))
  327. if (therm_throt_process(msr_val &
  328. PACKAGE_THERM_STATUS_POWER_LIMIT,
  329. POWER_LIMIT_EVENT,
  330. PACKAGE_LEVEL) != 0)
  331. mce_log_therm_throt_event(PACKAGE_POWER_LIMIT
  332. | msr_val);
  333. }
  334. }
  335. static void unexpected_thermal_interrupt(void)
  336. {
  337. printk(KERN_ERR "CPU%d: Unexpected LVT thermal interrupt!\n",
  338. smp_processor_id());
  339. add_taint(TAINT_MACHINE_CHECK);
  340. }
  341. static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
  342. asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
  343. {
  344. exit_idle();
  345. irq_enter();
  346. inc_irq_stat(irq_thermal_count);
  347. smp_thermal_vector();
  348. irq_exit();
  349. /* Ack only at the end to avoid potential reentry */
  350. ack_APIC_irq();
  351. }
  352. /* Thermal monitoring depends on APIC, ACPI and clock modulation */
  353. static int intel_thermal_supported(struct cpuinfo_x86 *c)
  354. {
  355. if (!cpu_has_apic)
  356. return 0;
  357. if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
  358. return 0;
  359. return 1;
  360. }
  361. void __init mcheck_intel_therm_init(void)
  362. {
  363. /*
  364. * This function is only called on boot CPU. Save the init thermal
  365. * LVT value on BSP and use that value to restore APs' thermal LVT
  366. * entry BIOS programmed later
  367. */
  368. if (intel_thermal_supported(&boot_cpu_data))
  369. lvtthmr_init = apic_read(APIC_LVTTHMR);
  370. }
  371. void intel_init_thermal(struct cpuinfo_x86 *c)
  372. {
  373. unsigned int cpu = smp_processor_id();
  374. int tm2 = 0;
  375. u32 l, h;
  376. if (!intel_thermal_supported(c))
  377. return;
  378. /*
  379. * First check if its enabled already, in which case there might
  380. * be some SMM goo which handles it, so we can't even put a handler
  381. * since it might be delivered via SMI already:
  382. */
  383. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  384. /*
  385. * The initial value of thermal LVT entries on all APs always reads
  386. * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
  387. * sequence to them and LVT registers are reset to 0s except for
  388. * the mask bits which are set to 1s when APs receive INIT IPI.
  389. * Always restore the value that BIOS has programmed on AP based on
  390. * BSP's info we saved since BIOS is always setting the same value
  391. * for all threads/cores
  392. */
  393. apic_write(APIC_LVTTHMR, lvtthmr_init);
  394. h = lvtthmr_init;
  395. if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
  396. printk(KERN_DEBUG
  397. "CPU%d: Thermal monitoring handled by SMI\n", cpu);
  398. return;
  399. }
  400. /* Check whether a vector already exists */
  401. if (h & APIC_VECTOR_MASK) {
  402. printk(KERN_DEBUG
  403. "CPU%d: Thermal LVT vector (%#x) already installed\n",
  404. cpu, (h & APIC_VECTOR_MASK));
  405. return;
  406. }
  407. /* early Pentium M models use different method for enabling TM2 */
  408. if (cpu_has(c, X86_FEATURE_TM2)) {
  409. if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
  410. rdmsr(MSR_THERM2_CTL, l, h);
  411. if (l & MSR_THERM2_CTL_TM_SELECT)
  412. tm2 = 1;
  413. } else if (l & MSR_IA32_MISC_ENABLE_TM2)
  414. tm2 = 1;
  415. }
  416. /* We'll mask the thermal vector in the lapic till we're ready: */
  417. h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
  418. apic_write(APIC_LVTTHMR, h);
  419. rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
  420. if (cpu_has(c, X86_FEATURE_PLN))
  421. wrmsr(MSR_IA32_THERM_INTERRUPT,
  422. l | (THERM_INT_LOW_ENABLE
  423. | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
  424. else
  425. wrmsr(MSR_IA32_THERM_INTERRUPT,
  426. l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
  427. if (cpu_has(c, X86_FEATURE_PTS)) {
  428. rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
  429. if (cpu_has(c, X86_FEATURE_PLN))
  430. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  431. l | (PACKAGE_THERM_INT_LOW_ENABLE
  432. | PACKAGE_THERM_INT_HIGH_ENABLE
  433. | PACKAGE_THERM_INT_PLN_ENABLE), h);
  434. else
  435. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  436. l | (PACKAGE_THERM_INT_LOW_ENABLE
  437. | PACKAGE_THERM_INT_HIGH_ENABLE), h);
  438. }
  439. smp_thermal_vector = intel_thermal_interrupt;
  440. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  441. wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
  442. /* Unmask the thermal vector: */
  443. l = apic_read(APIC_LVTTHMR);
  444. apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
  445. printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n",
  446. tm2 ? "TM2" : "TM1");
  447. /* enable thermal throttle processing */
  448. atomic_set(&therm_throt_en, 1);
  449. }