pci.h 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. /*
  2. * Copyright 2010 Tilera Corporation. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation, version 2.
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11. * NON INFRINGEMENT. See the GNU General Public License for
  12. * more details.
  13. */
  14. #ifndef _ASM_TILE_PCI_H
  15. #define _ASM_TILE_PCI_H
  16. #include <linux/pci.h>
  17. /*
  18. * Structure of a PCI controller (host bridge)
  19. */
  20. struct pci_controller {
  21. int index; /* PCI domain number */
  22. struct pci_bus *root_bus;
  23. int first_busno;
  24. int last_busno;
  25. int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
  26. int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
  27. struct pci_ops *ops;
  28. int irq_base; /* Base IRQ from the Hypervisor */
  29. int plx_gen1; /* flag for PLX Gen 1 configuration */
  30. /* Address ranges that are routed to this controller/bridge. */
  31. struct resource mem_resources[3];
  32. };
  33. /*
  34. * The hypervisor maps the entirety of CPA-space as bus addresses, so
  35. * bus addresses are physical addresses. The networking and block
  36. * device layers use this boolean for bounce buffer decisions.
  37. */
  38. #define PCI_DMA_BUS_IS_PHYS 1
  39. int __init tile_pci_init(void);
  40. void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
  41. static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
  42. void __devinit pcibios_fixup_bus(struct pci_bus *bus);
  43. #define TILE_NUM_PCIE 2
  44. #define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
  45. /*
  46. * This decides whether to display the domain number in /proc.
  47. */
  48. static inline int pci_proc_domain(struct pci_bus *bus)
  49. {
  50. return 1;
  51. }
  52. /*
  53. * pcibios_assign_all_busses() tells whether or not the bus numbers
  54. * should be reassigned, in case the BIOS didn't do it correctly, or
  55. * in case we don't have a BIOS and we want to let Linux do it.
  56. */
  57. static inline int pcibios_assign_all_busses(void)
  58. {
  59. return 1;
  60. }
  61. /*
  62. * No special bus mastering setup handling.
  63. */
  64. static inline void pcibios_set_master(struct pci_dev *dev)
  65. {
  66. }
  67. #define PCIBIOS_MIN_MEM 0
  68. #define PCIBIOS_MIN_IO 0
  69. /*
  70. * This flag tells if the platform is TILEmpower that needs
  71. * special configuration for the PLX switch chip.
  72. */
  73. extern int tile_plx_gen1;
  74. /* Use any cpu for PCI. */
  75. #define cpumask_of_pcibus(bus) cpu_online_mask
  76. /* implement the pci_ DMA API in terms of the generic device dma_ one */
  77. #include <asm-generic/pci-dma-compat.h>
  78. /* generic pci stuff */
  79. #include <asm-generic/pci.h>
  80. #endif /* _ASM_TILE_PCI_H */