irq.h 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687
  1. /*
  2. * Copyright 2010 Tilera Corporation. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation, version 2.
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11. * NON INFRINGEMENT. See the GNU General Public License for
  12. * more details.
  13. */
  14. #ifndef _ASM_TILE_IRQ_H
  15. #define _ASM_TILE_IRQ_H
  16. #include <linux/hardirq.h>
  17. /* The hypervisor interface provides 32 IRQs. */
  18. #define NR_IRQS 32
  19. /* IRQ numbers used for linux IPIs. */
  20. #define IRQ_RESCHEDULE 1
  21. void ack_bad_irq(unsigned int irq);
  22. /*
  23. * Different ways of handling interrupts. Tile interrupts are always
  24. * per-cpu; there is no global interrupt controller to implement
  25. * enable/disable. Most onboard devices can send their interrupts to
  26. * many tiles at the same time, and Tile-specific drivers know how to
  27. * deal with this.
  28. *
  29. * However, generic devices (usually PCIE based, sometimes GPIO)
  30. * expect that interrupts will fire on a single core at a time and
  31. * that the irq can be enabled or disabled from any core at any time.
  32. * We implement this by directing such interrupts to a single core.
  33. *
  34. * One added wrinkle is that PCI interrupts can be either
  35. * hardware-cleared (legacy interrupts) or software cleared (MSI).
  36. * Other generic device systems (GPIO) are always software-cleared.
  37. *
  38. * The enums below are used by drivers for onboard devices, including
  39. * the internals of PCI root complex and GPIO. They allow the driver
  40. * to tell the generic irq code what kind of interrupt is mapped to a
  41. * particular IRQ number.
  42. */
  43. enum {
  44. /* per-cpu interrupt; use enable/disable_percpu_irq() to mask */
  45. TILE_IRQ_PERCPU,
  46. /* global interrupt, hardware responsible for clearing. */
  47. TILE_IRQ_HW_CLEAR,
  48. /* global interrupt, software responsible for clearing. */
  49. TILE_IRQ_SW_CLEAR,
  50. };
  51. /*
  52. * Paravirtualized drivers should call this when they dynamically
  53. * allocate a new IRQ or discover an IRQ that was pre-allocated by the
  54. * hypervisor for use with their particular device. This gives the
  55. * IRQ subsystem an opportunity to do interrupt-type-specific
  56. * initialization.
  57. *
  58. * ISSUE: We should modify this API so that registering anything
  59. * except percpu interrupts also requires providing callback methods
  60. * for enabling and disabling the interrupt. This would allow the
  61. * generic IRQ code to proxy enable/disable_irq() calls back into the
  62. * PCI subsystem, which in turn could enable or disable the interrupt
  63. * at the PCI shim.
  64. */
  65. void tile_irq_activate(unsigned int irq, int tile_irq_type);
  66. /*
  67. * For onboard, non-PCI (e.g. TILE_IRQ_PERCPU) devices, drivers know
  68. * how to use enable/disable_percpu_irq() to manage interrupts on each
  69. * core. We can't use the generic enable/disable_irq() because they
  70. * use a single reference count per irq, rather than per cpu per irq.
  71. */
  72. void enable_percpu_irq(unsigned int irq);
  73. void disable_percpu_irq(unsigned int irq);
  74. void setup_irq_regs(void);
  75. #endif /* _ASM_TILE_IRQ_H */