setup.c 4.5 KB

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  1. /*
  2. * linux/arch/sh/boards/se/770x/setup.c
  3. *
  4. * Copyright (C) 2000 Kazumoto Kojima
  5. *
  6. * Hitachi SolutionEngine Support.
  7. *
  8. */
  9. #include <linux/init.h>
  10. #include <linux/platform_device.h>
  11. #include <mach-se/mach/se.h>
  12. #include <mach-se/mach/mrshpc.h>
  13. #include <asm/machvec.h>
  14. #include <asm/io.h>
  15. #include <asm/smc37c93x.h>
  16. #include <asm/heartbeat.h>
  17. /*
  18. * Configure the Super I/O chip
  19. */
  20. static void __init smsc_config(int index, int data)
  21. {
  22. outb_p(index, INDEX_PORT);
  23. outb_p(data, DATA_PORT);
  24. }
  25. /* XXX: Another candidate for a more generic cchip machine vector */
  26. static void __init smsc_setup(char **cmdline_p)
  27. {
  28. outb_p(CONFIG_ENTER, CONFIG_PORT);
  29. outb_p(CONFIG_ENTER, CONFIG_PORT);
  30. /* FDC */
  31. smsc_config(CURRENT_LDN_INDEX, LDN_FDC);
  32. smsc_config(ACTIVATE_INDEX, 0x01);
  33. smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */
  34. /* AUXIO (GPIO): to use IDE1 */
  35. smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO);
  36. smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */
  37. smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */
  38. /* COM1 */
  39. smsc_config(CURRENT_LDN_INDEX, LDN_COM1);
  40. smsc_config(ACTIVATE_INDEX, 0x01);
  41. smsc_config(IO_BASE_HI_INDEX, 0x03);
  42. smsc_config(IO_BASE_LO_INDEX, 0xf8);
  43. smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */
  44. /* COM2 */
  45. smsc_config(CURRENT_LDN_INDEX, LDN_COM2);
  46. smsc_config(ACTIVATE_INDEX, 0x01);
  47. smsc_config(IO_BASE_HI_INDEX, 0x02);
  48. smsc_config(IO_BASE_LO_INDEX, 0xf8);
  49. smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */
  50. /* RTC */
  51. smsc_config(CURRENT_LDN_INDEX, LDN_RTC);
  52. smsc_config(ACTIVATE_INDEX, 0x01);
  53. smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */
  54. /* XXX: PARPORT, KBD, and MOUSE will come here... */
  55. outb_p(CONFIG_EXIT, CONFIG_PORT);
  56. }
  57. static struct resource cf_ide_resources[] = {
  58. [0] = {
  59. .start = PA_MRSHPC_IO + 0x1f0,
  60. .end = PA_MRSHPC_IO + 0x1f0 + 8,
  61. .flags = IORESOURCE_MEM,
  62. },
  63. [1] = {
  64. .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
  65. .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
  66. .flags = IORESOURCE_MEM,
  67. },
  68. [2] = {
  69. .start = IRQ_CFCARD,
  70. .flags = IORESOURCE_IRQ,
  71. },
  72. };
  73. static struct platform_device cf_ide_device = {
  74. .name = "pata_platform",
  75. .id = -1,
  76. .num_resources = ARRAY_SIZE(cf_ide_resources),
  77. .resource = cf_ide_resources,
  78. };
  79. static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
  80. static struct heartbeat_data heartbeat_data = {
  81. .bit_pos = heartbeat_bit_pos,
  82. .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
  83. };
  84. static struct resource heartbeat_resource = {
  85. .start = PA_LED,
  86. .end = PA_LED,
  87. .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
  88. };
  89. static struct platform_device heartbeat_device = {
  90. .name = "heartbeat",
  91. .id = -1,
  92. .dev = {
  93. .platform_data = &heartbeat_data,
  94. },
  95. .num_resources = 1,
  96. .resource = &heartbeat_resource,
  97. };
  98. #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
  99. defined(CONFIG_CPU_SUBTYPE_SH7712)
  100. /* SH771X Ethernet driver */
  101. static struct resource sh_eth0_resources[] = {
  102. [0] = {
  103. .start = SH_ETH0_BASE,
  104. .end = SH_ETH0_BASE + 0x1B8,
  105. .flags = IORESOURCE_MEM,
  106. },
  107. [1] = {
  108. .start = SH_ETH0_IRQ,
  109. .end = SH_ETH0_IRQ,
  110. .flags = IORESOURCE_IRQ,
  111. },
  112. };
  113. static struct platform_device sh_eth0_device = {
  114. .name = "sh-eth",
  115. .id = 0,
  116. .dev = {
  117. .platform_data = PHY_ID,
  118. },
  119. .num_resources = ARRAY_SIZE(sh_eth0_resources),
  120. .resource = sh_eth0_resources,
  121. };
  122. static struct resource sh_eth1_resources[] = {
  123. [0] = {
  124. .start = SH_ETH1_BASE,
  125. .end = SH_ETH1_BASE + 0x1B8,
  126. .flags = IORESOURCE_MEM,
  127. },
  128. [1] = {
  129. .start = SH_ETH1_IRQ,
  130. .end = SH_ETH1_IRQ,
  131. .flags = IORESOURCE_IRQ,
  132. },
  133. };
  134. static struct platform_device sh_eth1_device = {
  135. .name = "sh-eth",
  136. .id = 1,
  137. .dev = {
  138. .platform_data = PHY_ID,
  139. },
  140. .num_resources = ARRAY_SIZE(sh_eth1_resources),
  141. .resource = sh_eth1_resources,
  142. };
  143. #endif
  144. static struct platform_device *se_devices[] __initdata = {
  145. &heartbeat_device,
  146. &cf_ide_device,
  147. #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
  148. defined(CONFIG_CPU_SUBTYPE_SH7712)
  149. &sh_eth0_device,
  150. &sh_eth1_device,
  151. #endif
  152. };
  153. static int __init se_devices_setup(void)
  154. {
  155. mrshpc_setup_windows();
  156. return platform_add_devices(se_devices, ARRAY_SIZE(se_devices));
  157. }
  158. device_initcall(se_devices_setup);
  159. /*
  160. * The Machine Vector
  161. */
  162. static struct sh_machine_vector mv_se __initmv = {
  163. .mv_name = "SolutionEngine",
  164. .mv_setup = smsc_setup,
  165. #if defined(CONFIG_CPU_SH4)
  166. .mv_nr_irqs = 48,
  167. #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
  168. .mv_nr_irqs = 32,
  169. #elif defined(CONFIG_CPU_SUBTYPE_SH7709)
  170. .mv_nr_irqs = 61,
  171. #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  172. .mv_nr_irqs = 86,
  173. #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  174. .mv_nr_irqs = 104,
  175. #endif
  176. .mv_init_irq = init_se_IRQ,
  177. };