hlwd-pic.c 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242
  1. /*
  2. * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
  3. *
  4. * Nintendo Wii "Hollywood" interrupt controller support.
  5. * Copyright (C) 2009 The GameCube Linux Team
  6. * Copyright (C) 2009 Albert Herranz
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. *
  13. */
  14. #define DRV_MODULE_NAME "hlwd-pic"
  15. #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/irq.h>
  19. #include <linux/of.h>
  20. #include <asm/io.h>
  21. #include "hlwd-pic.h"
  22. #define HLWD_NR_IRQS 32
  23. /*
  24. * Each interrupt has a corresponding bit in both
  25. * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
  26. *
  27. * Enabling/disabling an interrupt line involves asserting/clearing
  28. * the corresponding bit in IMR. ACK'ing a request simply involves
  29. * asserting the corresponding bit in ICR.
  30. */
  31. #define HW_BROADWAY_ICR 0x00
  32. #define HW_BROADWAY_IMR 0x04
  33. /*
  34. * IRQ chip hooks.
  35. *
  36. */
  37. static void hlwd_pic_mask_and_ack(struct irq_data *d)
  38. {
  39. int irq = virq_to_hw(d->irq);
  40. void __iomem *io_base = irq_data_get_irq_chip_data(d);
  41. u32 mask = 1 << irq;
  42. clrbits32(io_base + HW_BROADWAY_IMR, mask);
  43. out_be32(io_base + HW_BROADWAY_ICR, mask);
  44. }
  45. static void hlwd_pic_ack(struct irq_data *d)
  46. {
  47. int irq = virq_to_hw(d->irq);
  48. void __iomem *io_base = irq_data_get_irq_chip_data(d);
  49. out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
  50. }
  51. static void hlwd_pic_mask(struct irq_data *d)
  52. {
  53. int irq = virq_to_hw(d->irq);
  54. void __iomem *io_base = irq_data_get_irq_chip_data(d);
  55. clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
  56. }
  57. static void hlwd_pic_unmask(struct irq_data *d)
  58. {
  59. int irq = virq_to_hw(d->irq);
  60. void __iomem *io_base = irq_data_get_irq_chip_data(d);
  61. setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
  62. }
  63. static struct irq_chip hlwd_pic = {
  64. .name = "hlwd-pic",
  65. .irq_ack = hlwd_pic_ack,
  66. .irq_mask_ack = hlwd_pic_mask_and_ack,
  67. .irq_mask = hlwd_pic_mask,
  68. .irq_unmask = hlwd_pic_unmask,
  69. };
  70. /*
  71. * IRQ host hooks.
  72. *
  73. */
  74. static struct irq_host *hlwd_irq_host;
  75. static int hlwd_pic_map(struct irq_host *h, unsigned int virq,
  76. irq_hw_number_t hwirq)
  77. {
  78. irq_set_chip_data(virq, h->host_data);
  79. irq_set_status_flags(virq, IRQ_LEVEL);
  80. irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
  81. return 0;
  82. }
  83. static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq)
  84. {
  85. irq_set_chip_data(irq, NULL);
  86. irq_set_chip(irq, NULL);
  87. }
  88. static struct irq_host_ops hlwd_irq_host_ops = {
  89. .map = hlwd_pic_map,
  90. .unmap = hlwd_pic_unmap,
  91. };
  92. static unsigned int __hlwd_pic_get_irq(struct irq_host *h)
  93. {
  94. void __iomem *io_base = h->host_data;
  95. int irq;
  96. u32 irq_status;
  97. irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
  98. in_be32(io_base + HW_BROADWAY_IMR);
  99. if (irq_status == 0)
  100. return NO_IRQ; /* no more IRQs pending */
  101. irq = __ffs(irq_status);
  102. return irq_linear_revmap(h, irq);
  103. }
  104. static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
  105. struct irq_desc *desc)
  106. {
  107. struct irq_chip *chip = irq_desc_get_chip(desc);
  108. struct irq_host *irq_host = irq_get_handler_data(cascade_virq);
  109. unsigned int virq;
  110. raw_spin_lock(&desc->lock);
  111. chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
  112. raw_spin_unlock(&desc->lock);
  113. virq = __hlwd_pic_get_irq(irq_host);
  114. if (virq != NO_IRQ)
  115. generic_handle_irq(virq);
  116. else
  117. pr_err("spurious interrupt!\n");
  118. raw_spin_lock(&desc->lock);
  119. chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
  120. if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
  121. chip->irq_unmask(&desc->irq_data);
  122. raw_spin_unlock(&desc->lock);
  123. }
  124. /*
  125. * Platform hooks.
  126. *
  127. */
  128. static void __hlwd_quiesce(void __iomem *io_base)
  129. {
  130. /* mask and ack all IRQs */
  131. out_be32(io_base + HW_BROADWAY_IMR, 0);
  132. out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
  133. }
  134. struct irq_host *hlwd_pic_init(struct device_node *np)
  135. {
  136. struct irq_host *irq_host;
  137. struct resource res;
  138. void __iomem *io_base;
  139. int retval;
  140. retval = of_address_to_resource(np, 0, &res);
  141. if (retval) {
  142. pr_err("no io memory range found\n");
  143. return NULL;
  144. }
  145. io_base = ioremap(res.start, resource_size(&res));
  146. if (!io_base) {
  147. pr_err("ioremap failed\n");
  148. return NULL;
  149. }
  150. pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
  151. __hlwd_quiesce(io_base);
  152. irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, HLWD_NR_IRQS,
  153. &hlwd_irq_host_ops, -1);
  154. if (!irq_host) {
  155. pr_err("failed to allocate irq_host\n");
  156. return NULL;
  157. }
  158. irq_host->host_data = io_base;
  159. return irq_host;
  160. }
  161. unsigned int hlwd_pic_get_irq(void)
  162. {
  163. return __hlwd_pic_get_irq(hlwd_irq_host);
  164. }
  165. /*
  166. * Probe function.
  167. *
  168. */
  169. void hlwd_pic_probe(void)
  170. {
  171. struct irq_host *host;
  172. struct device_node *np;
  173. const u32 *interrupts;
  174. int cascade_virq;
  175. for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
  176. interrupts = of_get_property(np, "interrupts", NULL);
  177. if (interrupts) {
  178. host = hlwd_pic_init(np);
  179. BUG_ON(!host);
  180. cascade_virq = irq_of_parse_and_map(np, 0);
  181. irq_set_handler_data(cascade_virq, host);
  182. irq_set_chained_handler(cascade_virq,
  183. hlwd_pic_irq_cascade);
  184. hlwd_irq_host = host;
  185. break;
  186. }
  187. }
  188. }
  189. /**
  190. * hlwd_quiesce() - quiesce hollywood irq controller
  191. *
  192. * Mask and ack all interrupt sources.
  193. *
  194. */
  195. void hlwd_quiesce(void)
  196. {
  197. void __iomem *io_base = hlwd_irq_host->host_data;
  198. __hlwd_quiesce(io_base);
  199. }