mpc85xx_ds.c 7.2 KB

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  1. /*
  2. * MPC85xx DS Board Setup
  3. *
  4. * Author Xianghua Xiao (x.xiao@freescale.com)
  5. * Roy Zang <tie-fei.zang@freescale.com>
  6. * - Add PCI/PCI Exprees support
  7. * Copyright 2007 Freescale Semiconductor Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/stddef.h>
  15. #include <linux/kernel.h>
  16. #include <linux/pci.h>
  17. #include <linux/kdev_t.h>
  18. #include <linux/delay.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/memblock.h>
  23. #include <asm/system.h>
  24. #include <asm/time.h>
  25. #include <asm/machdep.h>
  26. #include <asm/pci-bridge.h>
  27. #include <mm/mmu_decl.h>
  28. #include <asm/prom.h>
  29. #include <asm/udbg.h>
  30. #include <asm/mpic.h>
  31. #include <asm/i8259.h>
  32. #include <asm/swiotlb.h>
  33. #include <sysdev/fsl_soc.h>
  34. #include <sysdev/fsl_pci.h>
  35. #undef DEBUG
  36. #ifdef DEBUG
  37. #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
  38. #else
  39. #define DBG(fmt, args...)
  40. #endif
  41. #ifdef CONFIG_PPC_I8259
  42. static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
  43. {
  44. struct irq_chip *chip = irq_desc_get_chip(desc);
  45. unsigned int cascade_irq = i8259_irq();
  46. if (cascade_irq != NO_IRQ) {
  47. generic_handle_irq(cascade_irq);
  48. }
  49. chip->irq_eoi(&desc->irq_data);
  50. }
  51. #endif /* CONFIG_PPC_I8259 */
  52. void __init mpc85xx_ds_pic_init(void)
  53. {
  54. struct mpic *mpic;
  55. struct resource r;
  56. struct device_node *np;
  57. #ifdef CONFIG_PPC_I8259
  58. struct device_node *cascade_node = NULL;
  59. int cascade_irq;
  60. #endif
  61. unsigned long root = of_get_flat_dt_root();
  62. np = of_find_node_by_type(NULL, "open-pic");
  63. if (np == NULL) {
  64. printk(KERN_ERR "Could not find open-pic node\n");
  65. return;
  66. }
  67. if (of_address_to_resource(np, 0, &r)) {
  68. printk(KERN_ERR "Failed to map mpic register space\n");
  69. of_node_put(np);
  70. return;
  71. }
  72. if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
  73. mpic = mpic_alloc(np, r.start,
  74. MPIC_PRIMARY |
  75. MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
  76. 0, 256, " OpenPIC ");
  77. } else {
  78. mpic = mpic_alloc(np, r.start,
  79. MPIC_PRIMARY | MPIC_WANTS_RESET |
  80. MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
  81. MPIC_SINGLE_DEST_CPU,
  82. 0, 256, " OpenPIC ");
  83. }
  84. BUG_ON(mpic == NULL);
  85. of_node_put(np);
  86. mpic_init(mpic);
  87. #ifdef CONFIG_PPC_I8259
  88. /* Initialize the i8259 controller */
  89. for_each_node_by_type(np, "interrupt-controller")
  90. if (of_device_is_compatible(np, "chrp,iic")) {
  91. cascade_node = np;
  92. break;
  93. }
  94. if (cascade_node == NULL) {
  95. printk(KERN_DEBUG "Could not find i8259 PIC\n");
  96. return;
  97. }
  98. cascade_irq = irq_of_parse_and_map(cascade_node, 0);
  99. if (cascade_irq == NO_IRQ) {
  100. printk(KERN_ERR "Failed to map cascade interrupt\n");
  101. return;
  102. }
  103. DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq);
  104. i8259_init(cascade_node, 0);
  105. of_node_put(cascade_node);
  106. irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
  107. #endif /* CONFIG_PPC_I8259 */
  108. }
  109. #ifdef CONFIG_PCI
  110. static int primary_phb_addr;
  111. extern int uli_exclude_device(struct pci_controller *hose,
  112. u_char bus, u_char devfn);
  113. static int mpc85xx_exclude_device(struct pci_controller *hose,
  114. u_char bus, u_char devfn)
  115. {
  116. struct device_node* node;
  117. struct resource rsrc;
  118. node = hose->dn;
  119. of_address_to_resource(node, 0, &rsrc);
  120. if ((rsrc.start & 0xfffff) == primary_phb_addr) {
  121. return uli_exclude_device(hose, bus, devfn);
  122. }
  123. return PCIBIOS_SUCCESSFUL;
  124. }
  125. #endif /* CONFIG_PCI */
  126. /*
  127. * Setup the architecture
  128. */
  129. #ifdef CONFIG_SMP
  130. extern void __init mpc85xx_smp_init(void);
  131. #endif
  132. static void __init mpc85xx_ds_setup_arch(void)
  133. {
  134. #ifdef CONFIG_PCI
  135. struct device_node *np;
  136. struct pci_controller *hose;
  137. #endif
  138. dma_addr_t max = 0xffffffff;
  139. if (ppc_md.progress)
  140. ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
  141. #ifdef CONFIG_PCI
  142. for_each_node_by_type(np, "pci") {
  143. if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
  144. of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
  145. of_device_is_compatible(np, "fsl,p2020-pcie")) {
  146. struct resource rsrc;
  147. of_address_to_resource(np, 0, &rsrc);
  148. if ((rsrc.start & 0xfffff) == primary_phb_addr)
  149. fsl_add_bridge(np, 1);
  150. else
  151. fsl_add_bridge(np, 0);
  152. hose = pci_find_hose_for_OF_device(np);
  153. max = min(max, hose->dma_window_base_cur +
  154. hose->dma_window_size);
  155. }
  156. }
  157. ppc_md.pci_exclude_device = mpc85xx_exclude_device;
  158. #endif
  159. #ifdef CONFIG_SMP
  160. mpc85xx_smp_init();
  161. #endif
  162. #ifdef CONFIG_SWIOTLB
  163. if (memblock_end_of_DRAM() > max) {
  164. ppc_swiotlb_enable = 1;
  165. set_pci_dma_ops(&swiotlb_dma_ops);
  166. ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
  167. }
  168. #endif
  169. printk("MPC85xx DS board from Freescale Semiconductor\n");
  170. }
  171. /*
  172. * Called very early, device-tree isn't unflattened
  173. */
  174. static int __init mpc8544_ds_probe(void)
  175. {
  176. unsigned long root = of_get_flat_dt_root();
  177. if (of_flat_dt_is_compatible(root, "MPC8544DS")) {
  178. #ifdef CONFIG_PCI
  179. primary_phb_addr = 0xb000;
  180. #endif
  181. return 1;
  182. }
  183. return 0;
  184. }
  185. static struct of_device_id __initdata mpc85xxds_ids[] = {
  186. { .type = "soc", },
  187. { .compatible = "soc", },
  188. { .compatible = "simple-bus", },
  189. { .compatible = "gianfar", },
  190. {},
  191. };
  192. static int __init mpc85xxds_publish_devices(void)
  193. {
  194. return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
  195. }
  196. machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
  197. machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
  198. machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
  199. machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
  200. machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
  201. machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier);
  202. /*
  203. * Called very early, device-tree isn't unflattened
  204. */
  205. static int __init mpc8572_ds_probe(void)
  206. {
  207. unsigned long root = of_get_flat_dt_root();
  208. if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) {
  209. #ifdef CONFIG_PCI
  210. primary_phb_addr = 0x8000;
  211. #endif
  212. return 1;
  213. }
  214. return 0;
  215. }
  216. /*
  217. * Called very early, device-tree isn't unflattened
  218. */
  219. static int __init p2020_ds_probe(void)
  220. {
  221. unsigned long root = of_get_flat_dt_root();
  222. if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
  223. #ifdef CONFIG_PCI
  224. primary_phb_addr = 0x9000;
  225. #endif
  226. return 1;
  227. }
  228. return 0;
  229. }
  230. define_machine(mpc8544_ds) {
  231. .name = "MPC8544 DS",
  232. .probe = mpc8544_ds_probe,
  233. .setup_arch = mpc85xx_ds_setup_arch,
  234. .init_IRQ = mpc85xx_ds_pic_init,
  235. #ifdef CONFIG_PCI
  236. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  237. #endif
  238. .get_irq = mpic_get_irq,
  239. .restart = fsl_rstcr_restart,
  240. .calibrate_decr = generic_calibrate_decr,
  241. .progress = udbg_progress,
  242. };
  243. define_machine(mpc8572_ds) {
  244. .name = "MPC8572 DS",
  245. .probe = mpc8572_ds_probe,
  246. .setup_arch = mpc85xx_ds_setup_arch,
  247. .init_IRQ = mpc85xx_ds_pic_init,
  248. #ifdef CONFIG_PCI
  249. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  250. #endif
  251. .get_irq = mpic_get_irq,
  252. .restart = fsl_rstcr_restart,
  253. .calibrate_decr = generic_calibrate_decr,
  254. .progress = udbg_progress,
  255. };
  256. define_machine(p2020_ds) {
  257. .name = "P2020 DS",
  258. .probe = p2020_ds_probe,
  259. .setup_arch = mpc85xx_ds_setup_arch,
  260. .init_IRQ = mpc85xx_ds_pic_init,
  261. #ifdef CONFIG_PCI
  262. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  263. #endif
  264. .get_irq = mpic_get_irq,
  265. .restart = fsl_rstcr_restart,
  266. .calibrate_decr = generic_calibrate_decr,
  267. .progress = udbg_progress,
  268. };