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arch
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arm
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plat-s5p
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include
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plat
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regs-srom.h

regs-srom.h 1.6 KB
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  1. /* linux/arch/arm/plat-s5p/include/plat/regs-srom.h
    2. 

  2.  *
    3. 

  3.  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
    4. 

  4.  *		http://www.samsung.com
    5. 

  5.  *
    6. 

  6.  * S5P SROMC register definitions
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11. */
    12. 

  12. 

  13. #ifndef __ASM_PLAT_S5P_REGS_SROM_H
    14. 

  14. #define __ASM_PLAT_S5P_REGS_SROM_H __FILE__
    15. 

  15. 

  16. #include <mach/map.h>
    17. 

  17. 

  18. #define S5P_SROMREG(x)		(S5P_VA_SROMC + (x))
    19. 

  19. 

  20. #define S5P_SROM_BW		S5P_SROMREG(0x0)
    21. 

  21. #define S5P_SROM_BC0		S5P_SROMREG(0x4)
    22. 

  22. #define S5P_SROM_BC1		S5P_SROMREG(0x8)
    23. 

  23. #define S5P_SROM_BC2		S5P_SROMREG(0xc)
    24. 

  24. #define S5P_SROM_BC3		S5P_SROMREG(0x10)
    25. 

  25. #define S5P_SROM_BC4		S5P_SROMREG(0x14)
    26. 

  26. #define S5P_SROM_BC5		S5P_SROMREG(0x18)
    27. 

  27. 

  28. /* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
    29. 

  29. 

  30. #define S5P_SROM_BW__DATAWIDTH__SHIFT		0
    31. 

  31. #define S5P_SROM_BW__ADDRMODE__SHIFT		1
    32. 

  32. #define S5P_SROM_BW__WAITENABLE__SHIFT		2
    33. 

  33. #define S5P_SROM_BW__BYTEENABLE__SHIFT		3
    34. 

  34. 

  35. #define S5P_SROM_BW__CS_MASK			0xf
    36. 

  36. 

  37. #define S5P_SROM_BW__NCS0__SHIFT		0
    38. 

  38. #define S5P_SROM_BW__NCS1__SHIFT		4
    39. 

  39. #define S5P_SROM_BW__NCS2__SHIFT		8
    40. 

  40. #define S5P_SROM_BW__NCS3__SHIFT		12
    41. 

  41. #define S5P_SROM_BW__NCS4__SHIFT		16
    42. 

  42. #define S5P_SROM_BW__NCS5__SHIFT		20
    43. 

  43. 

  44. /* applies to same to BCS0 - BCS3 */
    45. 

  45. 

  46. #define S5P_SROM_BCX__PMC__SHIFT		0
    47. 

  47. #define S5P_SROM_BCX__TACP__SHIFT		4
    48. 

  48. #define S5P_SROM_BCX__TCAH__SHIFT		8
    49. 

  49. #define S5P_SROM_BCX__TCOH__SHIFT		12
    50. 

  50. #define S5P_SROM_BCX__TACC__SHIFT		16
    51. 

  51. #define S5P_SROM_BCX__TCOS__SHIFT		24
    52. 

  52. #define S5P_SROM_BCX__TACS__SHIFT		28
    53. 

  53. 

  54. #endif /* __ASM_PLAT_S5P_REGS_SROM_H */
    55.