irqs.h 2.0 KB

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  1. /*
  2. * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3. */
  4. /*
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #ifndef __ASM_ARCH_MXC_IRQS_H__
  10. #define __ASM_ARCH_MXC_IRQS_H__
  11. /*
  12. * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
  13. */
  14. #ifdef CONFIG_MXC_TZIC
  15. #define MXC_INTERNAL_IRQS 128
  16. #else
  17. #define MXC_INTERNAL_IRQS 64
  18. #endif
  19. #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
  20. /* these are ordered by size to support multi-SoC kernels */
  21. #if defined CONFIG_SOC_IMX53
  22. #define MXC_GPIO_IRQS (32 * 7)
  23. #elif defined CONFIG_ARCH_MX2
  24. #define MXC_GPIO_IRQS (32 * 6)
  25. #elif defined CONFIG_SOC_IMX50
  26. #define MXC_GPIO_IRQS (32 * 6)
  27. #elif defined CONFIG_ARCH_MX1
  28. #define MXC_GPIO_IRQS (32 * 4)
  29. #elif defined CONFIG_ARCH_MX25
  30. #define MXC_GPIO_IRQS (32 * 4)
  31. #elif defined CONFIG_SOC_IMX51
  32. #define MXC_GPIO_IRQS (32 * 4)
  33. #elif defined CONFIG_ARCH_MXC91231
  34. #define MXC_GPIO_IRQS (32 * 4)
  35. #elif defined CONFIG_ARCH_MX3
  36. #define MXC_GPIO_IRQS (32 * 3)
  37. #endif
  38. /*
  39. * The next 16 interrupts are for board specific purposes. Since
  40. * the kernel can only run on one machine at a time, we can re-use
  41. * these. If you need more, increase MXC_BOARD_IRQS, but keep it
  42. * within sensible limits.
  43. */
  44. #define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
  45. #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
  46. #define MXC_BOARD_IRQS 80
  47. #else
  48. #define MXC_BOARD_IRQS 16
  49. #endif
  50. #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
  51. #ifdef CONFIG_MX3_IPU_IRQS
  52. #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
  53. #else
  54. #define MX3_IPU_IRQS 0
  55. #endif
  56. /* REVISIT: Add IPU irqs on IMX51 */
  57. #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
  58. extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
  59. /* all normal IRQs can be FIQs */
  60. #define FIQ_START 0
  61. /* switch between IRQ and FIQ */
  62. extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
  63. #endif /* __ASM_ARCH_MXC_IRQS_H__ */