timer.c 4.5 KB

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  1. /*
  2. * arch/arm/mach-vt8500/timer.c
  3. *
  4. * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/io.h>
  21. #include <linux/irq.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/clocksource.h>
  24. #include <linux/clockchips.h>
  25. #include <linux/delay.h>
  26. #include <asm/mach/time.h>
  27. #include "devices.h"
  28. #define VT8500_TIMER_OFFSET 0x0100
  29. #define TIMER_MATCH_VAL 0x0000
  30. #define TIMER_COUNT_VAL 0x0010
  31. #define TIMER_STATUS_VAL 0x0014
  32. #define TIMER_IER_VAL 0x001c /* interrupt enable */
  33. #define TIMER_CTRL_VAL 0x0020
  34. #define TIMER_AS_VAL 0x0024 /* access status */
  35. #define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */
  36. #define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */
  37. #define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */
  38. #define VT8500_TIMER_HZ 3000000
  39. #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
  40. static void __iomem *regbase;
  41. static cycle_t vt8500_timer_read(struct clocksource *cs)
  42. {
  43. int loops = msecs_to_loops(10);
  44. writel(3, regbase + TIMER_CTRL_VAL);
  45. while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
  46. && --loops)
  47. cpu_relax();
  48. return readl(regbase + TIMER_COUNT_VAL);
  49. }
  50. struct clocksource clocksource = {
  51. .name = "vt8500_timer",
  52. .rating = 200,
  53. .read = vt8500_timer_read,
  54. .mask = CLOCKSOURCE_MASK(32),
  55. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  56. };
  57. static int vt8500_timer_set_next_event(unsigned long cycles,
  58. struct clock_event_device *evt)
  59. {
  60. int loops = msecs_to_loops(10);
  61. cycle_t alarm = clocksource.read(&clocksource) + cycles;
  62. while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
  63. && --loops)
  64. cpu_relax();
  65. writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
  66. if ((signed)(alarm - clocksource.read(&clocksource)) <= 16)
  67. return -ETIME;
  68. writel(1, regbase + TIMER_IER_VAL);
  69. return 0;
  70. }
  71. static void vt8500_timer_set_mode(enum clock_event_mode mode,
  72. struct clock_event_device *evt)
  73. {
  74. switch (mode) {
  75. case CLOCK_EVT_MODE_RESUME:
  76. case CLOCK_EVT_MODE_PERIODIC:
  77. break;
  78. case CLOCK_EVT_MODE_ONESHOT:
  79. case CLOCK_EVT_MODE_UNUSED:
  80. case CLOCK_EVT_MODE_SHUTDOWN:
  81. writel(readl(regbase + TIMER_CTRL_VAL) | 1,
  82. regbase + TIMER_CTRL_VAL);
  83. writel(0, regbase + TIMER_IER_VAL);
  84. break;
  85. }
  86. }
  87. struct clock_event_device clockevent = {
  88. .name = "vt8500_timer",
  89. .features = CLOCK_EVT_FEAT_ONESHOT,
  90. .rating = 200,
  91. .set_next_event = vt8500_timer_set_next_event,
  92. .set_mode = vt8500_timer_set_mode,
  93. };
  94. static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
  95. {
  96. struct clock_event_device *evt = dev_id;
  97. writel(0xf, regbase + TIMER_STATUS_VAL);
  98. evt->event_handler(evt);
  99. return IRQ_HANDLED;
  100. }
  101. struct irqaction irq = {
  102. .name = "vt8500_timer",
  103. .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  104. .handler = vt8500_timer_interrupt,
  105. .dev_id = &clockevent,
  106. };
  107. static void __init vt8500_timer_init(void)
  108. {
  109. regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
  110. if (!regbase)
  111. printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
  112. writel(1, regbase + TIMER_CTRL_VAL);
  113. writel(0xf, regbase + TIMER_STATUS_VAL);
  114. writel(~0, regbase + TIMER_MATCH_VAL);
  115. if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
  116. printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
  117. clocksource.name);
  118. clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
  119. /* copy-pasted from mach-msm; no idea */
  120. clockevent.max_delta_ns =
  121. clockevent_delta2ns(0xf0000000, &clockevent);
  122. clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
  123. clockevent.cpumask = cpumask_of(0);
  124. if (setup_irq(wmt_timer_irq, &irq))
  125. printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
  126. clockevent.name);
  127. clockevents_register_device(&clockevent);
  128. }
  129. struct sys_timer vt8500_timer = {
  130. .init = vt8500_timer_init
  131. };