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mach-spear3xx
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mach
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spear320.h

spear320.h 2.1 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-spear3xx/include/mach/spear320.h
    3. 

  3.  *
    4. 

  4.  * SPEAr320 Machine specific definition
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2009 ST Microelectronics
    7. 

  7.  * Viresh Kumar<viresh.kumar@st.com>
    8. 

  8.  *
    9. 

  9.  * This file is licensed under the terms of the GNU General Public
    10. 

  10.  * License version 2. This program is licensed "as is" without any
    11. 

  11.  * warranty of any kind, whether express or implied.
    12. 

  12.  */
    13. 

  13. 

  14. #ifdef	CONFIG_MACH_SPEAR320
    15. 

  15. 

  16. #ifndef __MACH_SPEAR320_H
    17. 

  17. #define __MACH_SPEAR320_H
    18. 

  18. 

  19. #define SPEAR320_EMI_CTRL_BASE		UL(0x40000000)
    20. 

  20. #define SPEAR320_FSMC_BASE		UL(0x4C000000)
    21. 

  21. #define SPEAR320_NAND_BASE		UL(0x50000000)
    22. 

  22. #define SPEAR320_I2S_BASE		UL(0x60000000)
    23. 

  23. #define SPEAR320_SDHCI_BASE		UL(0x70000000)
    24. 

  24. #define SPEAR320_CLCD_BASE		UL(0x90000000)
    25. 

  25. #define SPEAR320_PAR_PORT_BASE		UL(0xA0000000)
    26. 

  26. #define SPEAR320_CAN0_BASE		UL(0xA1000000)
    27. 

  27. #define SPEAR320_CAN1_BASE		UL(0xA2000000)
    28. 

  28. #define SPEAR320_UART1_BASE		UL(0xA3000000)
    29. 

  29. #define SPEAR320_UART2_BASE		UL(0xA4000000)
    30. 

  30. #define SPEAR320_SSP0_BASE		UL(0xA5000000)
    31. 

  31. #define SPEAR320_SSP1_BASE		UL(0xA6000000)
    32. 

  32. #define SPEAR320_I2C_BASE		UL(0xA7000000)
    33. 

  33. #define SPEAR320_PWM_BASE		UL(0xA8000000)
    34. 

  34. #define SPEAR320_SMII0_BASE		UL(0xAA000000)
    35. 

  35. #define SPEAR320_SMII1_BASE		UL(0xAB000000)
    36. 

  36. #define SPEAR320_SOC_CONFIG_BASE	UL(0xB3000000)
    37. 

  37. 

  38. /* Interrupt registers offsets and masks */
    39. 

  39. #define INT_STS_MASK_REG		0x04
    40. 

  40. #define INT_CLR_MASK_REG		0x04
    41. 

  41. #define INT_ENB_MASK_REG		0x08
    42. 

  42. #define GPIO_IRQ_MASK			(1 << 0)
    43. 

  43. #define I2S_PLAY_IRQ_MASK		(1 << 1)
    44. 

  44. #define I2S_REC_IRQ_MASK		(1 << 2)
    45. 

  45. #define EMI_IRQ_MASK			(1 << 7)
    46. 

  46. #define CLCD_IRQ_MASK			(1 << 8)
    47. 

  47. #define SPP_IRQ_MASK			(1 << 9)
    48. 

  48. #define SDHCI_IRQ_MASK			(1 << 10)
    49. 

  49. #define CAN_U_IRQ_MASK			(1 << 11)
    50. 

  50. #define CAN_L_IRQ_MASK			(1 << 12)
    51. 

  51. #define UART1_IRQ_MASK			(1 << 13)
    52. 

  52. #define UART2_IRQ_MASK			(1 << 14)
    53. 

  53. #define SSP1_IRQ_MASK			(1 << 15)
    54. 

  54. #define SSP2_IRQ_MASK			(1 << 16)
    55. 

  55. #define SMII0_IRQ_MASK			(1 << 17)
    56. 

  56. #define MII1_SMII1_IRQ_MASK		(1 << 18)
    57. 

  57. #define WAKEUP_SMII0_IRQ_MASK		(1 << 19)
    58. 

  58. #define WAKEUP_MII1_SMII1_IRQ_MASK	(1 << 20)
    59. 

  59. #define I2C1_IRQ_MASK			(1 << 21)
    60. 

  60. 

  61. #define SHIRQ_RAS1_MASK			0x000380
    62. 

  62. #define SHIRQ_RAS3_MASK			0x000007
    63. 

  63. #define SHIRQ_INTRCOMM_RAS_MASK		0x3FF800
    64. 

  64. 

  65. #endif /* __MACH_SPEAR320_H */
    66. 

  66. 

  67. #endif /* CONFIG_MACH_SPEAR320 */
    68.