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mach-spear3xx
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mach
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spear310.h

spear310.h 1.8 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-spear3xx/include/mach/spear310.h
    3. 

  3.  *
    4. 

  4.  * SPEAr310 Machine specific definition
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2009 ST Microelectronics
    7. 

  7.  * Viresh Kumar<viresh.kumar@st.com>
    8. 

  8.  *
    9. 

  9.  * This file is licensed under the terms of the GNU General Public
    10. 

  10.  * License version 2. This program is licensed "as is" without any
    11. 

  11.  * warranty of any kind, whether express or implied.
    12. 

  12.  */
    13. 

  13. 

  14. #ifdef	CONFIG_MACH_SPEAR310
    15. 

  15. 

  16. #ifndef __MACH_SPEAR310_H
    17. 

  17. #define __MACH_SPEAR310_H
    18. 

  18. 

  19. #define SPEAR310_NAND_BASE		UL(0x40000000)
    20. 

  20. #define SPEAR310_FSMC_BASE		UL(0x44000000)
    21. 

  21. #define SPEAR310_UART1_BASE		UL(0xB2000000)
    22. 

  22. #define SPEAR310_UART2_BASE		UL(0xB2080000)
    23. 

  23. #define SPEAR310_UART3_BASE		UL(0xB2100000)
    24. 

  24. #define SPEAR310_UART4_BASE		UL(0xB2180000)
    25. 

  25. #define SPEAR310_UART5_BASE		UL(0xB2200000)
    26. 

  26. #define SPEAR310_HDLC_BASE		UL(0xB2800000)
    27. 

  27. #define SPEAR310_RS485_0_BASE		UL(0xB3000000)
    28. 

  28. #define SPEAR310_RS485_1_BASE		UL(0xB3800000)
    29. 

  29. #define SPEAR310_SOC_CONFIG_BASE	UL(0xB4000000)
    30. 

  30. 

  31. /* Interrupt registers offsets and masks */
    32. 

  32. #define INT_STS_MASK_REG		0x04
    33. 

  33. #define SMII0_IRQ_MASK			(1 << 0)
    34. 

  34. #define SMII1_IRQ_MASK			(1 << 1)
    35. 

  35. #define SMII2_IRQ_MASK			(1 << 2)
    36. 

  36. #define SMII3_IRQ_MASK			(1 << 3)
    37. 

  37. #define WAKEUP_SMII0_IRQ_MASK		(1 << 4)
    38. 

  38. #define WAKEUP_SMII1_IRQ_MASK		(1 << 5)
    39. 

  39. #define WAKEUP_SMII2_IRQ_MASK		(1 << 6)
    40. 

  40. #define WAKEUP_SMII3_IRQ_MASK		(1 << 7)
    41. 

  41. #define UART1_IRQ_MASK			(1 << 8)
    42. 

  42. #define UART2_IRQ_MASK			(1 << 9)
    43. 

  43. #define UART3_IRQ_MASK			(1 << 10)
    44. 

  44. #define UART4_IRQ_MASK			(1 << 11)
    45. 

  45. #define UART5_IRQ_MASK			(1 << 12)
    46. 

  46. #define EMI_IRQ_MASK			(1 << 13)
    47. 

  47. #define TDM_HDLC_IRQ_MASK		(1 << 14)
    48. 

  48. #define RS485_0_IRQ_MASK		(1 << 15)
    49. 

  49. #define RS485_1_IRQ_MASK		(1 << 16)
    50. 

  50. 

  51. #define SHIRQ_RAS1_MASK			0x000FF
    52. 

  52. #define SHIRQ_RAS2_MASK			0x01F00
    53. 

  53. #define SHIRQ_RAS3_MASK			0x02000
    54. 

  54. #define SHIRQ_INTRCOMM_RAS_MASK		0x1C000
    55. 

  55. 

  56. #endif /* __MACH_SPEAR310_H */
    57. 

  57. 

  58. #endif /* CONFIG_MACH_SPEAR310 */
    59.