dev-spi.c 4.6 KB

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  1. /* linux/arch/arm/mach-s5p64x0/dev-spi.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  7. * Jaswinder Singh <jassi.brar@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/platform_device.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/gpio.h>
  16. #include <mach/dma.h>
  17. #include <mach/map.h>
  18. #include <mach/irqs.h>
  19. #include <mach/regs-clock.h>
  20. #include <mach/spi-clocks.h>
  21. #include <plat/s3c64xx-spi.h>
  22. #include <plat/gpio-cfg.h>
  23. static char *s5p64x0_spi_src_clks[] = {
  24. [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
  25. [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
  26. };
  27. /* SPI Controller platform_devices */
  28. /* Since we emulate multi-cs capability, we do not touch the CS.
  29. * The emulated CS is toggled by board specific mechanism, as it can
  30. * be either some immediate GPIO or some signal out of some other
  31. * chip in between ... or some yet another way.
  32. * We simply do not assume anything about CS.
  33. */
  34. static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
  35. {
  36. unsigned int base;
  37. switch (pdev->id) {
  38. case 0:
  39. base = S5P6440_GPC(0);
  40. break;
  41. case 1:
  42. base = S5P6440_GPC(4);
  43. break;
  44. default:
  45. dev_err(&pdev->dev, "Invalid SPI Controller number!");
  46. return -EINVAL;
  47. }
  48. s3c_gpio_cfgall_range(base, 3,
  49. S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  50. return 0;
  51. }
  52. static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
  53. {
  54. unsigned int base;
  55. switch (pdev->id) {
  56. case 0:
  57. base = S5P6450_GPC(0);
  58. break;
  59. case 1:
  60. base = S5P6450_GPC(4);
  61. break;
  62. default:
  63. dev_err(&pdev->dev, "Invalid SPI Controller number!");
  64. return -EINVAL;
  65. }
  66. s3c_gpio_cfgall_range(base, 3,
  67. S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  68. return 0;
  69. }
  70. static struct resource s5p64x0_spi0_resource[] = {
  71. [0] = {
  72. .start = S5P64X0_PA_SPI0,
  73. .end = S5P64X0_PA_SPI0 + 0x100 - 1,
  74. .flags = IORESOURCE_MEM,
  75. },
  76. [1] = {
  77. .start = DMACH_SPI0_TX,
  78. .end = DMACH_SPI0_TX,
  79. .flags = IORESOURCE_DMA,
  80. },
  81. [2] = {
  82. .start = DMACH_SPI0_RX,
  83. .end = DMACH_SPI0_RX,
  84. .flags = IORESOURCE_DMA,
  85. },
  86. [3] = {
  87. .start = IRQ_SPI0,
  88. .end = IRQ_SPI0,
  89. .flags = IORESOURCE_IRQ,
  90. },
  91. };
  92. static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
  93. .cfg_gpio = s5p6440_spi_cfg_gpio,
  94. .fifo_lvl_mask = 0x1ff,
  95. .rx_lvl_offset = 15,
  96. };
  97. static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
  98. .cfg_gpio = s5p6450_spi_cfg_gpio,
  99. .fifo_lvl_mask = 0x1ff,
  100. .rx_lvl_offset = 15,
  101. };
  102. static u64 spi_dmamask = DMA_BIT_MASK(32);
  103. struct platform_device s5p64x0_device_spi0 = {
  104. .name = "s3c64xx-spi",
  105. .id = 0,
  106. .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
  107. .resource = s5p64x0_spi0_resource,
  108. .dev = {
  109. .dma_mask = &spi_dmamask,
  110. .coherent_dma_mask = DMA_BIT_MASK(32),
  111. },
  112. };
  113. static struct resource s5p64x0_spi1_resource[] = {
  114. [0] = {
  115. .start = S5P64X0_PA_SPI1,
  116. .end = S5P64X0_PA_SPI1 + 0x100 - 1,
  117. .flags = IORESOURCE_MEM,
  118. },
  119. [1] = {
  120. .start = DMACH_SPI1_TX,
  121. .end = DMACH_SPI1_TX,
  122. .flags = IORESOURCE_DMA,
  123. },
  124. [2] = {
  125. .start = DMACH_SPI1_RX,
  126. .end = DMACH_SPI1_RX,
  127. .flags = IORESOURCE_DMA,
  128. },
  129. [3] = {
  130. .start = IRQ_SPI1,
  131. .end = IRQ_SPI1,
  132. .flags = IORESOURCE_IRQ,
  133. },
  134. };
  135. static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
  136. .cfg_gpio = s5p6440_spi_cfg_gpio,
  137. .fifo_lvl_mask = 0x7f,
  138. .rx_lvl_offset = 15,
  139. };
  140. static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
  141. .cfg_gpio = s5p6450_spi_cfg_gpio,
  142. .fifo_lvl_mask = 0x7f,
  143. .rx_lvl_offset = 15,
  144. };
  145. struct platform_device s5p64x0_device_spi1 = {
  146. .name = "s3c64xx-spi",
  147. .id = 1,
  148. .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
  149. .resource = s5p64x0_spi1_resource,
  150. .dev = {
  151. .dma_mask = &spi_dmamask,
  152. .coherent_dma_mask = DMA_BIT_MASK(32),
  153. },
  154. };
  155. void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
  156. {
  157. unsigned int id;
  158. struct s3c64xx_spi_info *pd;
  159. id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
  160. /* Reject invalid configuration */
  161. if (!num_cs || src_clk_nr < 0
  162. || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
  163. printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
  164. return;
  165. }
  166. switch (cntrlr) {
  167. case 0:
  168. if (id == 0x50000)
  169. pd = &s5p6450_spi0_pdata;
  170. else
  171. pd = &s5p6440_spi0_pdata;
  172. s5p64x0_device_spi0.dev.platform_data = pd;
  173. break;
  174. case 1:
  175. if (id == 0x50000)
  176. pd = &s5p6450_spi1_pdata;
  177. else
  178. pd = &s5p6440_spi1_pdata;
  179. s5p64x0_device_spi1.dev.platform_data = pd;
  180. break;
  181. default:
  182. printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
  183. __func__, cntrlr);
  184. return;
  185. }
  186. pd->num_cs = num_cs;
  187. pd->src_clk_nr = src_clk_nr;
  188. pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
  189. }