dev-spi.c 4.5 KB

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  1. /* linux/arch/arm/plat-s3c64xx/dev-spi.c
  2. *
  3. * Copyright (C) 2009 Samsung Electronics Ltd.
  4. * Jaswinder Singh <jassi.brar@samsung.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/string.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/gpio.h>
  15. #include <mach/dma.h>
  16. #include <mach/map.h>
  17. #include <mach/gpio-bank-c.h>
  18. #include <mach/spi-clocks.h>
  19. #include <mach/irqs.h>
  20. #include <plat/s3c64xx-spi.h>
  21. #include <plat/gpio-cfg.h>
  22. #include <plat/devs.h>
  23. static char *spi_src_clks[] = {
  24. [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
  25. [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
  26. [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
  27. };
  28. /* SPI Controller platform_devices */
  29. /* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
  30. * The emulated CS is toggled by board specific mechanism, as it can
  31. * be either some immediate GPIO or some signal out of some other
  32. * chip in between ... or some yet another way.
  33. * We simply do not assume anything about CS.
  34. */
  35. static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
  36. {
  37. switch (pdev->id) {
  38. case 0:
  39. s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
  40. s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO);
  41. s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO);
  42. s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP);
  43. s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP);
  44. s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP);
  45. break;
  46. case 1:
  47. s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1);
  48. s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1);
  49. s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1);
  50. s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP);
  51. s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP);
  52. s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP);
  53. break;
  54. default:
  55. dev_err(&pdev->dev, "Invalid SPI Controller number!");
  56. return -EINVAL;
  57. }
  58. return 0;
  59. }
  60. static struct resource s3c64xx_spi0_resource[] = {
  61. [0] = {
  62. .start = S3C64XX_PA_SPI0,
  63. .end = S3C64XX_PA_SPI0 + 0x100 - 1,
  64. .flags = IORESOURCE_MEM,
  65. },
  66. [1] = {
  67. .start = DMACH_SPI0_TX,
  68. .end = DMACH_SPI0_TX,
  69. .flags = IORESOURCE_DMA,
  70. },
  71. [2] = {
  72. .start = DMACH_SPI0_RX,
  73. .end = DMACH_SPI0_RX,
  74. .flags = IORESOURCE_DMA,
  75. },
  76. [3] = {
  77. .start = IRQ_SPI0,
  78. .end = IRQ_SPI0,
  79. .flags = IORESOURCE_IRQ,
  80. },
  81. };
  82. static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
  83. .cfg_gpio = s3c64xx_spi_cfg_gpio,
  84. .fifo_lvl_mask = 0x7f,
  85. .rx_lvl_offset = 13,
  86. };
  87. static u64 spi_dmamask = DMA_BIT_MASK(32);
  88. struct platform_device s3c64xx_device_spi0 = {
  89. .name = "s3c64xx-spi",
  90. .id = 0,
  91. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  92. .resource = s3c64xx_spi0_resource,
  93. .dev = {
  94. .dma_mask = &spi_dmamask,
  95. .coherent_dma_mask = DMA_BIT_MASK(32),
  96. .platform_data = &s3c64xx_spi0_pdata,
  97. },
  98. };
  99. EXPORT_SYMBOL(s3c64xx_device_spi0);
  100. static struct resource s3c64xx_spi1_resource[] = {
  101. [0] = {
  102. .start = S3C64XX_PA_SPI1,
  103. .end = S3C64XX_PA_SPI1 + 0x100 - 1,
  104. .flags = IORESOURCE_MEM,
  105. },
  106. [1] = {
  107. .start = DMACH_SPI1_TX,
  108. .end = DMACH_SPI1_TX,
  109. .flags = IORESOURCE_DMA,
  110. },
  111. [2] = {
  112. .start = DMACH_SPI1_RX,
  113. .end = DMACH_SPI1_RX,
  114. .flags = IORESOURCE_DMA,
  115. },
  116. [3] = {
  117. .start = IRQ_SPI1,
  118. .end = IRQ_SPI1,
  119. .flags = IORESOURCE_IRQ,
  120. },
  121. };
  122. static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
  123. .cfg_gpio = s3c64xx_spi_cfg_gpio,
  124. .fifo_lvl_mask = 0x7f,
  125. .rx_lvl_offset = 13,
  126. };
  127. struct platform_device s3c64xx_device_spi1 = {
  128. .name = "s3c64xx-spi",
  129. .id = 1,
  130. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  131. .resource = s3c64xx_spi1_resource,
  132. .dev = {
  133. .dma_mask = &spi_dmamask,
  134. .coherent_dma_mask = DMA_BIT_MASK(32),
  135. .platform_data = &s3c64xx_spi1_pdata,
  136. },
  137. };
  138. EXPORT_SYMBOL(s3c64xx_device_spi1);
  139. void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
  140. {
  141. struct s3c64xx_spi_info *pd;
  142. /* Reject invalid configuration */
  143. if (!num_cs || src_clk_nr < 0
  144. || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
  145. printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
  146. return;
  147. }
  148. switch (cntrlr) {
  149. case 0:
  150. pd = &s3c64xx_spi0_pdata;
  151. break;
  152. case 1:
  153. pd = &s3c64xx_spi1_pdata;
  154. break;
  155. default:
  156. printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
  157. __func__, cntrlr);
  158. return;
  159. }
  160. pd->num_cs = num_cs;
  161. pd->src_clk_nr = src_clk_nr;
  162. pd->src_clk_name = spi_src_clks[src_clk_nr];
  163. }