devices.c 21 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include <asm/pmu.h>
  9. #include <mach/udc.h>
  10. #include <mach/pxa3xx-u2d.h>
  11. #include <mach/pxafb.h>
  12. #include <mach/mmc.h>
  13. #include <mach/irda.h>
  14. #include <mach/ohci.h>
  15. #include <plat/pxa27x_keypad.h>
  16. #include <mach/camera.h>
  17. #include <mach/audio.h>
  18. #include <mach/hardware.h>
  19. #include <plat/pxa3xx_nand.h>
  20. #include "devices.h"
  21. #include "generic.h"
  22. void __init pxa_register_device(struct platform_device *dev, void *data)
  23. {
  24. int ret;
  25. dev->dev.platform_data = data;
  26. ret = platform_device_register(dev);
  27. if (ret)
  28. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  29. }
  30. static struct resource pxa_resource_pmu = {
  31. .start = IRQ_PMU,
  32. .end = IRQ_PMU,
  33. .flags = IORESOURCE_IRQ,
  34. };
  35. struct platform_device pxa_device_pmu = {
  36. .name = "arm-pmu",
  37. .id = ARM_PMU_DEVICE_CPU,
  38. .resource = &pxa_resource_pmu,
  39. .num_resources = 1,
  40. };
  41. static struct resource pxamci_resources[] = {
  42. [0] = {
  43. .start = 0x41100000,
  44. .end = 0x41100fff,
  45. .flags = IORESOURCE_MEM,
  46. },
  47. [1] = {
  48. .start = IRQ_MMC,
  49. .end = IRQ_MMC,
  50. .flags = IORESOURCE_IRQ,
  51. },
  52. [2] = {
  53. .start = 21,
  54. .end = 21,
  55. .flags = IORESOURCE_DMA,
  56. },
  57. [3] = {
  58. .start = 22,
  59. .end = 22,
  60. .flags = IORESOURCE_DMA,
  61. },
  62. };
  63. static u64 pxamci_dmamask = 0xffffffffUL;
  64. struct platform_device pxa_device_mci = {
  65. .name = "pxa2xx-mci",
  66. .id = 0,
  67. .dev = {
  68. .dma_mask = &pxamci_dmamask,
  69. .coherent_dma_mask = 0xffffffff,
  70. },
  71. .num_resources = ARRAY_SIZE(pxamci_resources),
  72. .resource = pxamci_resources,
  73. };
  74. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  75. {
  76. pxa_register_device(&pxa_device_mci, info);
  77. }
  78. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  79. .gpio_pullup = -1,
  80. .gpio_vbus = -1,
  81. };
  82. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  83. {
  84. memcpy(&pxa_udc_info, info, sizeof *info);
  85. }
  86. static struct resource pxa2xx_udc_resources[] = {
  87. [0] = {
  88. .start = 0x40600000,
  89. .end = 0x4060ffff,
  90. .flags = IORESOURCE_MEM,
  91. },
  92. [1] = {
  93. .start = IRQ_USB,
  94. .end = IRQ_USB,
  95. .flags = IORESOURCE_IRQ,
  96. },
  97. };
  98. static u64 udc_dma_mask = ~(u32)0;
  99. struct platform_device pxa25x_device_udc = {
  100. .name = "pxa25x-udc",
  101. .id = -1,
  102. .resource = pxa2xx_udc_resources,
  103. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  104. .dev = {
  105. .platform_data = &pxa_udc_info,
  106. .dma_mask = &udc_dma_mask,
  107. }
  108. };
  109. struct platform_device pxa27x_device_udc = {
  110. .name = "pxa27x-udc",
  111. .id = -1,
  112. .resource = pxa2xx_udc_resources,
  113. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  114. .dev = {
  115. .platform_data = &pxa_udc_info,
  116. .dma_mask = &udc_dma_mask,
  117. }
  118. };
  119. #ifdef CONFIG_PXA3xx
  120. static struct resource pxa3xx_u2d_resources[] = {
  121. [0] = {
  122. .start = 0x54100000,
  123. .end = 0x54100fff,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [1] = {
  127. .start = IRQ_USB2,
  128. .end = IRQ_USB2,
  129. .flags = IORESOURCE_IRQ,
  130. },
  131. };
  132. struct platform_device pxa3xx_device_u2d = {
  133. .name = "pxa3xx-u2d",
  134. .id = -1,
  135. .resource = pxa3xx_u2d_resources,
  136. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  137. };
  138. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  139. {
  140. pxa_register_device(&pxa3xx_device_u2d, info);
  141. }
  142. #endif /* CONFIG_PXA3xx */
  143. static struct resource pxafb_resources[] = {
  144. [0] = {
  145. .start = 0x44000000,
  146. .end = 0x4400ffff,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. [1] = {
  150. .start = IRQ_LCD,
  151. .end = IRQ_LCD,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static u64 fb_dma_mask = ~(u64)0;
  156. struct platform_device pxa_device_fb = {
  157. .name = "pxa2xx-fb",
  158. .id = -1,
  159. .dev = {
  160. .dma_mask = &fb_dma_mask,
  161. .coherent_dma_mask = 0xffffffff,
  162. },
  163. .num_resources = ARRAY_SIZE(pxafb_resources),
  164. .resource = pxafb_resources,
  165. };
  166. void __init set_pxa_fb_info(struct pxafb_mach_info *info)
  167. {
  168. pxa_register_device(&pxa_device_fb, info);
  169. }
  170. void __init set_pxa_fb_parent(struct device *parent_dev)
  171. {
  172. pxa_device_fb.dev.parent = parent_dev;
  173. }
  174. static struct resource pxa_resource_ffuart[] = {
  175. {
  176. .start = 0x40100000,
  177. .end = 0x40100023,
  178. .flags = IORESOURCE_MEM,
  179. }, {
  180. .start = IRQ_FFUART,
  181. .end = IRQ_FFUART,
  182. .flags = IORESOURCE_IRQ,
  183. }
  184. };
  185. struct platform_device pxa_device_ffuart = {
  186. .name = "pxa2xx-uart",
  187. .id = 0,
  188. .resource = pxa_resource_ffuart,
  189. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  190. };
  191. void __init pxa_set_ffuart_info(void *info)
  192. {
  193. pxa_register_device(&pxa_device_ffuart, info);
  194. }
  195. static struct resource pxa_resource_btuart[] = {
  196. {
  197. .start = 0x40200000,
  198. .end = 0x40200023,
  199. .flags = IORESOURCE_MEM,
  200. }, {
  201. .start = IRQ_BTUART,
  202. .end = IRQ_BTUART,
  203. .flags = IORESOURCE_IRQ,
  204. }
  205. };
  206. struct platform_device pxa_device_btuart = {
  207. .name = "pxa2xx-uart",
  208. .id = 1,
  209. .resource = pxa_resource_btuart,
  210. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  211. };
  212. void __init pxa_set_btuart_info(void *info)
  213. {
  214. pxa_register_device(&pxa_device_btuart, info);
  215. }
  216. static struct resource pxa_resource_stuart[] = {
  217. {
  218. .start = 0x40700000,
  219. .end = 0x40700023,
  220. .flags = IORESOURCE_MEM,
  221. }, {
  222. .start = IRQ_STUART,
  223. .end = IRQ_STUART,
  224. .flags = IORESOURCE_IRQ,
  225. }
  226. };
  227. struct platform_device pxa_device_stuart = {
  228. .name = "pxa2xx-uart",
  229. .id = 2,
  230. .resource = pxa_resource_stuart,
  231. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  232. };
  233. void __init pxa_set_stuart_info(void *info)
  234. {
  235. pxa_register_device(&pxa_device_stuart, info);
  236. }
  237. static struct resource pxa_resource_hwuart[] = {
  238. {
  239. .start = 0x41600000,
  240. .end = 0x4160002F,
  241. .flags = IORESOURCE_MEM,
  242. }, {
  243. .start = IRQ_HWUART,
  244. .end = IRQ_HWUART,
  245. .flags = IORESOURCE_IRQ,
  246. }
  247. };
  248. struct platform_device pxa_device_hwuart = {
  249. .name = "pxa2xx-uart",
  250. .id = 3,
  251. .resource = pxa_resource_hwuart,
  252. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  253. };
  254. void __init pxa_set_hwuart_info(void *info)
  255. {
  256. if (cpu_is_pxa255())
  257. pxa_register_device(&pxa_device_hwuart, info);
  258. else
  259. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  260. }
  261. static struct resource pxai2c_resources[] = {
  262. {
  263. .start = 0x40301680,
  264. .end = 0x403016a3,
  265. .flags = IORESOURCE_MEM,
  266. }, {
  267. .start = IRQ_I2C,
  268. .end = IRQ_I2C,
  269. .flags = IORESOURCE_IRQ,
  270. },
  271. };
  272. struct platform_device pxa_device_i2c = {
  273. .name = "pxa2xx-i2c",
  274. .id = 0,
  275. .resource = pxai2c_resources,
  276. .num_resources = ARRAY_SIZE(pxai2c_resources),
  277. };
  278. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  279. {
  280. pxa_register_device(&pxa_device_i2c, info);
  281. }
  282. #ifdef CONFIG_PXA27x
  283. static struct resource pxa27x_resources_i2c_power[] = {
  284. {
  285. .start = 0x40f00180,
  286. .end = 0x40f001a3,
  287. .flags = IORESOURCE_MEM,
  288. }, {
  289. .start = IRQ_PWRI2C,
  290. .end = IRQ_PWRI2C,
  291. .flags = IORESOURCE_IRQ,
  292. },
  293. };
  294. struct platform_device pxa27x_device_i2c_power = {
  295. .name = "pxa2xx-i2c",
  296. .id = 1,
  297. .resource = pxa27x_resources_i2c_power,
  298. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  299. };
  300. #endif
  301. static struct resource pxai2s_resources[] = {
  302. {
  303. .start = 0x40400000,
  304. .end = 0x40400083,
  305. .flags = IORESOURCE_MEM,
  306. }, {
  307. .start = IRQ_I2S,
  308. .end = IRQ_I2S,
  309. .flags = IORESOURCE_IRQ,
  310. },
  311. };
  312. struct platform_device pxa_device_i2s = {
  313. .name = "pxa2xx-i2s",
  314. .id = -1,
  315. .resource = pxai2s_resources,
  316. .num_resources = ARRAY_SIZE(pxai2s_resources),
  317. };
  318. struct platform_device pxa_device_asoc_ssp1 = {
  319. .name = "pxa-ssp-dai",
  320. .id = 0,
  321. };
  322. struct platform_device pxa_device_asoc_ssp2= {
  323. .name = "pxa-ssp-dai",
  324. .id = 1,
  325. };
  326. struct platform_device pxa_device_asoc_ssp3 = {
  327. .name = "pxa-ssp-dai",
  328. .id = 2,
  329. };
  330. struct platform_device pxa_device_asoc_ssp4 = {
  331. .name = "pxa-ssp-dai",
  332. .id = 3,
  333. };
  334. struct platform_device pxa_device_asoc_platform = {
  335. .name = "pxa-pcm-audio",
  336. .id = -1,
  337. };
  338. static u64 pxaficp_dmamask = ~(u32)0;
  339. struct platform_device pxa_device_ficp = {
  340. .name = "pxa2xx-ir",
  341. .id = -1,
  342. .dev = {
  343. .dma_mask = &pxaficp_dmamask,
  344. .coherent_dma_mask = 0xffffffff,
  345. },
  346. };
  347. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  348. {
  349. pxa_register_device(&pxa_device_ficp, info);
  350. }
  351. static struct resource pxa_rtc_resources[] = {
  352. [0] = {
  353. .start = 0x40900000,
  354. .end = 0x40900000 + 0x3b,
  355. .flags = IORESOURCE_MEM,
  356. },
  357. [1] = {
  358. .start = IRQ_RTC1Hz,
  359. .end = IRQ_RTC1Hz,
  360. .flags = IORESOURCE_IRQ,
  361. },
  362. [2] = {
  363. .start = IRQ_RTCAlrm,
  364. .end = IRQ_RTCAlrm,
  365. .flags = IORESOURCE_IRQ,
  366. },
  367. };
  368. struct platform_device sa1100_device_rtc = {
  369. .name = "sa1100-rtc",
  370. .id = -1,
  371. };
  372. struct platform_device pxa_device_rtc = {
  373. .name = "pxa-rtc",
  374. .id = -1,
  375. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  376. .resource = pxa_rtc_resources,
  377. };
  378. static struct resource pxa_ac97_resources[] = {
  379. [0] = {
  380. .start = 0x40500000,
  381. .end = 0x40500000 + 0xfff,
  382. .flags = IORESOURCE_MEM,
  383. },
  384. [1] = {
  385. .start = IRQ_AC97,
  386. .end = IRQ_AC97,
  387. .flags = IORESOURCE_IRQ,
  388. },
  389. };
  390. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  391. struct platform_device pxa_device_ac97 = {
  392. .name = "pxa2xx-ac97",
  393. .id = -1,
  394. .dev = {
  395. .dma_mask = &pxa_ac97_dmamask,
  396. .coherent_dma_mask = 0xffffffff,
  397. },
  398. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  399. .resource = pxa_ac97_resources,
  400. };
  401. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  402. {
  403. pxa_register_device(&pxa_device_ac97, ops);
  404. }
  405. #ifdef CONFIG_PXA25x
  406. static struct resource pxa25x_resource_pwm0[] = {
  407. [0] = {
  408. .start = 0x40b00000,
  409. .end = 0x40b0000f,
  410. .flags = IORESOURCE_MEM,
  411. },
  412. };
  413. struct platform_device pxa25x_device_pwm0 = {
  414. .name = "pxa25x-pwm",
  415. .id = 0,
  416. .resource = pxa25x_resource_pwm0,
  417. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  418. };
  419. static struct resource pxa25x_resource_pwm1[] = {
  420. [0] = {
  421. .start = 0x40c00000,
  422. .end = 0x40c0000f,
  423. .flags = IORESOURCE_MEM,
  424. },
  425. };
  426. struct platform_device pxa25x_device_pwm1 = {
  427. .name = "pxa25x-pwm",
  428. .id = 1,
  429. .resource = pxa25x_resource_pwm1,
  430. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  431. };
  432. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  433. static struct resource pxa25x_resource_ssp[] = {
  434. [0] = {
  435. .start = 0x41000000,
  436. .end = 0x4100001f,
  437. .flags = IORESOURCE_MEM,
  438. },
  439. [1] = {
  440. .start = IRQ_SSP,
  441. .end = IRQ_SSP,
  442. .flags = IORESOURCE_IRQ,
  443. },
  444. [2] = {
  445. /* DRCMR for RX */
  446. .start = 13,
  447. .end = 13,
  448. .flags = IORESOURCE_DMA,
  449. },
  450. [3] = {
  451. /* DRCMR for TX */
  452. .start = 14,
  453. .end = 14,
  454. .flags = IORESOURCE_DMA,
  455. },
  456. };
  457. struct platform_device pxa25x_device_ssp = {
  458. .name = "pxa25x-ssp",
  459. .id = 0,
  460. .dev = {
  461. .dma_mask = &pxa25x_ssp_dma_mask,
  462. .coherent_dma_mask = DMA_BIT_MASK(32),
  463. },
  464. .resource = pxa25x_resource_ssp,
  465. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  466. };
  467. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  468. static struct resource pxa25x_resource_nssp[] = {
  469. [0] = {
  470. .start = 0x41400000,
  471. .end = 0x4140002f,
  472. .flags = IORESOURCE_MEM,
  473. },
  474. [1] = {
  475. .start = IRQ_NSSP,
  476. .end = IRQ_NSSP,
  477. .flags = IORESOURCE_IRQ,
  478. },
  479. [2] = {
  480. /* DRCMR for RX */
  481. .start = 15,
  482. .end = 15,
  483. .flags = IORESOURCE_DMA,
  484. },
  485. [3] = {
  486. /* DRCMR for TX */
  487. .start = 16,
  488. .end = 16,
  489. .flags = IORESOURCE_DMA,
  490. },
  491. };
  492. struct platform_device pxa25x_device_nssp = {
  493. .name = "pxa25x-nssp",
  494. .id = 1,
  495. .dev = {
  496. .dma_mask = &pxa25x_nssp_dma_mask,
  497. .coherent_dma_mask = DMA_BIT_MASK(32),
  498. },
  499. .resource = pxa25x_resource_nssp,
  500. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  501. };
  502. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  503. static struct resource pxa25x_resource_assp[] = {
  504. [0] = {
  505. .start = 0x41500000,
  506. .end = 0x4150002f,
  507. .flags = IORESOURCE_MEM,
  508. },
  509. [1] = {
  510. .start = IRQ_ASSP,
  511. .end = IRQ_ASSP,
  512. .flags = IORESOURCE_IRQ,
  513. },
  514. [2] = {
  515. /* DRCMR for RX */
  516. .start = 23,
  517. .end = 23,
  518. .flags = IORESOURCE_DMA,
  519. },
  520. [3] = {
  521. /* DRCMR for TX */
  522. .start = 24,
  523. .end = 24,
  524. .flags = IORESOURCE_DMA,
  525. },
  526. };
  527. struct platform_device pxa25x_device_assp = {
  528. /* ASSP is basically equivalent to NSSP */
  529. .name = "pxa25x-nssp",
  530. .id = 2,
  531. .dev = {
  532. .dma_mask = &pxa25x_assp_dma_mask,
  533. .coherent_dma_mask = DMA_BIT_MASK(32),
  534. },
  535. .resource = pxa25x_resource_assp,
  536. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  537. };
  538. #endif /* CONFIG_PXA25x */
  539. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  540. static struct resource pxa27x_resource_camera[] = {
  541. [0] = {
  542. .start = 0x50000000,
  543. .end = 0x50000fff,
  544. .flags = IORESOURCE_MEM,
  545. },
  546. [1] = {
  547. .start = IRQ_CAMERA,
  548. .end = IRQ_CAMERA,
  549. .flags = IORESOURCE_IRQ,
  550. },
  551. };
  552. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  553. static struct platform_device pxa27x_device_camera = {
  554. .name = "pxa27x-camera",
  555. .id = 0, /* This is used to put cameras on this interface */
  556. .dev = {
  557. .dma_mask = &pxa27x_dma_mask_camera,
  558. .coherent_dma_mask = 0xffffffff,
  559. },
  560. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  561. .resource = pxa27x_resource_camera,
  562. };
  563. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  564. {
  565. pxa_register_device(&pxa27x_device_camera, info);
  566. }
  567. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  568. static struct resource pxa27x_resource_ohci[] = {
  569. [0] = {
  570. .start = 0x4C000000,
  571. .end = 0x4C00ff6f,
  572. .flags = IORESOURCE_MEM,
  573. },
  574. [1] = {
  575. .start = IRQ_USBH1,
  576. .end = IRQ_USBH1,
  577. .flags = IORESOURCE_IRQ,
  578. },
  579. };
  580. struct platform_device pxa27x_device_ohci = {
  581. .name = "pxa27x-ohci",
  582. .id = -1,
  583. .dev = {
  584. .dma_mask = &pxa27x_ohci_dma_mask,
  585. .coherent_dma_mask = DMA_BIT_MASK(32),
  586. },
  587. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  588. .resource = pxa27x_resource_ohci,
  589. };
  590. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  591. {
  592. pxa_register_device(&pxa27x_device_ohci, info);
  593. }
  594. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  595. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  596. static struct resource pxa27x_resource_keypad[] = {
  597. [0] = {
  598. .start = 0x41500000,
  599. .end = 0x4150004c,
  600. .flags = IORESOURCE_MEM,
  601. },
  602. [1] = {
  603. .start = IRQ_KEYPAD,
  604. .end = IRQ_KEYPAD,
  605. .flags = IORESOURCE_IRQ,
  606. },
  607. };
  608. struct platform_device pxa27x_device_keypad = {
  609. .name = "pxa27x-keypad",
  610. .id = -1,
  611. .resource = pxa27x_resource_keypad,
  612. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  613. };
  614. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  615. {
  616. pxa_register_device(&pxa27x_device_keypad, info);
  617. }
  618. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  619. static struct resource pxa27x_resource_ssp1[] = {
  620. [0] = {
  621. .start = 0x41000000,
  622. .end = 0x4100003f,
  623. .flags = IORESOURCE_MEM,
  624. },
  625. [1] = {
  626. .start = IRQ_SSP,
  627. .end = IRQ_SSP,
  628. .flags = IORESOURCE_IRQ,
  629. },
  630. [2] = {
  631. /* DRCMR for RX */
  632. .start = 13,
  633. .end = 13,
  634. .flags = IORESOURCE_DMA,
  635. },
  636. [3] = {
  637. /* DRCMR for TX */
  638. .start = 14,
  639. .end = 14,
  640. .flags = IORESOURCE_DMA,
  641. },
  642. };
  643. struct platform_device pxa27x_device_ssp1 = {
  644. .name = "pxa27x-ssp",
  645. .id = 0,
  646. .dev = {
  647. .dma_mask = &pxa27x_ssp1_dma_mask,
  648. .coherent_dma_mask = DMA_BIT_MASK(32),
  649. },
  650. .resource = pxa27x_resource_ssp1,
  651. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  652. };
  653. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  654. static struct resource pxa27x_resource_ssp2[] = {
  655. [0] = {
  656. .start = 0x41700000,
  657. .end = 0x4170003f,
  658. .flags = IORESOURCE_MEM,
  659. },
  660. [1] = {
  661. .start = IRQ_SSP2,
  662. .end = IRQ_SSP2,
  663. .flags = IORESOURCE_IRQ,
  664. },
  665. [2] = {
  666. /* DRCMR for RX */
  667. .start = 15,
  668. .end = 15,
  669. .flags = IORESOURCE_DMA,
  670. },
  671. [3] = {
  672. /* DRCMR for TX */
  673. .start = 16,
  674. .end = 16,
  675. .flags = IORESOURCE_DMA,
  676. },
  677. };
  678. struct platform_device pxa27x_device_ssp2 = {
  679. .name = "pxa27x-ssp",
  680. .id = 1,
  681. .dev = {
  682. .dma_mask = &pxa27x_ssp2_dma_mask,
  683. .coherent_dma_mask = DMA_BIT_MASK(32),
  684. },
  685. .resource = pxa27x_resource_ssp2,
  686. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  687. };
  688. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  689. static struct resource pxa27x_resource_ssp3[] = {
  690. [0] = {
  691. .start = 0x41900000,
  692. .end = 0x4190003f,
  693. .flags = IORESOURCE_MEM,
  694. },
  695. [1] = {
  696. .start = IRQ_SSP3,
  697. .end = IRQ_SSP3,
  698. .flags = IORESOURCE_IRQ,
  699. },
  700. [2] = {
  701. /* DRCMR for RX */
  702. .start = 66,
  703. .end = 66,
  704. .flags = IORESOURCE_DMA,
  705. },
  706. [3] = {
  707. /* DRCMR for TX */
  708. .start = 67,
  709. .end = 67,
  710. .flags = IORESOURCE_DMA,
  711. },
  712. };
  713. struct platform_device pxa27x_device_ssp3 = {
  714. .name = "pxa27x-ssp",
  715. .id = 2,
  716. .dev = {
  717. .dma_mask = &pxa27x_ssp3_dma_mask,
  718. .coherent_dma_mask = DMA_BIT_MASK(32),
  719. },
  720. .resource = pxa27x_resource_ssp3,
  721. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  722. };
  723. static struct resource pxa27x_resource_pwm0[] = {
  724. [0] = {
  725. .start = 0x40b00000,
  726. .end = 0x40b0001f,
  727. .flags = IORESOURCE_MEM,
  728. },
  729. };
  730. struct platform_device pxa27x_device_pwm0 = {
  731. .name = "pxa27x-pwm",
  732. .id = 0,
  733. .resource = pxa27x_resource_pwm0,
  734. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  735. };
  736. static struct resource pxa27x_resource_pwm1[] = {
  737. [0] = {
  738. .start = 0x40c00000,
  739. .end = 0x40c0001f,
  740. .flags = IORESOURCE_MEM,
  741. },
  742. };
  743. struct platform_device pxa27x_device_pwm1 = {
  744. .name = "pxa27x-pwm",
  745. .id = 1,
  746. .resource = pxa27x_resource_pwm1,
  747. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  748. };
  749. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
  750. #ifdef CONFIG_PXA3xx
  751. static struct resource pxa3xx_resources_mci2[] = {
  752. [0] = {
  753. .start = 0x42000000,
  754. .end = 0x42000fff,
  755. .flags = IORESOURCE_MEM,
  756. },
  757. [1] = {
  758. .start = IRQ_MMC2,
  759. .end = IRQ_MMC2,
  760. .flags = IORESOURCE_IRQ,
  761. },
  762. [2] = {
  763. .start = 93,
  764. .end = 93,
  765. .flags = IORESOURCE_DMA,
  766. },
  767. [3] = {
  768. .start = 94,
  769. .end = 94,
  770. .flags = IORESOURCE_DMA,
  771. },
  772. };
  773. struct platform_device pxa3xx_device_mci2 = {
  774. .name = "pxa2xx-mci",
  775. .id = 1,
  776. .dev = {
  777. .dma_mask = &pxamci_dmamask,
  778. .coherent_dma_mask = 0xffffffff,
  779. },
  780. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  781. .resource = pxa3xx_resources_mci2,
  782. };
  783. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  784. {
  785. pxa_register_device(&pxa3xx_device_mci2, info);
  786. }
  787. static struct resource pxa3xx_resources_mci3[] = {
  788. [0] = {
  789. .start = 0x42500000,
  790. .end = 0x42500fff,
  791. .flags = IORESOURCE_MEM,
  792. },
  793. [1] = {
  794. .start = IRQ_MMC3,
  795. .end = IRQ_MMC3,
  796. .flags = IORESOURCE_IRQ,
  797. },
  798. [2] = {
  799. .start = 100,
  800. .end = 100,
  801. .flags = IORESOURCE_DMA,
  802. },
  803. [3] = {
  804. .start = 101,
  805. .end = 101,
  806. .flags = IORESOURCE_DMA,
  807. },
  808. };
  809. struct platform_device pxa3xx_device_mci3 = {
  810. .name = "pxa2xx-mci",
  811. .id = 2,
  812. .dev = {
  813. .dma_mask = &pxamci_dmamask,
  814. .coherent_dma_mask = 0xffffffff,
  815. },
  816. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  817. .resource = pxa3xx_resources_mci3,
  818. };
  819. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  820. {
  821. pxa_register_device(&pxa3xx_device_mci3, info);
  822. }
  823. static struct resource pxa3xx_resources_gcu[] = {
  824. {
  825. .start = 0x54000000,
  826. .end = 0x54000fff,
  827. .flags = IORESOURCE_MEM,
  828. },
  829. {
  830. .start = IRQ_GCU,
  831. .end = IRQ_GCU,
  832. .flags = IORESOURCE_IRQ,
  833. },
  834. };
  835. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  836. struct platform_device pxa3xx_device_gcu = {
  837. .name = "pxa3xx-gcu",
  838. .id = -1,
  839. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  840. .resource = pxa3xx_resources_gcu,
  841. .dev = {
  842. .dma_mask = &pxa3xx_gcu_dmamask,
  843. .coherent_dma_mask = 0xffffffff,
  844. },
  845. };
  846. #endif /* CONFIG_PXA3xx */
  847. #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  848. static struct resource pxa3xx_resources_i2c_power[] = {
  849. {
  850. .start = 0x40f500c0,
  851. .end = 0x40f500d3,
  852. .flags = IORESOURCE_MEM,
  853. }, {
  854. .start = IRQ_PWRI2C,
  855. .end = IRQ_PWRI2C,
  856. .flags = IORESOURCE_IRQ,
  857. },
  858. };
  859. struct platform_device pxa3xx_device_i2c_power = {
  860. .name = "pxa3xx-pwri2c",
  861. .id = 1,
  862. .resource = pxa3xx_resources_i2c_power,
  863. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  864. };
  865. static struct resource pxa3xx_resources_nand[] = {
  866. [0] = {
  867. .start = 0x43100000,
  868. .end = 0x43100053,
  869. .flags = IORESOURCE_MEM,
  870. },
  871. [1] = {
  872. .start = IRQ_NAND,
  873. .end = IRQ_NAND,
  874. .flags = IORESOURCE_IRQ,
  875. },
  876. [2] = {
  877. /* DRCMR for Data DMA */
  878. .start = 97,
  879. .end = 97,
  880. .flags = IORESOURCE_DMA,
  881. },
  882. [3] = {
  883. /* DRCMR for Command DMA */
  884. .start = 99,
  885. .end = 99,
  886. .flags = IORESOURCE_DMA,
  887. },
  888. };
  889. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  890. struct platform_device pxa3xx_device_nand = {
  891. .name = "pxa3xx-nand",
  892. .id = -1,
  893. .dev = {
  894. .dma_mask = &pxa3xx_nand_dma_mask,
  895. .coherent_dma_mask = DMA_BIT_MASK(32),
  896. },
  897. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  898. .resource = pxa3xx_resources_nand,
  899. };
  900. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  901. {
  902. pxa_register_device(&pxa3xx_device_nand, info);
  903. }
  904. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  905. static struct resource pxa3xx_resource_ssp4[] = {
  906. [0] = {
  907. .start = 0x41a00000,
  908. .end = 0x41a0003f,
  909. .flags = IORESOURCE_MEM,
  910. },
  911. [1] = {
  912. .start = IRQ_SSP4,
  913. .end = IRQ_SSP4,
  914. .flags = IORESOURCE_IRQ,
  915. },
  916. [2] = {
  917. /* DRCMR for RX */
  918. .start = 2,
  919. .end = 2,
  920. .flags = IORESOURCE_DMA,
  921. },
  922. [3] = {
  923. /* DRCMR for TX */
  924. .start = 3,
  925. .end = 3,
  926. .flags = IORESOURCE_DMA,
  927. },
  928. };
  929. struct platform_device pxa3xx_device_ssp4 = {
  930. /* PXA3xx SSP is basically equivalent to PXA27x */
  931. .name = "pxa27x-ssp",
  932. .id = 3,
  933. .dev = {
  934. .dma_mask = &pxa3xx_ssp4_dma_mask,
  935. .coherent_dma_mask = DMA_BIT_MASK(32),
  936. },
  937. .resource = pxa3xx_resource_ssp4,
  938. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  939. };
  940. #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
  941. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  942. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  943. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  944. {
  945. struct platform_device *pd;
  946. pd = platform_device_alloc("pxa2xx-spi", id);
  947. if (pd == NULL) {
  948. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  949. id);
  950. return;
  951. }
  952. pd->dev.platform_data = info;
  953. platform_device_add(pd);
  954. }