clockdomains44xx_data.c 18 KB

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  1. /*
  2. * OMAP4 Clock domains framework
  3. *
  4. * Copyright (C) 2009 Texas Instruments, Inc.
  5. * Copyright (C) 2009 Nokia Corporation
  6. *
  7. * Abhijit Pagare (abhijitpagare@ti.com)
  8. * Benoit Cousson (b-cousson@ti.com)
  9. *
  10. * This file is automatically generated from the OMAP hardware databases.
  11. * We respectfully ask that any modifications to this file be coordinated
  12. * with the public linux-omap@vger.kernel.org mailing list and the
  13. * authors above to ensure that the autogeneration scripts are kept
  14. * up-to-date with the file contents.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/io.h>
  22. #include "clockdomain.h"
  23. #include "cm1_44xx.h"
  24. #include "cm2_44xx.h"
  25. #include "cm-regbits-44xx.h"
  26. #include "prm44xx.h"
  27. #include "prcm44xx.h"
  28. #include "prcm_mpu44xx.h"
  29. /* Static Dependencies for OMAP4 Clock Domains */
  30. static struct clkdm_dep ducati_wkup_sleep_deps[] = {
  31. {
  32. .clkdm_name = "abe_clkdm",
  33. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  34. },
  35. {
  36. .clkdm_name = "ivahd_clkdm",
  37. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  38. },
  39. {
  40. .clkdm_name = "l3_1_clkdm",
  41. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  42. },
  43. {
  44. .clkdm_name = "l3_2_clkdm",
  45. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  46. },
  47. {
  48. .clkdm_name = "l3_dss_clkdm",
  49. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  50. },
  51. {
  52. .clkdm_name = "l3_emif_clkdm",
  53. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  54. },
  55. {
  56. .clkdm_name = "l3_gfx_clkdm",
  57. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  58. },
  59. {
  60. .clkdm_name = "l3_init_clkdm",
  61. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  62. },
  63. {
  64. .clkdm_name = "l4_cfg_clkdm",
  65. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  66. },
  67. {
  68. .clkdm_name = "l4_per_clkdm",
  69. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  70. },
  71. {
  72. .clkdm_name = "l4_secure_clkdm",
  73. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  74. },
  75. {
  76. .clkdm_name = "l4_wkup_clkdm",
  77. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  78. },
  79. {
  80. .clkdm_name = "tesla_clkdm",
  81. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  82. },
  83. { NULL },
  84. };
  85. static struct clkdm_dep iss_wkup_sleep_deps[] = {
  86. {
  87. .clkdm_name = "ivahd_clkdm",
  88. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  89. },
  90. {
  91. .clkdm_name = "l3_1_clkdm",
  92. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  93. },
  94. {
  95. .clkdm_name = "l3_emif_clkdm",
  96. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  97. },
  98. { NULL },
  99. };
  100. static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
  101. {
  102. .clkdm_name = "l3_1_clkdm",
  103. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  104. },
  105. {
  106. .clkdm_name = "l3_emif_clkdm",
  107. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  108. },
  109. { NULL },
  110. };
  111. static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
  112. {
  113. .clkdm_name = "abe_clkdm",
  114. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  115. },
  116. {
  117. .clkdm_name = "ivahd_clkdm",
  118. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  119. },
  120. {
  121. .clkdm_name = "l3_1_clkdm",
  122. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  123. },
  124. {
  125. .clkdm_name = "l3_2_clkdm",
  126. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  127. },
  128. {
  129. .clkdm_name = "l3_emif_clkdm",
  130. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  131. },
  132. {
  133. .clkdm_name = "l3_init_clkdm",
  134. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  135. },
  136. {
  137. .clkdm_name = "l4_cfg_clkdm",
  138. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  139. },
  140. {
  141. .clkdm_name = "l4_per_clkdm",
  142. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  143. },
  144. { NULL },
  145. };
  146. static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
  147. {
  148. .clkdm_name = "abe_clkdm",
  149. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  150. },
  151. {
  152. .clkdm_name = "ducati_clkdm",
  153. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  154. },
  155. {
  156. .clkdm_name = "ivahd_clkdm",
  157. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  158. },
  159. {
  160. .clkdm_name = "l3_1_clkdm",
  161. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  162. },
  163. {
  164. .clkdm_name = "l3_dss_clkdm",
  165. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  166. },
  167. {
  168. .clkdm_name = "l3_emif_clkdm",
  169. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  170. },
  171. {
  172. .clkdm_name = "l3_init_clkdm",
  173. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  174. },
  175. {
  176. .clkdm_name = "l4_cfg_clkdm",
  177. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  178. },
  179. {
  180. .clkdm_name = "l4_per_clkdm",
  181. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  182. },
  183. {
  184. .clkdm_name = "l4_secure_clkdm",
  185. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  186. },
  187. {
  188. .clkdm_name = "l4_wkup_clkdm",
  189. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  190. },
  191. { NULL },
  192. };
  193. static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
  194. {
  195. .clkdm_name = "ivahd_clkdm",
  196. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  197. },
  198. {
  199. .clkdm_name = "l3_2_clkdm",
  200. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  201. },
  202. {
  203. .clkdm_name = "l3_emif_clkdm",
  204. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  205. },
  206. { NULL },
  207. };
  208. static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
  209. {
  210. .clkdm_name = "ivahd_clkdm",
  211. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  212. },
  213. {
  214. .clkdm_name = "l3_1_clkdm",
  215. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  216. },
  217. {
  218. .clkdm_name = "l3_emif_clkdm",
  219. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  220. },
  221. { NULL },
  222. };
  223. static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
  224. {
  225. .clkdm_name = "abe_clkdm",
  226. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  227. },
  228. {
  229. .clkdm_name = "ivahd_clkdm",
  230. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  231. },
  232. {
  233. .clkdm_name = "l3_emif_clkdm",
  234. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  235. },
  236. {
  237. .clkdm_name = "l4_cfg_clkdm",
  238. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  239. },
  240. {
  241. .clkdm_name = "l4_per_clkdm",
  242. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  243. },
  244. {
  245. .clkdm_name = "l4_secure_clkdm",
  246. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  247. },
  248. {
  249. .clkdm_name = "l4_wkup_clkdm",
  250. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  251. },
  252. { NULL },
  253. };
  254. static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
  255. {
  256. .clkdm_name = "l3_1_clkdm",
  257. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  258. },
  259. {
  260. .clkdm_name = "l3_emif_clkdm",
  261. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  262. },
  263. {
  264. .clkdm_name = "l4_per_clkdm",
  265. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  266. },
  267. { NULL },
  268. };
  269. static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
  270. {
  271. .clkdm_name = "abe_clkdm",
  272. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  273. },
  274. {
  275. .clkdm_name = "ducati_clkdm",
  276. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  277. },
  278. {
  279. .clkdm_name = "ivahd_clkdm",
  280. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  281. },
  282. {
  283. .clkdm_name = "l3_1_clkdm",
  284. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  285. },
  286. {
  287. .clkdm_name = "l3_2_clkdm",
  288. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  289. },
  290. {
  291. .clkdm_name = "l3_dss_clkdm",
  292. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  293. },
  294. {
  295. .clkdm_name = "l3_emif_clkdm",
  296. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  297. },
  298. {
  299. .clkdm_name = "l3_gfx_clkdm",
  300. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  301. },
  302. {
  303. .clkdm_name = "l3_init_clkdm",
  304. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  305. },
  306. {
  307. .clkdm_name = "l4_cfg_clkdm",
  308. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  309. },
  310. {
  311. .clkdm_name = "l4_per_clkdm",
  312. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  313. },
  314. {
  315. .clkdm_name = "l4_secure_clkdm",
  316. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  317. },
  318. {
  319. .clkdm_name = "l4_wkup_clkdm",
  320. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  321. },
  322. {
  323. .clkdm_name = "tesla_clkdm",
  324. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  325. },
  326. { NULL },
  327. };
  328. static struct clkdm_dep tesla_wkup_sleep_deps[] = {
  329. {
  330. .clkdm_name = "abe_clkdm",
  331. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  332. },
  333. {
  334. .clkdm_name = "ivahd_clkdm",
  335. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  336. },
  337. {
  338. .clkdm_name = "l3_1_clkdm",
  339. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  340. },
  341. {
  342. .clkdm_name = "l3_2_clkdm",
  343. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  344. },
  345. {
  346. .clkdm_name = "l3_emif_clkdm",
  347. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  348. },
  349. {
  350. .clkdm_name = "l3_init_clkdm",
  351. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  352. },
  353. {
  354. .clkdm_name = "l4_cfg_clkdm",
  355. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  356. },
  357. {
  358. .clkdm_name = "l4_per_clkdm",
  359. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  360. },
  361. {
  362. .clkdm_name = "l4_wkup_clkdm",
  363. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
  364. },
  365. { NULL },
  366. };
  367. static struct clockdomain l4_cefuse_44xx_clkdm = {
  368. .name = "l4_cefuse_clkdm",
  369. .pwrdm = { .name = "cefuse_pwrdm" },
  370. .prcm_partition = OMAP4430_CM2_PARTITION,
  371. .cm_inst = OMAP4430_CM2_CEFUSE_INST,
  372. .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
  373. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  374. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  375. };
  376. static struct clockdomain l4_cfg_44xx_clkdm = {
  377. .name = "l4_cfg_clkdm",
  378. .pwrdm = { .name = "core_pwrdm" },
  379. .prcm_partition = OMAP4430_CM2_PARTITION,
  380. .cm_inst = OMAP4430_CM2_CORE_INST,
  381. .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
  382. .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
  383. .flags = CLKDM_CAN_HWSUP,
  384. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  385. };
  386. static struct clockdomain tesla_44xx_clkdm = {
  387. .name = "tesla_clkdm",
  388. .pwrdm = { .name = "tesla_pwrdm" },
  389. .prcm_partition = OMAP4430_CM1_PARTITION,
  390. .cm_inst = OMAP4430_CM1_TESLA_INST,
  391. .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
  392. .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
  393. .wkdep_srcs = tesla_wkup_sleep_deps,
  394. .sleepdep_srcs = tesla_wkup_sleep_deps,
  395. .flags = CLKDM_CAN_HWSUP_SWSUP,
  396. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  397. };
  398. static struct clockdomain l3_gfx_44xx_clkdm = {
  399. .name = "l3_gfx_clkdm",
  400. .pwrdm = { .name = "gfx_pwrdm" },
  401. .prcm_partition = OMAP4430_CM2_PARTITION,
  402. .cm_inst = OMAP4430_CM2_GFX_INST,
  403. .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
  404. .dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
  405. .wkdep_srcs = l3_gfx_wkup_sleep_deps,
  406. .sleepdep_srcs = l3_gfx_wkup_sleep_deps,
  407. .flags = CLKDM_CAN_HWSUP_SWSUP,
  408. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  409. };
  410. static struct clockdomain ivahd_44xx_clkdm = {
  411. .name = "ivahd_clkdm",
  412. .pwrdm = { .name = "ivahd_pwrdm" },
  413. .prcm_partition = OMAP4430_CM2_PARTITION,
  414. .cm_inst = OMAP4430_CM2_IVAHD_INST,
  415. .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
  416. .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
  417. .wkdep_srcs = ivahd_wkup_sleep_deps,
  418. .sleepdep_srcs = ivahd_wkup_sleep_deps,
  419. .flags = CLKDM_CAN_HWSUP_SWSUP,
  420. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  421. };
  422. static struct clockdomain l4_secure_44xx_clkdm = {
  423. .name = "l4_secure_clkdm",
  424. .pwrdm = { .name = "l4per_pwrdm" },
  425. .prcm_partition = OMAP4430_CM2_PARTITION,
  426. .cm_inst = OMAP4430_CM2_L4PER_INST,
  427. .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
  428. .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
  429. .wkdep_srcs = l4_secure_wkup_sleep_deps,
  430. .sleepdep_srcs = l4_secure_wkup_sleep_deps,
  431. .flags = CLKDM_CAN_HWSUP_SWSUP,
  432. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  433. };
  434. static struct clockdomain l4_per_44xx_clkdm = {
  435. .name = "l4_per_clkdm",
  436. .pwrdm = { .name = "l4per_pwrdm" },
  437. .prcm_partition = OMAP4430_CM2_PARTITION,
  438. .cm_inst = OMAP4430_CM2_L4PER_INST,
  439. .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
  440. .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
  441. .flags = CLKDM_CAN_HWSUP_SWSUP,
  442. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  443. };
  444. static struct clockdomain abe_44xx_clkdm = {
  445. .name = "abe_clkdm",
  446. .pwrdm = { .name = "abe_pwrdm" },
  447. .prcm_partition = OMAP4430_CM1_PARTITION,
  448. .cm_inst = OMAP4430_CM1_ABE_INST,
  449. .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
  450. .dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
  451. .flags = CLKDM_CAN_HWSUP_SWSUP,
  452. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  453. };
  454. static struct clockdomain l3_instr_44xx_clkdm = {
  455. .name = "l3_instr_clkdm",
  456. .pwrdm = { .name = "core_pwrdm" },
  457. .prcm_partition = OMAP4430_CM2_PARTITION,
  458. .cm_inst = OMAP4430_CM2_CORE_INST,
  459. .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
  460. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  461. };
  462. static struct clockdomain l3_init_44xx_clkdm = {
  463. .name = "l3_init_clkdm",
  464. .pwrdm = { .name = "l3init_pwrdm" },
  465. .prcm_partition = OMAP4430_CM2_PARTITION,
  466. .cm_inst = OMAP4430_CM2_L3INIT_INST,
  467. .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
  468. .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
  469. .wkdep_srcs = l3_init_wkup_sleep_deps,
  470. .sleepdep_srcs = l3_init_wkup_sleep_deps,
  471. .flags = CLKDM_CAN_HWSUP_SWSUP,
  472. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  473. };
  474. static struct clockdomain mpuss_44xx_clkdm = {
  475. .name = "mpuss_clkdm",
  476. .pwrdm = { .name = "mpu_pwrdm" },
  477. .prcm_partition = OMAP4430_CM1_PARTITION,
  478. .cm_inst = OMAP4430_CM1_MPU_INST,
  479. .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
  480. .wkdep_srcs = mpuss_wkup_sleep_deps,
  481. .sleepdep_srcs = mpuss_wkup_sleep_deps,
  482. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  483. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  484. };
  485. static struct clockdomain mpu0_44xx_clkdm = {
  486. .name = "mpu0_clkdm",
  487. .pwrdm = { .name = "cpu0_pwrdm" },
  488. .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
  489. .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
  490. .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
  491. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  492. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  493. };
  494. static struct clockdomain mpu1_44xx_clkdm = {
  495. .name = "mpu1_clkdm",
  496. .pwrdm = { .name = "cpu1_pwrdm" },
  497. .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
  498. .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
  499. .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
  500. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  501. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  502. };
  503. static struct clockdomain l3_emif_44xx_clkdm = {
  504. .name = "l3_emif_clkdm",
  505. .pwrdm = { .name = "core_pwrdm" },
  506. .prcm_partition = OMAP4430_CM2_PARTITION,
  507. .cm_inst = OMAP4430_CM2_CORE_INST,
  508. .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
  509. .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
  510. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  511. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  512. };
  513. static struct clockdomain l4_ao_44xx_clkdm = {
  514. .name = "l4_ao_clkdm",
  515. .pwrdm = { .name = "always_on_core_pwrdm" },
  516. .prcm_partition = OMAP4430_CM2_PARTITION,
  517. .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
  518. .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
  519. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  520. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  521. };
  522. static struct clockdomain ducati_44xx_clkdm = {
  523. .name = "ducati_clkdm",
  524. .pwrdm = { .name = "core_pwrdm" },
  525. .prcm_partition = OMAP4430_CM2_PARTITION,
  526. .cm_inst = OMAP4430_CM2_CORE_INST,
  527. .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
  528. .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
  529. .wkdep_srcs = ducati_wkup_sleep_deps,
  530. .sleepdep_srcs = ducati_wkup_sleep_deps,
  531. .flags = CLKDM_CAN_HWSUP_SWSUP,
  532. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  533. };
  534. static struct clockdomain l3_2_44xx_clkdm = {
  535. .name = "l3_2_clkdm",
  536. .pwrdm = { .name = "core_pwrdm" },
  537. .prcm_partition = OMAP4430_CM2_PARTITION,
  538. .cm_inst = OMAP4430_CM2_CORE_INST,
  539. .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
  540. .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
  541. .flags = CLKDM_CAN_HWSUP,
  542. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  543. };
  544. static struct clockdomain l3_1_44xx_clkdm = {
  545. .name = "l3_1_clkdm",
  546. .pwrdm = { .name = "core_pwrdm" },
  547. .prcm_partition = OMAP4430_CM2_PARTITION,
  548. .cm_inst = OMAP4430_CM2_CORE_INST,
  549. .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
  550. .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
  551. .flags = CLKDM_CAN_HWSUP,
  552. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  553. };
  554. static struct clockdomain l3_d2d_44xx_clkdm = {
  555. .name = "l3_d2d_clkdm",
  556. .pwrdm = { .name = "core_pwrdm" },
  557. .prcm_partition = OMAP4430_CM2_PARTITION,
  558. .cm_inst = OMAP4430_CM2_CORE_INST,
  559. .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
  560. .wkdep_srcs = l3_d2d_wkup_sleep_deps,
  561. .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
  562. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  563. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  564. };
  565. static struct clockdomain iss_44xx_clkdm = {
  566. .name = "iss_clkdm",
  567. .pwrdm = { .name = "cam_pwrdm" },
  568. .prcm_partition = OMAP4430_CM2_PARTITION,
  569. .cm_inst = OMAP4430_CM2_CAM_INST,
  570. .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
  571. .wkdep_srcs = iss_wkup_sleep_deps,
  572. .sleepdep_srcs = iss_wkup_sleep_deps,
  573. .flags = CLKDM_CAN_HWSUP_SWSUP,
  574. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  575. };
  576. static struct clockdomain l3_dss_44xx_clkdm = {
  577. .name = "l3_dss_clkdm",
  578. .pwrdm = { .name = "dss_pwrdm" },
  579. .prcm_partition = OMAP4430_CM2_PARTITION,
  580. .cm_inst = OMAP4430_CM2_DSS_INST,
  581. .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
  582. .dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
  583. .wkdep_srcs = l3_dss_wkup_sleep_deps,
  584. .sleepdep_srcs = l3_dss_wkup_sleep_deps,
  585. .flags = CLKDM_CAN_HWSUP_SWSUP,
  586. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  587. };
  588. static struct clockdomain l4_wkup_44xx_clkdm = {
  589. .name = "l4_wkup_clkdm",
  590. .pwrdm = { .name = "wkup_pwrdm" },
  591. .prcm_partition = OMAP4430_PRM_PARTITION,
  592. .cm_inst = OMAP4430_PRM_WKUP_CM_INST,
  593. .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
  594. .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
  595. .flags = CLKDM_CAN_HWSUP,
  596. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  597. };
  598. static struct clockdomain emu_sys_44xx_clkdm = {
  599. .name = "emu_sys_clkdm",
  600. .pwrdm = { .name = "emu_pwrdm" },
  601. .prcm_partition = OMAP4430_PRM_PARTITION,
  602. .cm_inst = OMAP4430_PRM_EMU_CM_INST,
  603. .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
  604. .flags = CLKDM_CAN_HWSUP,
  605. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  606. };
  607. static struct clockdomain l3_dma_44xx_clkdm = {
  608. .name = "l3_dma_clkdm",
  609. .pwrdm = { .name = "core_pwrdm" },
  610. .prcm_partition = OMAP4430_CM2_PARTITION,
  611. .cm_inst = OMAP4430_CM2_CORE_INST,
  612. .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
  613. .wkdep_srcs = l3_dma_wkup_sleep_deps,
  614. .sleepdep_srcs = l3_dma_wkup_sleep_deps,
  615. .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  616. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  617. };
  618. static struct clockdomain *clockdomains_omap44xx[] __initdata = {
  619. &l4_cefuse_44xx_clkdm,
  620. &l4_cfg_44xx_clkdm,
  621. &tesla_44xx_clkdm,
  622. &l3_gfx_44xx_clkdm,
  623. &ivahd_44xx_clkdm,
  624. &l4_secure_44xx_clkdm,
  625. &l4_per_44xx_clkdm,
  626. &abe_44xx_clkdm,
  627. &l3_instr_44xx_clkdm,
  628. &l3_init_44xx_clkdm,
  629. &mpuss_44xx_clkdm,
  630. &mpu0_44xx_clkdm,
  631. &mpu1_44xx_clkdm,
  632. &l3_emif_44xx_clkdm,
  633. &l4_ao_44xx_clkdm,
  634. &ducati_44xx_clkdm,
  635. &l3_2_44xx_clkdm,
  636. &l3_1_44xx_clkdm,
  637. &l3_d2d_44xx_clkdm,
  638. &iss_44xx_clkdm,
  639. &l3_dss_44xx_clkdm,
  640. &l4_wkup_44xx_clkdm,
  641. &emu_sys_44xx_clkdm,
  642. &l3_dma_44xx_clkdm,
  643. NULL,
  644. };
  645. void __init omap44xx_clockdomains_init(void)
  646. {
  647. clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
  648. }