pasemi_mac.c 36 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include <asm/irq.h>
  34. #include <asm/firmware.h>
  35. #include <asm/pasemi_dma.h>
  36. #include "pasemi_mac.h"
  37. /* We have our own align, since ppc64 in general has it at 0 because
  38. * of design flaws in some of the server bridge chips. However, for
  39. * PWRficient doing the unaligned copies is more expensive than doing
  40. * unaligned DMA, so make sure the data is aligned instead.
  41. */
  42. #define LOCAL_SKB_ALIGN 2
  43. /* TODO list
  44. *
  45. * - Multicast support
  46. * - Large MTU support
  47. * - SW LRO
  48. * - Multiqueue RX/TX
  49. */
  50. /* Must be a power of two */
  51. #define RX_RING_SIZE 4096
  52. #define TX_RING_SIZE 4096
  53. #define DEFAULT_MSG_ENABLE \
  54. (NETIF_MSG_DRV | \
  55. NETIF_MSG_PROBE | \
  56. NETIF_MSG_LINK | \
  57. NETIF_MSG_TIMER | \
  58. NETIF_MSG_IFDOWN | \
  59. NETIF_MSG_IFUP | \
  60. NETIF_MSG_RX_ERR | \
  61. NETIF_MSG_TX_ERR)
  62. #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
  63. #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
  64. #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
  65. #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
  66. #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
  67. #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
  68. & ((ring)->size - 1))
  69. #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
  70. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  71. MODULE_LICENSE("GPL");
  72. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  73. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  74. static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
  75. module_param(debug, int, 0);
  76. MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
  77. static int translation_enabled(void)
  78. {
  79. #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
  80. return 1;
  81. #else
  82. return firmware_has_feature(FW_FEATURE_LPAR);
  83. #endif
  84. }
  85. static void write_iob_reg(unsigned int reg, unsigned int val)
  86. {
  87. pasemi_write_iob_reg(reg, val);
  88. }
  89. static unsigned int read_mac_reg(struct pasemi_mac *mac, unsigned int reg)
  90. {
  91. return pasemi_read_mac_reg(mac->dma_if, reg);
  92. }
  93. static void write_mac_reg(struct pasemi_mac *mac, unsigned int reg,
  94. unsigned int val)
  95. {
  96. pasemi_write_mac_reg(mac->dma_if, reg, val);
  97. }
  98. static unsigned int read_dma_reg(unsigned int reg)
  99. {
  100. return pasemi_read_dma_reg(reg);
  101. }
  102. static void write_dma_reg(unsigned int reg, unsigned int val)
  103. {
  104. pasemi_write_dma_reg(reg, val);
  105. }
  106. static struct pasemi_mac_rxring *rx_ring(struct pasemi_mac *mac)
  107. {
  108. return mac->rx;
  109. }
  110. static struct pasemi_mac_txring *tx_ring(struct pasemi_mac *mac)
  111. {
  112. return mac->tx;
  113. }
  114. static int mac_to_intf(struct pasemi_mac *mac)
  115. {
  116. struct pci_dev *pdev = mac->pdev;
  117. u32 tmp;
  118. int nintf, off, i, j;
  119. int devfn = pdev->devfn;
  120. tmp = read_dma_reg(PAS_DMA_CAP_IFI);
  121. nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
  122. off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
  123. /* IOFF contains the offset to the registers containing the
  124. * DMA interface-to-MAC-pci-id mappings, and NIN contains number
  125. * of total interfaces. Each register contains 4 devfns.
  126. * Just do a linear search until we find the devfn of the MAC
  127. * we're trying to look up.
  128. */
  129. for (i = 0; i < (nintf+3)/4; i++) {
  130. tmp = read_dma_reg(off+4*i);
  131. for (j = 0; j < 4; j++) {
  132. if (((tmp >> (8*j)) & 0xff) == devfn)
  133. return i*4 + j;
  134. }
  135. }
  136. return -1;
  137. }
  138. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  139. {
  140. struct pci_dev *pdev = mac->pdev;
  141. struct device_node *dn = pci_device_to_OF_node(pdev);
  142. int len;
  143. const u8 *maddr;
  144. u8 addr[6];
  145. if (!dn) {
  146. dev_dbg(&pdev->dev,
  147. "No device node for mac, not configuring\n");
  148. return -ENOENT;
  149. }
  150. maddr = of_get_property(dn, "local-mac-address", &len);
  151. if (maddr && len == 6) {
  152. memcpy(mac->mac_addr, maddr, 6);
  153. return 0;
  154. }
  155. /* Some old versions of firmware mistakenly uses mac-address
  156. * (and as a string) instead of a byte array in local-mac-address.
  157. */
  158. if (maddr == NULL)
  159. maddr = of_get_property(dn, "mac-address", NULL);
  160. if (maddr == NULL) {
  161. dev_warn(&pdev->dev,
  162. "no mac address in device tree, not configuring\n");
  163. return -ENOENT;
  164. }
  165. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  166. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  167. dev_warn(&pdev->dev,
  168. "can't parse mac address, not configuring\n");
  169. return -EINVAL;
  170. }
  171. memcpy(mac->mac_addr, addr, 6);
  172. return 0;
  173. }
  174. static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
  175. struct sk_buff *skb,
  176. dma_addr_t *dmas)
  177. {
  178. int f;
  179. int nfrags = skb_shinfo(skb)->nr_frags;
  180. pci_unmap_single(mac->dma_pdev, dmas[0], skb_headlen(skb),
  181. PCI_DMA_TODEVICE);
  182. for (f = 0; f < nfrags; f++) {
  183. skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
  184. pci_unmap_page(mac->dma_pdev, dmas[f+1], frag->size,
  185. PCI_DMA_TODEVICE);
  186. }
  187. dev_kfree_skb_irq(skb);
  188. /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
  189. * aligned up to a power of 2
  190. */
  191. return (nfrags + 3) & ~1;
  192. }
  193. static int pasemi_mac_setup_rx_resources(struct net_device *dev)
  194. {
  195. struct pasemi_mac_rxring *ring;
  196. struct pasemi_mac *mac = netdev_priv(dev);
  197. int chno;
  198. unsigned int cfg;
  199. ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
  200. offsetof(struct pasemi_mac_rxring, chan));
  201. if (!ring) {
  202. dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
  203. goto out_chan;
  204. }
  205. chno = ring->chan.chno;
  206. spin_lock_init(&ring->lock);
  207. ring->size = RX_RING_SIZE;
  208. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  209. RX_RING_SIZE, GFP_KERNEL);
  210. if (!ring->ring_info)
  211. goto out_ring_info;
  212. /* Allocate descriptors */
  213. if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
  214. goto out_ring_desc;
  215. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  216. RX_RING_SIZE * sizeof(u64),
  217. &ring->buf_dma, GFP_KERNEL);
  218. if (!ring->buffers)
  219. goto out_ring_desc;
  220. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  221. write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
  222. PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
  223. write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
  224. PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
  225. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
  226. cfg = PAS_DMA_RXCHAN_CFG_HBU(1);
  227. if (translation_enabled())
  228. cfg |= PAS_DMA_RXCHAN_CFG_CTR;
  229. write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
  230. write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
  231. PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
  232. write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
  233. PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
  234. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  235. cfg = PAS_DMA_RXINT_CFG_DHL(1) | PAS_DMA_RXINT_CFG_L2 |
  236. PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
  237. PAS_DMA_RXINT_CFG_HEN;
  238. if (translation_enabled())
  239. cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
  240. write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
  241. ring->next_to_fill = 0;
  242. ring->next_to_clean = 0;
  243. ring->mac = mac;
  244. mac->rx = ring;
  245. return 0;
  246. out_ring_desc:
  247. kfree(ring->ring_info);
  248. out_ring_info:
  249. pasemi_dma_free_chan(&ring->chan);
  250. out_chan:
  251. return -ENOMEM;
  252. }
  253. static struct pasemi_mac_txring *
  254. pasemi_mac_setup_tx_resources(struct net_device *dev)
  255. {
  256. struct pasemi_mac *mac = netdev_priv(dev);
  257. u32 val;
  258. struct pasemi_mac_txring *ring;
  259. unsigned int cfg;
  260. int chno;
  261. ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
  262. offsetof(struct pasemi_mac_txring, chan));
  263. if (!ring) {
  264. dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
  265. goto out_chan;
  266. }
  267. chno = ring->chan.chno;
  268. spin_lock_init(&ring->lock);
  269. ring->size = TX_RING_SIZE;
  270. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  271. TX_RING_SIZE, GFP_KERNEL);
  272. if (!ring->ring_info)
  273. goto out_ring_info;
  274. /* Allocate descriptors */
  275. if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
  276. goto out_ring_desc;
  277. write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
  278. PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
  279. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
  280. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
  281. write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
  282. cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
  283. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  284. PAS_DMA_TXCHAN_CFG_UP |
  285. PAS_DMA_TXCHAN_CFG_WT(2);
  286. if (translation_enabled())
  287. cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
  288. write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
  289. ring->next_to_fill = 0;
  290. ring->next_to_clean = 0;
  291. ring->mac = mac;
  292. return ring;
  293. out_ring_desc:
  294. kfree(ring->ring_info);
  295. out_ring_info:
  296. pasemi_dma_free_chan(&ring->chan);
  297. out_chan:
  298. return NULL;
  299. }
  300. static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
  301. {
  302. struct pasemi_mac_txring *txring = tx_ring(mac);
  303. unsigned int i, j;
  304. struct pasemi_mac_buffer *info;
  305. dma_addr_t dmas[MAX_SKB_FRAGS+1];
  306. int freed;
  307. int start, limit;
  308. start = txring->next_to_clean;
  309. limit = txring->next_to_fill;
  310. /* Compensate for when fill has wrapped and clean has not */
  311. if (start > limit)
  312. limit += TX_RING_SIZE;
  313. for (i = start; i < limit; i += freed) {
  314. info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
  315. if (info->dma && info->skb) {
  316. for (j = 0; j <= skb_shinfo(info->skb)->nr_frags; j++)
  317. dmas[j] = txring->ring_info[(i+1+j) &
  318. (TX_RING_SIZE-1)].dma;
  319. freed = pasemi_mac_unmap_tx_skb(mac, info->skb, dmas);
  320. } else
  321. freed = 2;
  322. }
  323. kfree(txring->ring_info);
  324. pasemi_dma_free_chan(&txring->chan);
  325. }
  326. static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
  327. {
  328. struct pasemi_mac_rxring *rx = rx_ring(mac);
  329. unsigned int i;
  330. struct pasemi_mac_buffer *info;
  331. for (i = 0; i < RX_RING_SIZE; i++) {
  332. info = &RX_DESC_INFO(rx, i);
  333. if (info->skb && info->dma) {
  334. pci_unmap_single(mac->dma_pdev,
  335. info->dma,
  336. info->skb->len,
  337. PCI_DMA_FROMDEVICE);
  338. dev_kfree_skb_any(info->skb);
  339. }
  340. info->dma = 0;
  341. info->skb = NULL;
  342. }
  343. for (i = 0; i < RX_RING_SIZE; i++)
  344. RX_DESC(rx, i) = 0;
  345. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  346. rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
  347. kfree(rx_ring(mac)->ring_info);
  348. pasemi_dma_free_chan(&rx_ring(mac)->chan);
  349. mac->rx = NULL;
  350. }
  351. static void pasemi_mac_replenish_rx_ring(struct net_device *dev, int limit)
  352. {
  353. struct pasemi_mac *mac = netdev_priv(dev);
  354. struct pasemi_mac_rxring *rx = rx_ring(mac);
  355. int fill, count;
  356. if (limit <= 0)
  357. return;
  358. fill = rx_ring(mac)->next_to_fill;
  359. for (count = 0; count < limit; count++) {
  360. struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
  361. u64 *buff = &RX_BUFF(rx, fill);
  362. struct sk_buff *skb;
  363. dma_addr_t dma;
  364. /* Entry in use? */
  365. WARN_ON(*buff);
  366. /* skb might still be in there for recycle on short receives */
  367. if (info->skb)
  368. skb = info->skb;
  369. else {
  370. skb = dev_alloc_skb(BUF_SIZE);
  371. skb_reserve(skb, LOCAL_SKB_ALIGN);
  372. }
  373. if (unlikely(!skb))
  374. break;
  375. dma = pci_map_single(mac->dma_pdev, skb->data,
  376. BUF_SIZE - LOCAL_SKB_ALIGN,
  377. PCI_DMA_FROMDEVICE);
  378. if (unlikely(dma_mapping_error(dma))) {
  379. dev_kfree_skb_irq(info->skb);
  380. break;
  381. }
  382. info->skb = skb;
  383. info->dma = dma;
  384. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  385. fill++;
  386. }
  387. wmb();
  388. write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
  389. rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
  390. (RX_RING_SIZE - 1);
  391. }
  392. static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
  393. {
  394. unsigned int reg, pcnt;
  395. /* Re-enable packet count interrupts: finally
  396. * ack the packet count interrupt we got in rx_intr.
  397. */
  398. pcnt = *rx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
  399. reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
  400. write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
  401. }
  402. static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
  403. {
  404. unsigned int reg, pcnt;
  405. /* Re-enable packet count interrupts */
  406. pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
  407. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  408. write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
  409. }
  410. static inline void pasemi_mac_rx_error(struct pasemi_mac *mac, u64 macrx)
  411. {
  412. unsigned int rcmdsta, ccmdsta;
  413. struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
  414. if (!netif_msg_rx_err(mac))
  415. return;
  416. rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  417. ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
  418. printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
  419. macrx, *chan->status);
  420. printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
  421. rcmdsta, ccmdsta);
  422. }
  423. static inline void pasemi_mac_tx_error(struct pasemi_mac *mac, u64 mactx)
  424. {
  425. unsigned int cmdsta;
  426. struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
  427. if (!netif_msg_tx_err(mac))
  428. return;
  429. cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
  430. printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
  431. "tx status 0x%016lx\n", mactx, *chan->status);
  432. printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
  433. }
  434. static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, int limit)
  435. {
  436. struct pasemi_dmachan *chan = &rx->chan;
  437. struct pasemi_mac *mac = rx->mac;
  438. unsigned int n;
  439. int count;
  440. struct pasemi_mac_buffer *info;
  441. struct sk_buff *skb;
  442. unsigned int len;
  443. u64 macrx;
  444. dma_addr_t dma;
  445. int buf_index;
  446. u64 eval;
  447. spin_lock(&rx->lock);
  448. n = rx->next_to_clean;
  449. prefetch(&RX_DESC(rx, n));
  450. for (count = 0; count < limit; count++) {
  451. macrx = RX_DESC(rx, n);
  452. if ((macrx & XCT_MACRX_E) ||
  453. (*chan->status & PAS_STATUS_ERROR))
  454. pasemi_mac_rx_error(mac, macrx);
  455. if (!(macrx & XCT_MACRX_O))
  456. break;
  457. info = NULL;
  458. BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
  459. eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
  460. XCT_RXRES_8B_EVAL_S;
  461. buf_index = eval-1;
  462. dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
  463. info = &RX_DESC_INFO(rx, buf_index);
  464. skb = info->skb;
  465. prefetch(skb);
  466. prefetch(&skb->data_len);
  467. len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  468. pci_unmap_single(mac->dma_pdev, dma, len, PCI_DMA_FROMDEVICE);
  469. if (macrx & XCT_MACRX_CRC) {
  470. /* CRC error flagged */
  471. mac->netdev->stats.rx_errors++;
  472. mac->netdev->stats.rx_crc_errors++;
  473. /* No need to free skb, it'll be reused */
  474. goto next;
  475. }
  476. if (len < 256) {
  477. struct sk_buff *new_skb;
  478. new_skb = netdev_alloc_skb(mac->netdev,
  479. len + LOCAL_SKB_ALIGN);
  480. if (new_skb) {
  481. skb_reserve(new_skb, LOCAL_SKB_ALIGN);
  482. memcpy(new_skb->data, skb->data, len);
  483. /* save the skb in buffer_info as good */
  484. skb = new_skb;
  485. }
  486. /* else just continue with the old one */
  487. } else
  488. info->skb = NULL;
  489. info->dma = 0;
  490. /* Don't include CRC */
  491. skb_put(skb, len-4);
  492. if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
  493. skb->ip_summed = CHECKSUM_UNNECESSARY;
  494. skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
  495. XCT_MACRX_CSUM_S;
  496. } else
  497. skb->ip_summed = CHECKSUM_NONE;
  498. mac->netdev->stats.rx_bytes += len;
  499. mac->netdev->stats.rx_packets++;
  500. skb->protocol = eth_type_trans(skb, mac->netdev);
  501. netif_receive_skb(skb);
  502. next:
  503. RX_DESC(rx, n) = 0;
  504. RX_DESC(rx, n+1) = 0;
  505. /* Need to zero it out since hardware doesn't, since the
  506. * replenish loop uses it to tell when it's done.
  507. */
  508. RX_BUFF(rx, buf_index) = 0;
  509. n += 4;
  510. }
  511. if (n > RX_RING_SIZE) {
  512. /* Errata 5971 workaround: L2 target of headers */
  513. write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
  514. n &= (RX_RING_SIZE-1);
  515. }
  516. rx_ring(mac)->next_to_clean = n;
  517. /* Increase is in number of 16-byte entries, and since each descriptor
  518. * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
  519. * count*2.
  520. */
  521. write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
  522. pasemi_mac_replenish_rx_ring(mac->netdev, count);
  523. spin_unlock(&rx_ring(mac)->lock);
  524. return count;
  525. }
  526. /* Can't make this too large or we blow the kernel stack limits */
  527. #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
  528. static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
  529. {
  530. struct pasemi_dmachan *chan = &txring->chan;
  531. struct pasemi_mac *mac = txring->mac;
  532. int i, j;
  533. unsigned int start, descr_count, buf_count, batch_limit;
  534. unsigned int ring_limit;
  535. unsigned int total_count;
  536. unsigned long flags;
  537. struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
  538. dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
  539. total_count = 0;
  540. batch_limit = TX_CLEAN_BATCHSIZE;
  541. restart:
  542. spin_lock_irqsave(&txring->lock, flags);
  543. start = txring->next_to_clean;
  544. ring_limit = txring->next_to_fill;
  545. /* Compensate for when fill has wrapped but clean has not */
  546. if (start > ring_limit)
  547. ring_limit += TX_RING_SIZE;
  548. buf_count = 0;
  549. descr_count = 0;
  550. for (i = start;
  551. descr_count < batch_limit && i < ring_limit;
  552. i += buf_count) {
  553. u64 mactx = TX_DESC(txring, i);
  554. struct sk_buff *skb;
  555. if ((mactx & XCT_MACTX_E) ||
  556. (*chan->status & PAS_STATUS_ERROR))
  557. pasemi_mac_tx_error(mac, mactx);
  558. if (unlikely(mactx & XCT_MACTX_O))
  559. /* Not yet transmitted */
  560. break;
  561. skb = TX_DESC_INFO(txring, i+1).skb;
  562. skbs[descr_count] = skb;
  563. buf_count = 2 + skb_shinfo(skb)->nr_frags;
  564. for (j = 0; j <= skb_shinfo(skb)->nr_frags; j++)
  565. dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
  566. TX_DESC(txring, i) = 0;
  567. TX_DESC(txring, i+1) = 0;
  568. /* Since we always fill with an even number of entries, make
  569. * sure we skip any unused one at the end as well.
  570. */
  571. if (buf_count & 1)
  572. buf_count++;
  573. descr_count++;
  574. }
  575. txring->next_to_clean = i & (TX_RING_SIZE-1);
  576. spin_unlock_irqrestore(&txring->lock, flags);
  577. netif_wake_queue(mac->netdev);
  578. for (i = 0; i < descr_count; i++)
  579. pasemi_mac_unmap_tx_skb(mac, skbs[i], dmas[i]);
  580. total_count += descr_count;
  581. /* If the batch was full, try to clean more */
  582. if (descr_count == batch_limit)
  583. goto restart;
  584. return total_count;
  585. }
  586. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  587. {
  588. struct pasemi_mac_rxring *rxring = data;
  589. struct pasemi_mac *mac = rxring->mac;
  590. struct net_device *dev = mac->netdev;
  591. struct pasemi_dmachan *chan = &rxring->chan;
  592. unsigned int reg;
  593. if (!(*chan->status & PAS_STATUS_CAUSE_M))
  594. return IRQ_NONE;
  595. /* Don't reset packet count so it won't fire again but clear
  596. * all others.
  597. */
  598. reg = 0;
  599. if (*chan->status & PAS_STATUS_SOFT)
  600. reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
  601. if (*chan->status & PAS_STATUS_ERROR)
  602. reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
  603. if (*chan->status & PAS_STATUS_TIMER)
  604. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  605. netif_rx_schedule(dev, &mac->napi);
  606. write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
  607. return IRQ_HANDLED;
  608. }
  609. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  610. {
  611. struct pasemi_mac_txring *txring = data;
  612. struct pasemi_dmachan *chan = &txring->chan;
  613. unsigned int reg, pcnt;
  614. if (!(*chan->status & PAS_STATUS_CAUSE_M))
  615. return IRQ_NONE;
  616. pasemi_mac_clean_tx(txring);
  617. pcnt = *chan->status & PAS_STATUS_PCNT_M;
  618. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  619. if (*chan->status & PAS_STATUS_SOFT)
  620. reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
  621. if (*chan->status & PAS_STATUS_ERROR)
  622. reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
  623. write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
  624. return IRQ_HANDLED;
  625. }
  626. static void pasemi_adjust_link(struct net_device *dev)
  627. {
  628. struct pasemi_mac *mac = netdev_priv(dev);
  629. int msg;
  630. unsigned int flags;
  631. unsigned int new_flags;
  632. if (!mac->phydev->link) {
  633. /* If no link, MAC speed settings don't matter. Just report
  634. * link down and return.
  635. */
  636. if (mac->link && netif_msg_link(mac))
  637. printk(KERN_INFO "%s: Link is down.\n", dev->name);
  638. netif_carrier_off(dev);
  639. mac->link = 0;
  640. return;
  641. } else
  642. netif_carrier_on(dev);
  643. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  644. new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
  645. PAS_MAC_CFG_PCFG_TSR_M);
  646. if (!mac->phydev->duplex)
  647. new_flags |= PAS_MAC_CFG_PCFG_HD;
  648. switch (mac->phydev->speed) {
  649. case 1000:
  650. new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
  651. PAS_MAC_CFG_PCFG_TSR_1G;
  652. break;
  653. case 100:
  654. new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
  655. PAS_MAC_CFG_PCFG_TSR_100M;
  656. break;
  657. case 10:
  658. new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
  659. PAS_MAC_CFG_PCFG_TSR_10M;
  660. break;
  661. default:
  662. printk("Unsupported speed %d\n", mac->phydev->speed);
  663. }
  664. /* Print on link or speed/duplex change */
  665. msg = mac->link != mac->phydev->link || flags != new_flags;
  666. mac->duplex = mac->phydev->duplex;
  667. mac->speed = mac->phydev->speed;
  668. mac->link = mac->phydev->link;
  669. if (new_flags != flags)
  670. write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
  671. if (msg && netif_msg_link(mac))
  672. printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
  673. dev->name, mac->speed, mac->duplex ? "full" : "half");
  674. }
  675. static int pasemi_mac_phy_init(struct net_device *dev)
  676. {
  677. struct pasemi_mac *mac = netdev_priv(dev);
  678. struct device_node *dn, *phy_dn;
  679. struct phy_device *phydev;
  680. unsigned int phy_id;
  681. const phandle *ph;
  682. const unsigned int *prop;
  683. struct resource r;
  684. int ret;
  685. dn = pci_device_to_OF_node(mac->pdev);
  686. ph = of_get_property(dn, "phy-handle", NULL);
  687. if (!ph)
  688. return -ENODEV;
  689. phy_dn = of_find_node_by_phandle(*ph);
  690. prop = of_get_property(phy_dn, "reg", NULL);
  691. ret = of_address_to_resource(phy_dn->parent, 0, &r);
  692. if (ret)
  693. goto err;
  694. phy_id = *prop;
  695. snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
  696. of_node_put(phy_dn);
  697. mac->link = 0;
  698. mac->speed = 0;
  699. mac->duplex = -1;
  700. phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
  701. if (IS_ERR(phydev)) {
  702. printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
  703. return PTR_ERR(phydev);
  704. }
  705. mac->phydev = phydev;
  706. return 0;
  707. err:
  708. of_node_put(phy_dn);
  709. return -ENODEV;
  710. }
  711. static int pasemi_mac_open(struct net_device *dev)
  712. {
  713. struct pasemi_mac *mac = netdev_priv(dev);
  714. unsigned int flags;
  715. int ret;
  716. /* enable rx section */
  717. write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
  718. /* enable tx section */
  719. write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
  720. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  721. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  722. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  723. write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
  724. /* 0xffffff is max value, about 16ms */
  725. write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
  726. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
  727. ret = pasemi_mac_setup_rx_resources(dev);
  728. if (ret)
  729. goto out_rx_resources;
  730. mac->tx = pasemi_mac_setup_tx_resources(dev);
  731. if (!mac->tx)
  732. goto out_tx_ring;
  733. write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
  734. PAS_IOB_DMA_RXCH_CFG_CNTTH(0));
  735. write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
  736. PAS_IOB_DMA_TXCH_CFG_CNTTH(128));
  737. write_mac_reg(mac, PAS_MAC_IPC_CHNL,
  738. PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
  739. PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
  740. /* enable rx if */
  741. write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  742. PAS_DMA_RXINT_RCMDSTA_EN |
  743. PAS_DMA_RXINT_RCMDSTA_DROPS_M |
  744. PAS_DMA_RXINT_RCMDSTA_BP |
  745. PAS_DMA_RXINT_RCMDSTA_OO |
  746. PAS_DMA_RXINT_RCMDSTA_BT);
  747. /* enable rx channel */
  748. pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
  749. PAS_DMA_RXCHAN_CCMDSTA_OD |
  750. PAS_DMA_RXCHAN_CCMDSTA_FD |
  751. PAS_DMA_RXCHAN_CCMDSTA_DT);
  752. /* enable tx channel */
  753. pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
  754. PAS_DMA_TXCHAN_TCMDSTA_DB |
  755. PAS_DMA_TXCHAN_TCMDSTA_DE |
  756. PAS_DMA_TXCHAN_TCMDSTA_DA);
  757. pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
  758. write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
  759. RX_RING_SIZE>>1);
  760. /* Clear out any residual packet count state from firmware */
  761. pasemi_mac_restart_rx_intr(mac);
  762. pasemi_mac_restart_tx_intr(mac);
  763. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  764. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  765. if (mac->type == MAC_TYPE_GMAC)
  766. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  767. else
  768. flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
  769. /* Enable interface in MAC */
  770. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  771. ret = pasemi_mac_phy_init(dev);
  772. /* Some configs don't have PHYs (XAUI etc), so don't complain about
  773. * failed init due to -ENODEV.
  774. */
  775. if (ret && ret != -ENODEV)
  776. dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
  777. netif_start_queue(dev);
  778. napi_enable(&mac->napi);
  779. snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
  780. dev->name);
  781. ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
  782. mac->tx_irq_name, mac->tx);
  783. if (ret) {
  784. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  785. mac->tx->chan.irq, ret);
  786. goto out_tx_int;
  787. }
  788. snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
  789. dev->name);
  790. ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
  791. mac->rx_irq_name, mac->rx);
  792. if (ret) {
  793. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  794. mac->rx->chan.irq, ret);
  795. goto out_rx_int;
  796. }
  797. if (mac->phydev)
  798. phy_start(mac->phydev);
  799. return 0;
  800. out_rx_int:
  801. free_irq(mac->tx->chan.irq, mac->tx);
  802. out_tx_int:
  803. napi_disable(&mac->napi);
  804. netif_stop_queue(dev);
  805. out_tx_ring:
  806. if (mac->tx)
  807. pasemi_mac_free_tx_resources(mac);
  808. pasemi_mac_free_rx_resources(mac);
  809. out_rx_resources:
  810. return ret;
  811. }
  812. #define MAX_RETRIES 5000
  813. static int pasemi_mac_close(struct net_device *dev)
  814. {
  815. struct pasemi_mac *mac = netdev_priv(dev);
  816. unsigned int sta;
  817. int retries;
  818. int rxch, txch;
  819. rxch = rx_ring(mac)->chan.chno;
  820. txch = tx_ring(mac)->chan.chno;
  821. if (mac->phydev) {
  822. phy_stop(mac->phydev);
  823. phy_disconnect(mac->phydev);
  824. }
  825. netif_stop_queue(dev);
  826. napi_disable(&mac->napi);
  827. sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  828. if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
  829. PAS_DMA_RXINT_RCMDSTA_OO |
  830. PAS_DMA_RXINT_RCMDSTA_BT))
  831. printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
  832. sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
  833. if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
  834. PAS_DMA_RXCHAN_CCMDSTA_OD |
  835. PAS_DMA_RXCHAN_CCMDSTA_FD |
  836. PAS_DMA_RXCHAN_CCMDSTA_DT))
  837. printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
  838. sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
  839. if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
  840. PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
  841. printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
  842. /* Clean out any pending buffers */
  843. pasemi_mac_clean_tx(tx_ring(mac));
  844. pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
  845. /* Disable interface */
  846. write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
  847. PAS_DMA_TXCHAN_TCMDSTA_ST);
  848. write_dma_reg( PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  849. PAS_DMA_RXINT_RCMDSTA_ST);
  850. write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
  851. PAS_DMA_RXCHAN_CCMDSTA_ST);
  852. for (retries = 0; retries < MAX_RETRIES; retries++) {
  853. sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(rxch));
  854. if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
  855. break;
  856. cond_resched();
  857. }
  858. if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  859. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  860. for (retries = 0; retries < MAX_RETRIES; retries++) {
  861. sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
  862. if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
  863. break;
  864. cond_resched();
  865. }
  866. if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  867. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  868. for (retries = 0; retries < MAX_RETRIES; retries++) {
  869. sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  870. if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
  871. break;
  872. cond_resched();
  873. }
  874. if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
  875. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  876. /* Then, disable the channel. This must be done separately from
  877. * stopping, since you can't disable when active.
  878. */
  879. write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
  880. write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
  881. write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  882. free_irq(mac->tx->chan.irq, mac->tx);
  883. free_irq(mac->rx->chan.irq, mac->rx);
  884. /* Free resources */
  885. pasemi_mac_free_rx_resources(mac);
  886. pasemi_mac_free_tx_resources(mac);
  887. return 0;
  888. }
  889. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  890. {
  891. struct pasemi_mac *mac = netdev_priv(dev);
  892. struct pasemi_mac_txring *txring;
  893. u64 dflags, mactx;
  894. dma_addr_t map[MAX_SKB_FRAGS+1];
  895. unsigned int map_size[MAX_SKB_FRAGS+1];
  896. unsigned long flags;
  897. int i, nfrags;
  898. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
  899. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  900. const unsigned char *nh = skb_network_header(skb);
  901. switch (ip_hdr(skb)->protocol) {
  902. case IPPROTO_TCP:
  903. dflags |= XCT_MACTX_CSUM_TCP;
  904. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  905. dflags |= XCT_MACTX_IPO(nh - skb->data);
  906. break;
  907. case IPPROTO_UDP:
  908. dflags |= XCT_MACTX_CSUM_UDP;
  909. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  910. dflags |= XCT_MACTX_IPO(nh - skb->data);
  911. break;
  912. }
  913. }
  914. nfrags = skb_shinfo(skb)->nr_frags;
  915. map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
  916. PCI_DMA_TODEVICE);
  917. map_size[0] = skb_headlen(skb);
  918. if (dma_mapping_error(map[0]))
  919. goto out_err_nolock;
  920. for (i = 0; i < nfrags; i++) {
  921. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  922. map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
  923. frag->page_offset, frag->size,
  924. PCI_DMA_TODEVICE);
  925. map_size[i+1] = frag->size;
  926. if (dma_mapping_error(map[i+1])) {
  927. nfrags = i;
  928. goto out_err_nolock;
  929. }
  930. }
  931. mactx = dflags | XCT_MACTX_LLEN(skb->len);
  932. txring = tx_ring(mac);
  933. spin_lock_irqsave(&txring->lock, flags);
  934. /* Avoid stepping on the same cache line that the DMA controller
  935. * is currently about to send, so leave at least 8 words available.
  936. * Total free space needed is mactx + fragments + 8
  937. */
  938. if (RING_AVAIL(txring) < nfrags + 10) {
  939. /* no room -- stop the queue and wait for tx intr */
  940. netif_stop_queue(dev);
  941. goto out_err;
  942. }
  943. TX_DESC(txring, txring->next_to_fill) = mactx;
  944. txring->next_to_fill++;
  945. TX_DESC_INFO(txring, txring->next_to_fill).skb = skb;
  946. for (i = 0; i <= nfrags; i++) {
  947. TX_DESC(txring, txring->next_to_fill+i) =
  948. XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
  949. TX_DESC_INFO(txring, txring->next_to_fill+i).dma = map[i];
  950. }
  951. /* We have to add an even number of 8-byte entries to the ring
  952. * even if the last one is unused. That means always an odd number
  953. * of pointers + one mactx descriptor.
  954. */
  955. if (nfrags & 1)
  956. nfrags++;
  957. txring->next_to_fill = (txring->next_to_fill + nfrags + 1) &
  958. (TX_RING_SIZE-1);
  959. dev->stats.tx_packets++;
  960. dev->stats.tx_bytes += skb->len;
  961. spin_unlock_irqrestore(&txring->lock, flags);
  962. write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
  963. return NETDEV_TX_OK;
  964. out_err:
  965. spin_unlock_irqrestore(&txring->lock, flags);
  966. out_err_nolock:
  967. while (nfrags--)
  968. pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
  969. PCI_DMA_TODEVICE);
  970. return NETDEV_TX_BUSY;
  971. }
  972. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  973. {
  974. struct pasemi_mac *mac = netdev_priv(dev);
  975. unsigned int flags;
  976. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  977. /* Set promiscuous */
  978. if (dev->flags & IFF_PROMISC)
  979. flags |= PAS_MAC_CFG_PCFG_PR;
  980. else
  981. flags &= ~PAS_MAC_CFG_PCFG_PR;
  982. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  983. }
  984. static int pasemi_mac_poll(struct napi_struct *napi, int budget)
  985. {
  986. struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
  987. struct net_device *dev = mac->netdev;
  988. int pkts;
  989. pasemi_mac_clean_tx(tx_ring(mac));
  990. pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
  991. if (pkts < budget) {
  992. /* all done, no more packets present */
  993. netif_rx_complete(dev, napi);
  994. pasemi_mac_restart_rx_intr(mac);
  995. }
  996. return pkts;
  997. }
  998. static int __devinit
  999. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1000. {
  1001. struct net_device *dev;
  1002. struct pasemi_mac *mac;
  1003. int err;
  1004. DECLARE_MAC_BUF(mac_buf);
  1005. err = pci_enable_device(pdev);
  1006. if (err)
  1007. return err;
  1008. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  1009. if (dev == NULL) {
  1010. dev_err(&pdev->dev,
  1011. "pasemi_mac: Could not allocate ethernet device.\n");
  1012. err = -ENOMEM;
  1013. goto out_disable_device;
  1014. }
  1015. pci_set_drvdata(pdev, dev);
  1016. SET_NETDEV_DEV(dev, &pdev->dev);
  1017. mac = netdev_priv(dev);
  1018. mac->pdev = pdev;
  1019. mac->netdev = dev;
  1020. netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
  1021. dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG;
  1022. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  1023. if (!mac->dma_pdev) {
  1024. dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
  1025. err = -ENODEV;
  1026. goto out;
  1027. }
  1028. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  1029. if (!mac->iob_pdev) {
  1030. dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
  1031. err = -ENODEV;
  1032. goto out;
  1033. }
  1034. /* get mac addr from device tree */
  1035. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  1036. err = -ENODEV;
  1037. goto out;
  1038. }
  1039. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  1040. mac->dma_if = mac_to_intf(mac);
  1041. if (mac->dma_if < 0) {
  1042. dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
  1043. err = -ENODEV;
  1044. goto out;
  1045. }
  1046. switch (pdev->device) {
  1047. case 0xa005:
  1048. mac->type = MAC_TYPE_GMAC;
  1049. break;
  1050. case 0xa006:
  1051. mac->type = MAC_TYPE_XAUI;
  1052. break;
  1053. default:
  1054. err = -ENODEV;
  1055. goto out;
  1056. }
  1057. dev->open = pasemi_mac_open;
  1058. dev->stop = pasemi_mac_close;
  1059. dev->hard_start_xmit = pasemi_mac_start_tx;
  1060. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  1061. if (err)
  1062. goto out;
  1063. mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  1064. /* Enable most messages by default */
  1065. mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  1066. err = register_netdev(dev);
  1067. if (err) {
  1068. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  1069. err);
  1070. goto out;
  1071. } else if netif_msg_probe(mac)
  1072. printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %s\n",
  1073. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  1074. mac->dma_if, print_mac(mac_buf, dev->dev_addr));
  1075. return err;
  1076. out:
  1077. if (mac->iob_pdev)
  1078. pci_dev_put(mac->iob_pdev);
  1079. if (mac->dma_pdev)
  1080. pci_dev_put(mac->dma_pdev);
  1081. free_netdev(dev);
  1082. out_disable_device:
  1083. pci_disable_device(pdev);
  1084. return err;
  1085. }
  1086. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  1087. {
  1088. struct net_device *netdev = pci_get_drvdata(pdev);
  1089. struct pasemi_mac *mac;
  1090. if (!netdev)
  1091. return;
  1092. mac = netdev_priv(netdev);
  1093. unregister_netdev(netdev);
  1094. pci_disable_device(pdev);
  1095. pci_dev_put(mac->dma_pdev);
  1096. pci_dev_put(mac->iob_pdev);
  1097. pasemi_dma_free_chan(&mac->tx->chan);
  1098. pasemi_dma_free_chan(&mac->rx->chan);
  1099. pci_set_drvdata(pdev, NULL);
  1100. free_netdev(netdev);
  1101. }
  1102. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  1103. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  1104. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  1105. { },
  1106. };
  1107. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  1108. static struct pci_driver pasemi_mac_driver = {
  1109. .name = "pasemi_mac",
  1110. .id_table = pasemi_mac_pci_tbl,
  1111. .probe = pasemi_mac_probe,
  1112. .remove = __devexit_p(pasemi_mac_remove),
  1113. };
  1114. static void __exit pasemi_mac_cleanup_module(void)
  1115. {
  1116. pci_unregister_driver(&pasemi_mac_driver);
  1117. }
  1118. int pasemi_mac_init_module(void)
  1119. {
  1120. int err;
  1121. err = pasemi_dma_init();
  1122. if (err)
  1123. return err;
  1124. return pci_register_driver(&pasemi_mac_driver);
  1125. }
  1126. module_init(pasemi_mac_init_module);
  1127. module_exit(pasemi_mac_cleanup_module);