regs-apbx.h 4.7 KB

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  1. /*
  2. * STMP APBX Register Definitions
  3. *
  4. * Copyright (c) 2008 Freescale Semiconductor
  5. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #ifndef _INCLUDE_ASM_ARCH_REGS_APBX_H
  22. #define _INCLUDE_ASM_ARCH_REGS_APBX_H
  23. #include <mach/stmp3xxx_regs.h>
  24. #ifndef REGS_APBX_BASE
  25. #define REGS_APBX_BASE (REGS_BASE + 0x00024000)
  26. #endif
  27. HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00)
  28. #define BP_APBX_CTRL0_SFTRST 31
  29. #define BM_APBX_CTRL0_SFTRST 0x80000000
  30. #define BP_APBX_CTRL0_CLKGATE 30
  31. #define BM_APBX_CTRL0_CLKGATE 0x40000000
  32. #define BP_APBX_CTRL0_RESET_CHANNEL 16
  33. #define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
  34. #define BF_APBX_CTRL0_RESET_CHANNEL(v) \
  35. (((v) << BP_APBX_CTRL0_RESET_CHANNEL) & BM_APBX_CTRL0_RESET_CHANNEL)
  36. HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x10)
  37. HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x20)
  38. #define BP_APBX_DEVSEL_CH7 28
  39. #define BM_APBX_DEVSEL_CH7 0xF0000000
  40. #define BF_APBX_DEVSEL_CH7(v) \
  41. (((v) << BP_APBX_DEVSEL_CH7) & BM_APBX_DEVSEL_CH7)
  42. #define BV_APBX_DEVSEL_CH7__USE_UART 0x0
  43. #define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1
  44. #define BP_APBX_DEVSEL_CH6 24
  45. #define BM_APBX_DEVSEL_CH6 0x0F000000
  46. #define BF_APBX_DEVSEL_CH6(v) \
  47. (((v) << BP_APBX_DEVSEL_CH6) & BM_APBX_DEVSEL_CH6)
  48. #define BV_APBX_DEVSEL_CH6__USE_UART 0x0
  49. #define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1
  50. #define BP_APBX_CTRL1_CH7_AHB_ERROR_IRQ 23
  51. #define BM_APBX_CTRL1_CH7_AHB_ERROR_IRQ 0x00800000
  52. #define BP_APBX_CTRL1_CH6_AHB_ERROR_IRQ 22
  53. #define BM_APBX_CTRL1_CH6_AHB_ERROR_IRQ 0x00400000
  54. #define BP_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 15
  55. #define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00008000
  56. #define BP_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 14
  57. #define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00004000
  58. HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x40, 0x70)
  59. HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x50, 0x70)
  60. #define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0
  61. #define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
  62. #define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v)
  63. HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x60, 0x70)
  64. #define BP_APBX_CHn_CMD_XFER_COUNT 16
  65. #define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
  66. #define BF_APBX_CHn_CMD_XFER_COUNT(v) \
  67. (((v) << BP_APBX_CHn_CMD_XFER_COUNT) & BM_APBX_CHn_CMD_XFER_COUNT)
  68. #define BP_APBX_CHn_CMD_CMDWORDS 12
  69. #define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
  70. #define BF_APBX_CHn_CMD_CMDWORDS(v) \
  71. (((v) << BP_APBX_CHn_CMD_CMDWORDS) & BM_APBX_CHn_CMD_CMDWORDS)
  72. #define BP_APBX_CHn_CMD_WAIT4ENDCMD 7
  73. #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
  74. #define BP_APBX_CHn_CMD_SEMAPHORE 6
  75. #define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
  76. #define BP_APBX_CHn_CMD_IRQONCMPLT 3
  77. #define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
  78. #define BP_APBX_CHn_CMD_CHAIN 2
  79. #define BM_APBX_CHn_CMD_CHAIN 0x00000004
  80. #define BM_APBX_CHn_CMD_DMA_READ 0x00000003
  81. #define BP_APBX_CHn_CMD_DMA_READ 0
  82. #define BF_APBX_CHn_CMD_DMA_READ(v) \
  83. (((v) << BP_APBX_CHn_CMD_DMA_READ) & BM_APBX_CHn_CMD_DMA_READ)
  84. #define BP_APBX_CHn_CMD_COMMAND 0
  85. #define BM_APBX_CHn_CMD_COMMAND 0x00000003
  86. #define BF_APBX_CHn_CMD_COMMAND(v) \
  87. (((v) << BP_APBX_CHn_CMD_COMMAND) & BM_APBX_CHn_CMD_COMMAND)
  88. #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
  89. #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1
  90. #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2
  91. HW_REGISTER_RO_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x70, 0x70)
  92. HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x80, 0x70)
  93. #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
  94. #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
  95. #define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \
  96. (((v) << BP_APBX_CHn_SEMA_INCREMENT_SEMA) & \
  97. BM_APBX_CHn_SEMA_INCREMENT_SEMA)
  98. #define BP_APBX_CHn_SEMA_PHORE 16
  99. #define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
  100. HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x90, 0x70)
  101. HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0xA0, 0x70)
  102. HW_REGISTER_RO(HW_APBX_VERSION, REGS_APBX_BASE, 0x3F0)
  103. #endif /* _INCLUDE_ASM_ARCH_REGS_APBX_H */