be_main.c 61 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441
  1. /*
  2. * Copyright (C) 2005 - 2009 ServerEngines
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@serverengines.com
  12. *
  13. * ServerEngines
  14. * 209 N. Fair Oaks Ave
  15. * Sunnyvale, CA 94085
  16. */
  17. #include "be.h"
  18. #include "be_cmds.h"
  19. #include <asm/div64.h>
  20. MODULE_VERSION(DRV_VER);
  21. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  22. MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
  23. MODULE_AUTHOR("ServerEngines Corporation");
  24. MODULE_LICENSE("GPL");
  25. static unsigned int rx_frag_size = 2048;
  26. module_param(rx_frag_size, uint, S_IRUGO);
  27. MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
  28. static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
  29. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  30. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  31. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  32. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  33. { 0 }
  34. };
  35. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  36. static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
  37. {
  38. struct be_dma_mem *mem = &q->dma_mem;
  39. if (mem->va)
  40. pci_free_consistent(adapter->pdev, mem->size,
  41. mem->va, mem->dma);
  42. }
  43. static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
  44. u16 len, u16 entry_size)
  45. {
  46. struct be_dma_mem *mem = &q->dma_mem;
  47. memset(q, 0, sizeof(*q));
  48. q->len = len;
  49. q->entry_size = entry_size;
  50. mem->size = len * entry_size;
  51. mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
  52. if (!mem->va)
  53. return -1;
  54. memset(mem->va, 0, mem->size);
  55. return 0;
  56. }
  57. static void be_intr_set(struct be_adapter *adapter, bool enable)
  58. {
  59. u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  60. u32 reg = ioread32(addr);
  61. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  62. if (!enabled && enable)
  63. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  64. else if (enabled && !enable)
  65. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  66. else
  67. return;
  68. iowrite32(reg, addr);
  69. }
  70. static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  71. {
  72. u32 val = 0;
  73. val |= qid & DB_RQ_RING_ID_MASK;
  74. val |= posted << DB_RQ_NUM_POSTED_SHIFT;
  75. iowrite32(val, adapter->db + DB_RQ_OFFSET);
  76. }
  77. static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  78. {
  79. u32 val = 0;
  80. val |= qid & DB_TXULP_RING_ID_MASK;
  81. val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
  82. iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
  83. }
  84. static void be_eq_notify(struct be_adapter *adapter, u16 qid,
  85. bool arm, bool clear_int, u16 num_popped)
  86. {
  87. u32 val = 0;
  88. val |= qid & DB_EQ_RING_ID_MASK;
  89. if (arm)
  90. val |= 1 << DB_EQ_REARM_SHIFT;
  91. if (clear_int)
  92. val |= 1 << DB_EQ_CLR_SHIFT;
  93. val |= 1 << DB_EQ_EVNT_SHIFT;
  94. val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
  95. iowrite32(val, adapter->db + DB_EQ_OFFSET);
  96. }
  97. void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
  98. {
  99. u32 val = 0;
  100. val |= qid & DB_CQ_RING_ID_MASK;
  101. if (arm)
  102. val |= 1 << DB_CQ_REARM_SHIFT;
  103. val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
  104. iowrite32(val, adapter->db + DB_CQ_OFFSET);
  105. }
  106. static int be_mac_addr_set(struct net_device *netdev, void *p)
  107. {
  108. struct be_adapter *adapter = netdev_priv(netdev);
  109. struct sockaddr *addr = p;
  110. int status = 0;
  111. if (!is_valid_ether_addr(addr->sa_data))
  112. return -EADDRNOTAVAIL;
  113. status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
  114. if (status)
  115. return status;
  116. status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
  117. adapter->if_handle, &adapter->pmac_id);
  118. if (!status)
  119. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  120. return status;
  121. }
  122. void netdev_stats_update(struct be_adapter *adapter)
  123. {
  124. struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
  125. struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
  126. struct be_port_rxf_stats *port_stats =
  127. &rxf_stats->port[adapter->port_num];
  128. struct net_device_stats *dev_stats = &adapter->netdev->stats;
  129. struct be_erx_stats *erx_stats = &hw_stats->erx;
  130. dev_stats->rx_packets = port_stats->rx_total_frames;
  131. dev_stats->tx_packets = port_stats->tx_unicastframes +
  132. port_stats->tx_multicastframes + port_stats->tx_broadcastframes;
  133. dev_stats->rx_bytes = (u64) port_stats->rx_bytes_msd << 32 |
  134. (u64) port_stats->rx_bytes_lsd;
  135. dev_stats->tx_bytes = (u64) port_stats->tx_bytes_msd << 32 |
  136. (u64) port_stats->tx_bytes_lsd;
  137. /* bad pkts received */
  138. dev_stats->rx_errors = port_stats->rx_crc_errors +
  139. port_stats->rx_alignment_symbol_errors +
  140. port_stats->rx_in_range_errors +
  141. port_stats->rx_out_range_errors +
  142. port_stats->rx_frame_too_long +
  143. port_stats->rx_dropped_too_small +
  144. port_stats->rx_dropped_too_short +
  145. port_stats->rx_dropped_header_too_small +
  146. port_stats->rx_dropped_tcp_length +
  147. port_stats->rx_dropped_runt +
  148. port_stats->rx_tcp_checksum_errs +
  149. port_stats->rx_ip_checksum_errs +
  150. port_stats->rx_udp_checksum_errs;
  151. /* no space in linux buffers: best possible approximation */
  152. dev_stats->rx_dropped =
  153. erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
  154. /* detailed rx errors */
  155. dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
  156. port_stats->rx_out_range_errors +
  157. port_stats->rx_frame_too_long;
  158. /* receive ring buffer overflow */
  159. dev_stats->rx_over_errors = 0;
  160. dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
  161. /* frame alignment errors */
  162. dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
  163. /* receiver fifo overrun */
  164. /* drops_no_pbuf is no per i/f, it's per BE card */
  165. dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
  166. port_stats->rx_input_fifo_overflow +
  167. rxf_stats->rx_drops_no_pbuf;
  168. /* receiver missed packetd */
  169. dev_stats->rx_missed_errors = 0;
  170. /* packet transmit problems */
  171. dev_stats->tx_errors = 0;
  172. /* no space available in linux */
  173. dev_stats->tx_dropped = 0;
  174. dev_stats->multicast = port_stats->rx_multicast_frames;
  175. dev_stats->collisions = 0;
  176. /* detailed tx_errors */
  177. dev_stats->tx_aborted_errors = 0;
  178. dev_stats->tx_carrier_errors = 0;
  179. dev_stats->tx_fifo_errors = 0;
  180. dev_stats->tx_heartbeat_errors = 0;
  181. dev_stats->tx_window_errors = 0;
  182. }
  183. void be_link_status_update(struct be_adapter *adapter, bool link_up)
  184. {
  185. struct net_device *netdev = adapter->netdev;
  186. /* If link came up or went down */
  187. if (adapter->link_up != link_up) {
  188. adapter->link_speed = -1;
  189. if (link_up) {
  190. netif_start_queue(netdev);
  191. netif_carrier_on(netdev);
  192. printk(KERN_INFO "%s: Link up\n", netdev->name);
  193. } else {
  194. netif_stop_queue(netdev);
  195. netif_carrier_off(netdev);
  196. printk(KERN_INFO "%s: Link down\n", netdev->name);
  197. }
  198. adapter->link_up = link_up;
  199. }
  200. }
  201. /* Update the EQ delay n BE based on the RX frags consumed / sec */
  202. static void be_rx_eqd_update(struct be_adapter *adapter)
  203. {
  204. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  205. struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
  206. ulong now = jiffies;
  207. u32 eqd;
  208. if (!rx_eq->enable_aic)
  209. return;
  210. /* Wrapped around */
  211. if (time_before(now, stats->rx_fps_jiffies)) {
  212. stats->rx_fps_jiffies = now;
  213. return;
  214. }
  215. /* Update once a second */
  216. if ((now - stats->rx_fps_jiffies) < HZ)
  217. return;
  218. stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
  219. ((now - stats->rx_fps_jiffies) / HZ);
  220. stats->rx_fps_jiffies = now;
  221. stats->be_prev_rx_frags = stats->be_rx_frags;
  222. eqd = stats->be_rx_fps / 110000;
  223. eqd = eqd << 3;
  224. if (eqd > rx_eq->max_eqd)
  225. eqd = rx_eq->max_eqd;
  226. if (eqd < rx_eq->min_eqd)
  227. eqd = rx_eq->min_eqd;
  228. if (eqd < 10)
  229. eqd = 0;
  230. if (eqd != rx_eq->cur_eqd)
  231. be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
  232. rx_eq->cur_eqd = eqd;
  233. }
  234. static struct net_device_stats *be_get_stats(struct net_device *dev)
  235. {
  236. return &dev->stats;
  237. }
  238. static u32 be_calc_rate(u64 bytes, unsigned long ticks)
  239. {
  240. u64 rate = bytes;
  241. do_div(rate, ticks / HZ);
  242. rate <<= 3; /* bytes/sec -> bits/sec */
  243. do_div(rate, 1000000ul); /* MB/Sec */
  244. return rate;
  245. }
  246. static void be_tx_rate_update(struct be_adapter *adapter)
  247. {
  248. struct be_drvr_stats *stats = drvr_stats(adapter);
  249. ulong now = jiffies;
  250. /* Wrapped around? */
  251. if (time_before(now, stats->be_tx_jiffies)) {
  252. stats->be_tx_jiffies = now;
  253. return;
  254. }
  255. /* Update tx rate once in two seconds */
  256. if ((now - stats->be_tx_jiffies) > 2 * HZ) {
  257. stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
  258. - stats->be_tx_bytes_prev,
  259. now - stats->be_tx_jiffies);
  260. stats->be_tx_jiffies = now;
  261. stats->be_tx_bytes_prev = stats->be_tx_bytes;
  262. }
  263. }
  264. static void be_tx_stats_update(struct be_adapter *adapter,
  265. u32 wrb_cnt, u32 copied, bool stopped)
  266. {
  267. struct be_drvr_stats *stats = drvr_stats(adapter);
  268. stats->be_tx_reqs++;
  269. stats->be_tx_wrbs += wrb_cnt;
  270. stats->be_tx_bytes += copied;
  271. if (stopped)
  272. stats->be_tx_stops++;
  273. }
  274. /* Determine number of WRB entries needed to xmit data in an skb */
  275. static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
  276. {
  277. int cnt = (skb->len > skb->data_len);
  278. cnt += skb_shinfo(skb)->nr_frags;
  279. /* to account for hdr wrb */
  280. cnt++;
  281. if (cnt & 1) {
  282. /* add a dummy to make it an even num */
  283. cnt++;
  284. *dummy = true;
  285. } else
  286. *dummy = false;
  287. BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
  288. return cnt;
  289. }
  290. static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
  291. {
  292. wrb->frag_pa_hi = upper_32_bits(addr);
  293. wrb->frag_pa_lo = addr & 0xFFFFFFFF;
  294. wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
  295. }
  296. static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
  297. bool vlan, u32 wrb_cnt, u32 len)
  298. {
  299. memset(hdr, 0, sizeof(*hdr));
  300. AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
  301. if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
  302. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
  303. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
  304. hdr, skb_shinfo(skb)->gso_size);
  305. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  306. if (is_tcp_pkt(skb))
  307. AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
  308. else if (is_udp_pkt(skb))
  309. AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
  310. }
  311. if (vlan && vlan_tx_tag_present(skb)) {
  312. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
  313. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
  314. hdr, vlan_tx_tag_get(skb));
  315. }
  316. AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
  317. AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
  318. AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
  319. AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
  320. }
  321. static int make_tx_wrbs(struct be_adapter *adapter,
  322. struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
  323. {
  324. u64 busaddr;
  325. u32 i, copied = 0;
  326. struct pci_dev *pdev = adapter->pdev;
  327. struct sk_buff *first_skb = skb;
  328. struct be_queue_info *txq = &adapter->tx_obj.q;
  329. struct be_eth_wrb *wrb;
  330. struct be_eth_hdr_wrb *hdr;
  331. hdr = queue_head_node(txq);
  332. atomic_add(wrb_cnt, &txq->used);
  333. queue_head_inc(txq);
  334. if (skb->len > skb->data_len) {
  335. int len = skb->len - skb->data_len;
  336. busaddr = pci_map_single(pdev, skb->data, len,
  337. PCI_DMA_TODEVICE);
  338. wrb = queue_head_node(txq);
  339. wrb_fill(wrb, busaddr, len);
  340. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  341. queue_head_inc(txq);
  342. copied += len;
  343. }
  344. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  345. struct skb_frag_struct *frag =
  346. &skb_shinfo(skb)->frags[i];
  347. busaddr = pci_map_page(pdev, frag->page,
  348. frag->page_offset,
  349. frag->size, PCI_DMA_TODEVICE);
  350. wrb = queue_head_node(txq);
  351. wrb_fill(wrb, busaddr, frag->size);
  352. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  353. queue_head_inc(txq);
  354. copied += frag->size;
  355. }
  356. if (dummy_wrb) {
  357. wrb = queue_head_node(txq);
  358. wrb_fill(wrb, 0, 0);
  359. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  360. queue_head_inc(txq);
  361. }
  362. wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
  363. wrb_cnt, copied);
  364. be_dws_cpu_to_le(hdr, sizeof(*hdr));
  365. return copied;
  366. }
  367. static netdev_tx_t be_xmit(struct sk_buff *skb,
  368. struct net_device *netdev)
  369. {
  370. struct be_adapter *adapter = netdev_priv(netdev);
  371. struct be_tx_obj *tx_obj = &adapter->tx_obj;
  372. struct be_queue_info *txq = &tx_obj->q;
  373. u32 wrb_cnt = 0, copied = 0;
  374. u32 start = txq->head;
  375. bool dummy_wrb, stopped = false;
  376. wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
  377. copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
  378. if (copied) {
  379. /* record the sent skb in the sent_skb table */
  380. BUG_ON(tx_obj->sent_skb_list[start]);
  381. tx_obj->sent_skb_list[start] = skb;
  382. /* Ensure txq has space for the next skb; Else stop the queue
  383. * *BEFORE* ringing the tx doorbell, so that we serialze the
  384. * tx compls of the current transmit which'll wake up the queue
  385. */
  386. if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
  387. txq->len) {
  388. netif_stop_queue(netdev);
  389. stopped = true;
  390. }
  391. be_txq_notify(adapter, txq->id, wrb_cnt);
  392. be_tx_stats_update(adapter, wrb_cnt, copied, stopped);
  393. } else {
  394. txq->head = start;
  395. dev_kfree_skb_any(skb);
  396. }
  397. return NETDEV_TX_OK;
  398. }
  399. static int be_change_mtu(struct net_device *netdev, int new_mtu)
  400. {
  401. struct be_adapter *adapter = netdev_priv(netdev);
  402. if (new_mtu < BE_MIN_MTU ||
  403. new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
  404. (ETH_HLEN + ETH_FCS_LEN))) {
  405. dev_info(&adapter->pdev->dev,
  406. "MTU must be between %d and %d bytes\n",
  407. BE_MIN_MTU,
  408. (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
  409. return -EINVAL;
  410. }
  411. dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
  412. netdev->mtu, new_mtu);
  413. netdev->mtu = new_mtu;
  414. return 0;
  415. }
  416. /*
  417. * if there are BE_NUM_VLANS_SUPPORTED or lesser number of VLANS configured,
  418. * program them in BE. If more than BE_NUM_VLANS_SUPPORTED are configured,
  419. * set the BE in promiscuous VLAN mode.
  420. */
  421. static int be_vid_config(struct be_adapter *adapter)
  422. {
  423. u16 vtag[BE_NUM_VLANS_SUPPORTED];
  424. u16 ntags = 0, i;
  425. int status;
  426. if (adapter->num_vlans <= BE_NUM_VLANS_SUPPORTED) {
  427. /* Construct VLAN Table to give to HW */
  428. for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
  429. if (adapter->vlan_tag[i]) {
  430. vtag[ntags] = cpu_to_le16(i);
  431. ntags++;
  432. }
  433. }
  434. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  435. vtag, ntags, 1, 0);
  436. } else {
  437. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  438. NULL, 0, 1, 1);
  439. }
  440. return status;
  441. }
  442. static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
  443. {
  444. struct be_adapter *adapter = netdev_priv(netdev);
  445. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  446. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  447. be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
  448. be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
  449. adapter->vlan_grp = grp;
  450. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  451. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  452. }
  453. static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
  454. {
  455. struct be_adapter *adapter = netdev_priv(netdev);
  456. adapter->num_vlans++;
  457. adapter->vlan_tag[vid] = 1;
  458. be_vid_config(adapter);
  459. }
  460. static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
  461. {
  462. struct be_adapter *adapter = netdev_priv(netdev);
  463. adapter->num_vlans--;
  464. adapter->vlan_tag[vid] = 0;
  465. vlan_group_set_device(adapter->vlan_grp, vid, NULL);
  466. be_vid_config(adapter);
  467. }
  468. static void be_set_multicast_list(struct net_device *netdev)
  469. {
  470. struct be_adapter *adapter = netdev_priv(netdev);
  471. if (netdev->flags & IFF_PROMISC) {
  472. be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
  473. adapter->promiscuous = true;
  474. goto done;
  475. }
  476. /* BE was previously in promiscous mode; disable it */
  477. if (adapter->promiscuous) {
  478. adapter->promiscuous = false;
  479. be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
  480. }
  481. /* Enable multicast promisc if num configured exceeds what we support */
  482. if (netdev->flags & IFF_ALLMULTI ||
  483. netdev_mc_count(netdev) > BE_MAX_MC) {
  484. be_cmd_multicast_set(adapter, adapter->if_handle, NULL, 0,
  485. &adapter->mc_cmd_mem);
  486. goto done;
  487. }
  488. be_cmd_multicast_set(adapter, adapter->if_handle, netdev->mc_list,
  489. netdev_mc_count(netdev), &adapter->mc_cmd_mem);
  490. done:
  491. return;
  492. }
  493. static void be_rx_rate_update(struct be_adapter *adapter)
  494. {
  495. struct be_drvr_stats *stats = drvr_stats(adapter);
  496. ulong now = jiffies;
  497. /* Wrapped around */
  498. if (time_before(now, stats->be_rx_jiffies)) {
  499. stats->be_rx_jiffies = now;
  500. return;
  501. }
  502. /* Update the rate once in two seconds */
  503. if ((now - stats->be_rx_jiffies) < 2 * HZ)
  504. return;
  505. stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
  506. - stats->be_rx_bytes_prev,
  507. now - stats->be_rx_jiffies);
  508. stats->be_rx_jiffies = now;
  509. stats->be_rx_bytes_prev = stats->be_rx_bytes;
  510. }
  511. static void be_rx_stats_update(struct be_adapter *adapter,
  512. u32 pktsize, u16 numfrags)
  513. {
  514. struct be_drvr_stats *stats = drvr_stats(adapter);
  515. stats->be_rx_compl++;
  516. stats->be_rx_frags += numfrags;
  517. stats->be_rx_bytes += pktsize;
  518. }
  519. static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
  520. {
  521. u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
  522. l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
  523. ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
  524. ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
  525. if (ip_version) {
  526. tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  527. udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
  528. }
  529. ipv6_chk = (ip_version && (tcpf || udpf));
  530. return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
  531. }
  532. static struct be_rx_page_info *
  533. get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
  534. {
  535. struct be_rx_page_info *rx_page_info;
  536. struct be_queue_info *rxq = &adapter->rx_obj.q;
  537. rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
  538. BUG_ON(!rx_page_info->page);
  539. if (rx_page_info->last_page_user)
  540. pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus),
  541. adapter->big_page_size, PCI_DMA_FROMDEVICE);
  542. atomic_dec(&rxq->used);
  543. return rx_page_info;
  544. }
  545. /* Throwaway the data in the Rx completion */
  546. static void be_rx_compl_discard(struct be_adapter *adapter,
  547. struct be_eth_rx_compl *rxcp)
  548. {
  549. struct be_queue_info *rxq = &adapter->rx_obj.q;
  550. struct be_rx_page_info *page_info;
  551. u16 rxq_idx, i, num_rcvd;
  552. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  553. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  554. for (i = 0; i < num_rcvd; i++) {
  555. page_info = get_rx_page_info(adapter, rxq_idx);
  556. put_page(page_info->page);
  557. memset(page_info, 0, sizeof(*page_info));
  558. index_inc(&rxq_idx, rxq->len);
  559. }
  560. }
  561. /*
  562. * skb_fill_rx_data forms a complete skb for an ether frame
  563. * indicated by rxcp.
  564. */
  565. static void skb_fill_rx_data(struct be_adapter *adapter,
  566. struct sk_buff *skb, struct be_eth_rx_compl *rxcp)
  567. {
  568. struct be_queue_info *rxq = &adapter->rx_obj.q;
  569. struct be_rx_page_info *page_info;
  570. u16 rxq_idx, i, num_rcvd, j;
  571. u32 pktsize, hdr_len, curr_frag_len, size;
  572. u8 *start;
  573. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  574. pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  575. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  576. page_info = get_rx_page_info(adapter, rxq_idx);
  577. start = page_address(page_info->page) + page_info->page_offset;
  578. prefetch(start);
  579. /* Copy data in the first descriptor of this completion */
  580. curr_frag_len = min(pktsize, rx_frag_size);
  581. /* Copy the header portion into skb_data */
  582. hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
  583. memcpy(skb->data, start, hdr_len);
  584. skb->len = curr_frag_len;
  585. if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
  586. /* Complete packet has now been moved to data */
  587. put_page(page_info->page);
  588. skb->data_len = 0;
  589. skb->tail += curr_frag_len;
  590. } else {
  591. skb_shinfo(skb)->nr_frags = 1;
  592. skb_shinfo(skb)->frags[0].page = page_info->page;
  593. skb_shinfo(skb)->frags[0].page_offset =
  594. page_info->page_offset + hdr_len;
  595. skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
  596. skb->data_len = curr_frag_len - hdr_len;
  597. skb->tail += hdr_len;
  598. }
  599. memset(page_info, 0, sizeof(*page_info));
  600. if (pktsize <= rx_frag_size) {
  601. BUG_ON(num_rcvd != 1);
  602. goto done;
  603. }
  604. /* More frags present for this completion */
  605. size = pktsize;
  606. for (i = 1, j = 0; i < num_rcvd; i++) {
  607. size -= curr_frag_len;
  608. index_inc(&rxq_idx, rxq->len);
  609. page_info = get_rx_page_info(adapter, rxq_idx);
  610. curr_frag_len = min(size, rx_frag_size);
  611. /* Coalesce all frags from the same physical page in one slot */
  612. if (page_info->page_offset == 0) {
  613. /* Fresh page */
  614. j++;
  615. skb_shinfo(skb)->frags[j].page = page_info->page;
  616. skb_shinfo(skb)->frags[j].page_offset =
  617. page_info->page_offset;
  618. skb_shinfo(skb)->frags[j].size = 0;
  619. skb_shinfo(skb)->nr_frags++;
  620. } else {
  621. put_page(page_info->page);
  622. }
  623. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  624. skb->len += curr_frag_len;
  625. skb->data_len += curr_frag_len;
  626. memset(page_info, 0, sizeof(*page_info));
  627. }
  628. BUG_ON(j > MAX_SKB_FRAGS);
  629. done:
  630. be_rx_stats_update(adapter, pktsize, num_rcvd);
  631. return;
  632. }
  633. /* Process the RX completion indicated by rxcp when GRO is disabled */
  634. static void be_rx_compl_process(struct be_adapter *adapter,
  635. struct be_eth_rx_compl *rxcp)
  636. {
  637. struct sk_buff *skb;
  638. u32 vlanf, vid;
  639. u8 vtm;
  640. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  641. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  642. /* vlanf could be wrongly set in some cards.
  643. * ignore if vtm is not set */
  644. if ((adapter->cap & 0x400) && !vtm)
  645. vlanf = 0;
  646. skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
  647. if (!skb) {
  648. if (net_ratelimit())
  649. dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
  650. be_rx_compl_discard(adapter, rxcp);
  651. return;
  652. }
  653. skb_fill_rx_data(adapter, skb, rxcp);
  654. if (do_pkt_csum(rxcp, adapter->rx_csum))
  655. skb->ip_summed = CHECKSUM_NONE;
  656. else
  657. skb->ip_summed = CHECKSUM_UNNECESSARY;
  658. skb->truesize = skb->len + sizeof(struct sk_buff);
  659. skb->protocol = eth_type_trans(skb, adapter->netdev);
  660. skb->dev = adapter->netdev;
  661. if (vlanf) {
  662. if (!adapter->vlan_grp || adapter->num_vlans == 0) {
  663. kfree_skb(skb);
  664. return;
  665. }
  666. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  667. vid = be16_to_cpu(vid);
  668. vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
  669. } else {
  670. netif_receive_skb(skb);
  671. }
  672. return;
  673. }
  674. /* Process the RX completion indicated by rxcp when GRO is enabled */
  675. static void be_rx_compl_process_gro(struct be_adapter *adapter,
  676. struct be_eth_rx_compl *rxcp)
  677. {
  678. struct be_rx_page_info *page_info;
  679. struct sk_buff *skb = NULL;
  680. struct be_queue_info *rxq = &adapter->rx_obj.q;
  681. struct be_eq_obj *eq_obj = &adapter->rx_eq;
  682. u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
  683. u16 i, rxq_idx = 0, vid, j;
  684. u8 vtm;
  685. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  686. pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  687. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  688. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  689. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  690. /* vlanf could be wrongly set in some cards.
  691. * ignore if vtm is not set */
  692. if ((adapter->cap & 0x400) && !vtm)
  693. vlanf = 0;
  694. skb = napi_get_frags(&eq_obj->napi);
  695. if (!skb) {
  696. be_rx_compl_discard(adapter, rxcp);
  697. return;
  698. }
  699. remaining = pkt_size;
  700. for (i = 0, j = -1; i < num_rcvd; i++) {
  701. page_info = get_rx_page_info(adapter, rxq_idx);
  702. curr_frag_len = min(remaining, rx_frag_size);
  703. /* Coalesce all frags from the same physical page in one slot */
  704. if (i == 0 || page_info->page_offset == 0) {
  705. /* First frag or Fresh page */
  706. j++;
  707. skb_shinfo(skb)->frags[j].page = page_info->page;
  708. skb_shinfo(skb)->frags[j].page_offset =
  709. page_info->page_offset;
  710. skb_shinfo(skb)->frags[j].size = 0;
  711. } else {
  712. put_page(page_info->page);
  713. }
  714. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  715. remaining -= curr_frag_len;
  716. index_inc(&rxq_idx, rxq->len);
  717. memset(page_info, 0, sizeof(*page_info));
  718. }
  719. BUG_ON(j > MAX_SKB_FRAGS);
  720. skb_shinfo(skb)->nr_frags = j + 1;
  721. skb->len = pkt_size;
  722. skb->data_len = pkt_size;
  723. skb->truesize += pkt_size;
  724. skb->ip_summed = CHECKSUM_UNNECESSARY;
  725. if (likely(!vlanf)) {
  726. napi_gro_frags(&eq_obj->napi);
  727. } else {
  728. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  729. vid = be16_to_cpu(vid);
  730. if (!adapter->vlan_grp || adapter->num_vlans == 0)
  731. return;
  732. vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
  733. }
  734. be_rx_stats_update(adapter, pkt_size, num_rcvd);
  735. return;
  736. }
  737. static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
  738. {
  739. struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
  740. if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
  741. return NULL;
  742. be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
  743. queue_tail_inc(&adapter->rx_obj.cq);
  744. return rxcp;
  745. }
  746. /* To reset the valid bit, we need to reset the whole word as
  747. * when walking the queue the valid entries are little-endian
  748. * and invalid entries are host endian
  749. */
  750. static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
  751. {
  752. rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
  753. }
  754. static inline struct page *be_alloc_pages(u32 size)
  755. {
  756. gfp_t alloc_flags = GFP_ATOMIC;
  757. u32 order = get_order(size);
  758. if (order > 0)
  759. alloc_flags |= __GFP_COMP;
  760. return alloc_pages(alloc_flags, order);
  761. }
  762. /*
  763. * Allocate a page, split it to fragments of size rx_frag_size and post as
  764. * receive buffers to BE
  765. */
  766. static void be_post_rx_frags(struct be_adapter *adapter)
  767. {
  768. struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
  769. struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
  770. struct be_queue_info *rxq = &adapter->rx_obj.q;
  771. struct page *pagep = NULL;
  772. struct be_eth_rx_d *rxd;
  773. u64 page_dmaaddr = 0, frag_dmaaddr;
  774. u32 posted, page_offset = 0;
  775. page_info = &page_info_tbl[rxq->head];
  776. for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
  777. if (!pagep) {
  778. pagep = be_alloc_pages(adapter->big_page_size);
  779. if (unlikely(!pagep)) {
  780. drvr_stats(adapter)->be_ethrx_post_fail++;
  781. break;
  782. }
  783. page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
  784. adapter->big_page_size,
  785. PCI_DMA_FROMDEVICE);
  786. page_info->page_offset = 0;
  787. } else {
  788. get_page(pagep);
  789. page_info->page_offset = page_offset + rx_frag_size;
  790. }
  791. page_offset = page_info->page_offset;
  792. page_info->page = pagep;
  793. pci_unmap_addr_set(page_info, bus, page_dmaaddr);
  794. frag_dmaaddr = page_dmaaddr + page_info->page_offset;
  795. rxd = queue_head_node(rxq);
  796. rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
  797. rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
  798. /* Any space left in the current big page for another frag? */
  799. if ((page_offset + rx_frag_size + rx_frag_size) >
  800. adapter->big_page_size) {
  801. pagep = NULL;
  802. page_info->last_page_user = true;
  803. }
  804. prev_page_info = page_info;
  805. queue_head_inc(rxq);
  806. page_info = &page_info_tbl[rxq->head];
  807. }
  808. if (pagep)
  809. prev_page_info->last_page_user = true;
  810. if (posted) {
  811. atomic_add(posted, &rxq->used);
  812. be_rxq_notify(adapter, rxq->id, posted);
  813. } else if (atomic_read(&rxq->used) == 0) {
  814. /* Let be_worker replenish when memory is available */
  815. adapter->rx_post_starved = true;
  816. }
  817. return;
  818. }
  819. static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
  820. {
  821. struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
  822. if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
  823. return NULL;
  824. be_dws_le_to_cpu(txcp, sizeof(*txcp));
  825. txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
  826. queue_tail_inc(tx_cq);
  827. return txcp;
  828. }
  829. static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
  830. {
  831. struct be_queue_info *txq = &adapter->tx_obj.q;
  832. struct be_eth_wrb *wrb;
  833. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  834. struct sk_buff *sent_skb;
  835. u64 busaddr;
  836. u16 cur_index, num_wrbs = 0;
  837. cur_index = txq->tail;
  838. sent_skb = sent_skbs[cur_index];
  839. BUG_ON(!sent_skb);
  840. sent_skbs[cur_index] = NULL;
  841. wrb = queue_tail_node(txq);
  842. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  843. busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
  844. if (busaddr != 0) {
  845. pci_unmap_single(adapter->pdev, busaddr,
  846. wrb->frag_len, PCI_DMA_TODEVICE);
  847. }
  848. num_wrbs++;
  849. queue_tail_inc(txq);
  850. while (cur_index != last_index) {
  851. cur_index = txq->tail;
  852. wrb = queue_tail_node(txq);
  853. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  854. busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
  855. if (busaddr != 0) {
  856. pci_unmap_page(adapter->pdev, busaddr,
  857. wrb->frag_len, PCI_DMA_TODEVICE);
  858. }
  859. num_wrbs++;
  860. queue_tail_inc(txq);
  861. }
  862. atomic_sub(num_wrbs, &txq->used);
  863. kfree_skb(sent_skb);
  864. }
  865. static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
  866. {
  867. struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
  868. if (!eqe->evt)
  869. return NULL;
  870. eqe->evt = le32_to_cpu(eqe->evt);
  871. queue_tail_inc(&eq_obj->q);
  872. return eqe;
  873. }
  874. static int event_handle(struct be_adapter *adapter,
  875. struct be_eq_obj *eq_obj)
  876. {
  877. struct be_eq_entry *eqe;
  878. u16 num = 0;
  879. while ((eqe = event_get(eq_obj)) != NULL) {
  880. eqe->evt = 0;
  881. num++;
  882. }
  883. /* Deal with any spurious interrupts that come
  884. * without events
  885. */
  886. be_eq_notify(adapter, eq_obj->q.id, true, true, num);
  887. if (num)
  888. napi_schedule(&eq_obj->napi);
  889. return num;
  890. }
  891. /* Just read and notify events without processing them.
  892. * Used at the time of destroying event queues */
  893. static void be_eq_clean(struct be_adapter *adapter,
  894. struct be_eq_obj *eq_obj)
  895. {
  896. struct be_eq_entry *eqe;
  897. u16 num = 0;
  898. while ((eqe = event_get(eq_obj)) != NULL) {
  899. eqe->evt = 0;
  900. num++;
  901. }
  902. if (num)
  903. be_eq_notify(adapter, eq_obj->q.id, false, true, num);
  904. }
  905. static void be_rx_q_clean(struct be_adapter *adapter)
  906. {
  907. struct be_rx_page_info *page_info;
  908. struct be_queue_info *rxq = &adapter->rx_obj.q;
  909. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  910. struct be_eth_rx_compl *rxcp;
  911. u16 tail;
  912. /* First cleanup pending rx completions */
  913. while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
  914. be_rx_compl_discard(adapter, rxcp);
  915. be_rx_compl_reset(rxcp);
  916. be_cq_notify(adapter, rx_cq->id, true, 1);
  917. }
  918. /* Then free posted rx buffer that were not used */
  919. tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
  920. for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
  921. page_info = get_rx_page_info(adapter, tail);
  922. put_page(page_info->page);
  923. memset(page_info, 0, sizeof(*page_info));
  924. }
  925. BUG_ON(atomic_read(&rxq->used));
  926. }
  927. static void be_tx_compl_clean(struct be_adapter *adapter)
  928. {
  929. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  930. struct be_queue_info *txq = &adapter->tx_obj.q;
  931. struct be_eth_tx_compl *txcp;
  932. u16 end_idx, cmpl = 0, timeo = 0;
  933. /* Wait for a max of 200ms for all the tx-completions to arrive. */
  934. do {
  935. while ((txcp = be_tx_compl_get(tx_cq))) {
  936. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  937. wrb_index, txcp);
  938. be_tx_compl_process(adapter, end_idx);
  939. cmpl++;
  940. }
  941. if (cmpl) {
  942. be_cq_notify(adapter, tx_cq->id, false, cmpl);
  943. cmpl = 0;
  944. }
  945. if (atomic_read(&txq->used) == 0 || ++timeo > 200)
  946. break;
  947. mdelay(1);
  948. } while (true);
  949. if (atomic_read(&txq->used))
  950. dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
  951. atomic_read(&txq->used));
  952. }
  953. static void be_mcc_queues_destroy(struct be_adapter *adapter)
  954. {
  955. struct be_queue_info *q;
  956. q = &adapter->mcc_obj.q;
  957. if (q->created)
  958. be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
  959. be_queue_free(adapter, q);
  960. q = &adapter->mcc_obj.cq;
  961. if (q->created)
  962. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  963. be_queue_free(adapter, q);
  964. }
  965. /* Must be called only after TX qs are created as MCC shares TX EQ */
  966. static int be_mcc_queues_create(struct be_adapter *adapter)
  967. {
  968. struct be_queue_info *q, *cq;
  969. /* Alloc MCC compl queue */
  970. cq = &adapter->mcc_obj.cq;
  971. if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
  972. sizeof(struct be_mcc_compl)))
  973. goto err;
  974. /* Ask BE to create MCC compl queue; share TX's eq */
  975. if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
  976. goto mcc_cq_free;
  977. /* Alloc MCC queue */
  978. q = &adapter->mcc_obj.q;
  979. if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  980. goto mcc_cq_destroy;
  981. /* Ask BE to create MCC queue */
  982. if (be_cmd_mccq_create(adapter, q, cq))
  983. goto mcc_q_free;
  984. return 0;
  985. mcc_q_free:
  986. be_queue_free(adapter, q);
  987. mcc_cq_destroy:
  988. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  989. mcc_cq_free:
  990. be_queue_free(adapter, cq);
  991. err:
  992. return -1;
  993. }
  994. static void be_tx_queues_destroy(struct be_adapter *adapter)
  995. {
  996. struct be_queue_info *q;
  997. q = &adapter->tx_obj.q;
  998. if (q->created)
  999. be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
  1000. be_queue_free(adapter, q);
  1001. q = &adapter->tx_obj.cq;
  1002. if (q->created)
  1003. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1004. be_queue_free(adapter, q);
  1005. /* Clear any residual events */
  1006. be_eq_clean(adapter, &adapter->tx_eq);
  1007. q = &adapter->tx_eq.q;
  1008. if (q->created)
  1009. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1010. be_queue_free(adapter, q);
  1011. }
  1012. static int be_tx_queues_create(struct be_adapter *adapter)
  1013. {
  1014. struct be_queue_info *eq, *q, *cq;
  1015. adapter->tx_eq.max_eqd = 0;
  1016. adapter->tx_eq.min_eqd = 0;
  1017. adapter->tx_eq.cur_eqd = 96;
  1018. adapter->tx_eq.enable_aic = false;
  1019. /* Alloc Tx Event queue */
  1020. eq = &adapter->tx_eq.q;
  1021. if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
  1022. return -1;
  1023. /* Ask BE to create Tx Event queue */
  1024. if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
  1025. goto tx_eq_free;
  1026. /* Alloc TX eth compl queue */
  1027. cq = &adapter->tx_obj.cq;
  1028. if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
  1029. sizeof(struct be_eth_tx_compl)))
  1030. goto tx_eq_destroy;
  1031. /* Ask BE to create Tx eth compl queue */
  1032. if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
  1033. goto tx_cq_free;
  1034. /* Alloc TX eth queue */
  1035. q = &adapter->tx_obj.q;
  1036. if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
  1037. goto tx_cq_destroy;
  1038. /* Ask BE to create Tx eth queue */
  1039. if (be_cmd_txq_create(adapter, q, cq))
  1040. goto tx_q_free;
  1041. return 0;
  1042. tx_q_free:
  1043. be_queue_free(adapter, q);
  1044. tx_cq_destroy:
  1045. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1046. tx_cq_free:
  1047. be_queue_free(adapter, cq);
  1048. tx_eq_destroy:
  1049. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1050. tx_eq_free:
  1051. be_queue_free(adapter, eq);
  1052. return -1;
  1053. }
  1054. static void be_rx_queues_destroy(struct be_adapter *adapter)
  1055. {
  1056. struct be_queue_info *q;
  1057. q = &adapter->rx_obj.q;
  1058. if (q->created) {
  1059. be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
  1060. be_rx_q_clean(adapter);
  1061. }
  1062. be_queue_free(adapter, q);
  1063. q = &adapter->rx_obj.cq;
  1064. if (q->created)
  1065. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1066. be_queue_free(adapter, q);
  1067. /* Clear any residual events */
  1068. be_eq_clean(adapter, &adapter->rx_eq);
  1069. q = &adapter->rx_eq.q;
  1070. if (q->created)
  1071. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1072. be_queue_free(adapter, q);
  1073. }
  1074. static int be_rx_queues_create(struct be_adapter *adapter)
  1075. {
  1076. struct be_queue_info *eq, *q, *cq;
  1077. int rc;
  1078. adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
  1079. adapter->rx_eq.max_eqd = BE_MAX_EQD;
  1080. adapter->rx_eq.min_eqd = 0;
  1081. adapter->rx_eq.cur_eqd = 0;
  1082. adapter->rx_eq.enable_aic = true;
  1083. /* Alloc Rx Event queue */
  1084. eq = &adapter->rx_eq.q;
  1085. rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
  1086. sizeof(struct be_eq_entry));
  1087. if (rc)
  1088. return rc;
  1089. /* Ask BE to create Rx Event queue */
  1090. rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
  1091. if (rc)
  1092. goto rx_eq_free;
  1093. /* Alloc RX eth compl queue */
  1094. cq = &adapter->rx_obj.cq;
  1095. rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
  1096. sizeof(struct be_eth_rx_compl));
  1097. if (rc)
  1098. goto rx_eq_destroy;
  1099. /* Ask BE to create Rx eth compl queue */
  1100. rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
  1101. if (rc)
  1102. goto rx_cq_free;
  1103. /* Alloc RX eth queue */
  1104. q = &adapter->rx_obj.q;
  1105. rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
  1106. if (rc)
  1107. goto rx_cq_destroy;
  1108. /* Ask BE to create Rx eth queue */
  1109. rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
  1110. BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
  1111. if (rc)
  1112. goto rx_q_free;
  1113. return 0;
  1114. rx_q_free:
  1115. be_queue_free(adapter, q);
  1116. rx_cq_destroy:
  1117. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1118. rx_cq_free:
  1119. be_queue_free(adapter, cq);
  1120. rx_eq_destroy:
  1121. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1122. rx_eq_free:
  1123. be_queue_free(adapter, eq);
  1124. return rc;
  1125. }
  1126. /* There are 8 evt ids per func. Retruns the evt id's bit number */
  1127. static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
  1128. {
  1129. return eq_id - 8 * be_pci_func(adapter);
  1130. }
  1131. static irqreturn_t be_intx(int irq, void *dev)
  1132. {
  1133. struct be_adapter *adapter = dev;
  1134. int isr;
  1135. isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
  1136. (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
  1137. if (!isr)
  1138. return IRQ_NONE;
  1139. event_handle(adapter, &adapter->tx_eq);
  1140. event_handle(adapter, &adapter->rx_eq);
  1141. return IRQ_HANDLED;
  1142. }
  1143. static irqreturn_t be_msix_rx(int irq, void *dev)
  1144. {
  1145. struct be_adapter *adapter = dev;
  1146. event_handle(adapter, &adapter->rx_eq);
  1147. return IRQ_HANDLED;
  1148. }
  1149. static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
  1150. {
  1151. struct be_adapter *adapter = dev;
  1152. event_handle(adapter, &adapter->tx_eq);
  1153. return IRQ_HANDLED;
  1154. }
  1155. static inline bool do_gro(struct be_adapter *adapter,
  1156. struct be_eth_rx_compl *rxcp)
  1157. {
  1158. int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
  1159. int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  1160. if (err)
  1161. drvr_stats(adapter)->be_rxcp_err++;
  1162. return (tcp_frame && !err) ? true : false;
  1163. }
  1164. int be_poll_rx(struct napi_struct *napi, int budget)
  1165. {
  1166. struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
  1167. struct be_adapter *adapter =
  1168. container_of(rx_eq, struct be_adapter, rx_eq);
  1169. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  1170. struct be_eth_rx_compl *rxcp;
  1171. u32 work_done;
  1172. adapter->stats.drvr_stats.be_rx_polls++;
  1173. for (work_done = 0; work_done < budget; work_done++) {
  1174. rxcp = be_rx_compl_get(adapter);
  1175. if (!rxcp)
  1176. break;
  1177. if (do_gro(adapter, rxcp))
  1178. be_rx_compl_process_gro(adapter, rxcp);
  1179. else
  1180. be_rx_compl_process(adapter, rxcp);
  1181. be_rx_compl_reset(rxcp);
  1182. }
  1183. /* Refill the queue */
  1184. if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
  1185. be_post_rx_frags(adapter);
  1186. /* All consumed */
  1187. if (work_done < budget) {
  1188. napi_complete(napi);
  1189. be_cq_notify(adapter, rx_cq->id, true, work_done);
  1190. } else {
  1191. /* More to be consumed; continue with interrupts disabled */
  1192. be_cq_notify(adapter, rx_cq->id, false, work_done);
  1193. }
  1194. return work_done;
  1195. }
  1196. void be_process_tx(struct be_adapter *adapter)
  1197. {
  1198. struct be_queue_info *txq = &adapter->tx_obj.q;
  1199. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  1200. struct be_eth_tx_compl *txcp;
  1201. u32 num_cmpl = 0;
  1202. u16 end_idx;
  1203. while ((txcp = be_tx_compl_get(tx_cq))) {
  1204. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1205. wrb_index, txcp);
  1206. be_tx_compl_process(adapter, end_idx);
  1207. num_cmpl++;
  1208. }
  1209. if (num_cmpl) {
  1210. be_cq_notify(adapter, tx_cq->id, true, num_cmpl);
  1211. /* As Tx wrbs have been freed up, wake up netdev queue if
  1212. * it was stopped due to lack of tx wrbs.
  1213. */
  1214. if (netif_queue_stopped(adapter->netdev) &&
  1215. atomic_read(&txq->used) < txq->len / 2) {
  1216. netif_wake_queue(adapter->netdev);
  1217. }
  1218. drvr_stats(adapter)->be_tx_events++;
  1219. drvr_stats(adapter)->be_tx_compl += num_cmpl;
  1220. }
  1221. }
  1222. /* As TX and MCC share the same EQ check for both TX and MCC completions.
  1223. * For TX/MCC we don't honour budget; consume everything
  1224. */
  1225. static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
  1226. {
  1227. struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
  1228. struct be_adapter *adapter =
  1229. container_of(tx_eq, struct be_adapter, tx_eq);
  1230. napi_complete(napi);
  1231. be_process_tx(adapter);
  1232. be_process_mcc(adapter);
  1233. return 1;
  1234. }
  1235. static void be_worker(struct work_struct *work)
  1236. {
  1237. struct be_adapter *adapter =
  1238. container_of(work, struct be_adapter, work.work);
  1239. be_cmd_get_stats(adapter, &adapter->stats.cmd);
  1240. /* Set EQ delay */
  1241. be_rx_eqd_update(adapter);
  1242. be_tx_rate_update(adapter);
  1243. be_rx_rate_update(adapter);
  1244. if (adapter->rx_post_starved) {
  1245. adapter->rx_post_starved = false;
  1246. be_post_rx_frags(adapter);
  1247. }
  1248. schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
  1249. }
  1250. static void be_msix_disable(struct be_adapter *adapter)
  1251. {
  1252. if (adapter->msix_enabled) {
  1253. pci_disable_msix(adapter->pdev);
  1254. adapter->msix_enabled = false;
  1255. }
  1256. }
  1257. static void be_msix_enable(struct be_adapter *adapter)
  1258. {
  1259. int i, status;
  1260. for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
  1261. adapter->msix_entries[i].entry = i;
  1262. status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
  1263. BE_NUM_MSIX_VECTORS);
  1264. if (status == 0)
  1265. adapter->msix_enabled = true;
  1266. return;
  1267. }
  1268. static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
  1269. {
  1270. return adapter->msix_entries[
  1271. be_evt_bit_get(adapter, eq_id)].vector;
  1272. }
  1273. static int be_request_irq(struct be_adapter *adapter,
  1274. struct be_eq_obj *eq_obj,
  1275. void *handler, char *desc)
  1276. {
  1277. struct net_device *netdev = adapter->netdev;
  1278. int vec;
  1279. sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
  1280. vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1281. return request_irq(vec, handler, 0, eq_obj->desc, adapter);
  1282. }
  1283. static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
  1284. {
  1285. int vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1286. free_irq(vec, adapter);
  1287. }
  1288. static int be_msix_register(struct be_adapter *adapter)
  1289. {
  1290. int status;
  1291. status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
  1292. if (status)
  1293. goto err;
  1294. status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
  1295. if (status)
  1296. goto free_tx_irq;
  1297. return 0;
  1298. free_tx_irq:
  1299. be_free_irq(adapter, &adapter->tx_eq);
  1300. err:
  1301. dev_warn(&adapter->pdev->dev,
  1302. "MSIX Request IRQ failed - err %d\n", status);
  1303. pci_disable_msix(adapter->pdev);
  1304. adapter->msix_enabled = false;
  1305. return status;
  1306. }
  1307. static int be_irq_register(struct be_adapter *adapter)
  1308. {
  1309. struct net_device *netdev = adapter->netdev;
  1310. int status;
  1311. if (adapter->msix_enabled) {
  1312. status = be_msix_register(adapter);
  1313. if (status == 0)
  1314. goto done;
  1315. }
  1316. /* INTx */
  1317. netdev->irq = adapter->pdev->irq;
  1318. status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
  1319. adapter);
  1320. if (status) {
  1321. dev_err(&adapter->pdev->dev,
  1322. "INTx request IRQ failed - err %d\n", status);
  1323. return status;
  1324. }
  1325. done:
  1326. adapter->isr_registered = true;
  1327. return 0;
  1328. }
  1329. static void be_irq_unregister(struct be_adapter *adapter)
  1330. {
  1331. struct net_device *netdev = adapter->netdev;
  1332. if (!adapter->isr_registered)
  1333. return;
  1334. /* INTx */
  1335. if (!adapter->msix_enabled) {
  1336. free_irq(netdev->irq, adapter);
  1337. goto done;
  1338. }
  1339. /* MSIx */
  1340. be_free_irq(adapter, &adapter->tx_eq);
  1341. be_free_irq(adapter, &adapter->rx_eq);
  1342. done:
  1343. adapter->isr_registered = false;
  1344. return;
  1345. }
  1346. static int be_open(struct net_device *netdev)
  1347. {
  1348. struct be_adapter *adapter = netdev_priv(netdev);
  1349. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1350. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1351. bool link_up;
  1352. int status;
  1353. u8 mac_speed;
  1354. u16 link_speed;
  1355. /* First time posting */
  1356. be_post_rx_frags(adapter);
  1357. napi_enable(&rx_eq->napi);
  1358. napi_enable(&tx_eq->napi);
  1359. be_irq_register(adapter);
  1360. be_intr_set(adapter, true);
  1361. /* The evt queues are created in unarmed state; arm them */
  1362. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  1363. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  1364. /* Rx compl queue may be in unarmed state; rearm it */
  1365. be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
  1366. status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
  1367. &link_speed);
  1368. if (status)
  1369. goto ret_sts;
  1370. be_link_status_update(adapter, link_up);
  1371. status = be_vid_config(adapter);
  1372. if (status)
  1373. goto ret_sts;
  1374. status = be_cmd_set_flow_control(adapter,
  1375. adapter->tx_fc, adapter->rx_fc);
  1376. if (status)
  1377. goto ret_sts;
  1378. schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
  1379. ret_sts:
  1380. return status;
  1381. }
  1382. static int be_setup_wol(struct be_adapter *adapter, bool enable)
  1383. {
  1384. struct be_dma_mem cmd;
  1385. int status = 0;
  1386. u8 mac[ETH_ALEN];
  1387. memset(mac, 0, ETH_ALEN);
  1388. cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
  1389. cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
  1390. if (cmd.va == NULL)
  1391. return -1;
  1392. memset(cmd.va, 0, cmd.size);
  1393. if (enable) {
  1394. status = pci_write_config_dword(adapter->pdev,
  1395. PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
  1396. if (status) {
  1397. dev_err(&adapter->pdev->dev,
  1398. "Could not enable Wake-on-lan \n");
  1399. pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
  1400. cmd.dma);
  1401. return status;
  1402. }
  1403. status = be_cmd_enable_magic_wol(adapter,
  1404. adapter->netdev->dev_addr, &cmd);
  1405. pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
  1406. pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
  1407. } else {
  1408. status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
  1409. pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
  1410. pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
  1411. }
  1412. pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
  1413. return status;
  1414. }
  1415. static int be_setup(struct be_adapter *adapter)
  1416. {
  1417. struct net_device *netdev = adapter->netdev;
  1418. u32 cap_flags, en_flags;
  1419. int status;
  1420. cap_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
  1421. BE_IF_FLAGS_MCAST_PROMISCUOUS |
  1422. BE_IF_FLAGS_PROMISCUOUS |
  1423. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1424. en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
  1425. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1426. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1427. netdev->dev_addr, false/* pmac_invalid */,
  1428. &adapter->if_handle, &adapter->pmac_id);
  1429. if (status != 0)
  1430. goto do_none;
  1431. status = be_tx_queues_create(adapter);
  1432. if (status != 0)
  1433. goto if_destroy;
  1434. status = be_rx_queues_create(adapter);
  1435. if (status != 0)
  1436. goto tx_qs_destroy;
  1437. status = be_mcc_queues_create(adapter);
  1438. if (status != 0)
  1439. goto rx_qs_destroy;
  1440. adapter->link_speed = -1;
  1441. return 0;
  1442. rx_qs_destroy:
  1443. be_rx_queues_destroy(adapter);
  1444. tx_qs_destroy:
  1445. be_tx_queues_destroy(adapter);
  1446. if_destroy:
  1447. be_cmd_if_destroy(adapter, adapter->if_handle);
  1448. do_none:
  1449. return status;
  1450. }
  1451. static int be_clear(struct be_adapter *adapter)
  1452. {
  1453. be_mcc_queues_destroy(adapter);
  1454. be_rx_queues_destroy(adapter);
  1455. be_tx_queues_destroy(adapter);
  1456. be_cmd_if_destroy(adapter, adapter->if_handle);
  1457. /* tell fw we're done with firing cmds */
  1458. be_cmd_fw_clean(adapter);
  1459. return 0;
  1460. }
  1461. static int be_close(struct net_device *netdev)
  1462. {
  1463. struct be_adapter *adapter = netdev_priv(netdev);
  1464. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1465. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1466. int vec;
  1467. cancel_delayed_work_sync(&adapter->work);
  1468. netif_stop_queue(netdev);
  1469. netif_carrier_off(netdev);
  1470. adapter->link_up = false;
  1471. be_intr_set(adapter, false);
  1472. if (adapter->msix_enabled) {
  1473. vec = be_msix_vec_get(adapter, tx_eq->q.id);
  1474. synchronize_irq(vec);
  1475. vec = be_msix_vec_get(adapter, rx_eq->q.id);
  1476. synchronize_irq(vec);
  1477. } else {
  1478. synchronize_irq(netdev->irq);
  1479. }
  1480. be_irq_unregister(adapter);
  1481. napi_disable(&rx_eq->napi);
  1482. napi_disable(&tx_eq->napi);
  1483. /* Wait for all pending tx completions to arrive so that
  1484. * all tx skbs are freed.
  1485. */
  1486. be_tx_compl_clean(adapter);
  1487. return 0;
  1488. }
  1489. #define FW_FILE_HDR_SIGN "ServerEngines Corp. "
  1490. char flash_cookie[2][16] = {"*** SE FLAS",
  1491. "H DIRECTORY *** "};
  1492. static bool be_flash_redboot(struct be_adapter *adapter,
  1493. const u8 *p, u32 img_start, int image_size,
  1494. int hdr_size)
  1495. {
  1496. u32 crc_offset;
  1497. u8 flashed_crc[4];
  1498. int status;
  1499. crc_offset = hdr_size + img_start + image_size - 4;
  1500. p += crc_offset;
  1501. status = be_cmd_get_flash_crc(adapter, flashed_crc,
  1502. (img_start + image_size - 4));
  1503. if (status) {
  1504. dev_err(&adapter->pdev->dev,
  1505. "could not get crc from flash, not flashing redboot\n");
  1506. return false;
  1507. }
  1508. /*update redboot only if crc does not match*/
  1509. if (!memcmp(flashed_crc, p, 4))
  1510. return false;
  1511. else
  1512. return true;
  1513. }
  1514. static int be_flash_data(struct be_adapter *adapter,
  1515. const struct firmware *fw,
  1516. struct be_dma_mem *flash_cmd, int num_of_images)
  1517. {
  1518. int status = 0, i, filehdr_size = 0;
  1519. u32 total_bytes = 0, flash_op;
  1520. int num_bytes;
  1521. const u8 *p = fw->data;
  1522. struct be_cmd_write_flashrom *req = flash_cmd->va;
  1523. struct flash_comp *pflashcomp;
  1524. struct flash_comp gen3_flash_types[8] = {
  1525. { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
  1526. FLASH_IMAGE_MAX_SIZE_g3},
  1527. { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
  1528. FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
  1529. { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
  1530. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1531. { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
  1532. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1533. { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
  1534. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1535. { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
  1536. FLASH_IMAGE_MAX_SIZE_g3},
  1537. { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
  1538. FLASH_IMAGE_MAX_SIZE_g3},
  1539. { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
  1540. FLASH_IMAGE_MAX_SIZE_g3}
  1541. };
  1542. struct flash_comp gen2_flash_types[8] = {
  1543. { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
  1544. FLASH_IMAGE_MAX_SIZE_g2},
  1545. { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
  1546. FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
  1547. { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
  1548. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1549. { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
  1550. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1551. { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
  1552. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1553. { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
  1554. FLASH_IMAGE_MAX_SIZE_g2},
  1555. { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
  1556. FLASH_IMAGE_MAX_SIZE_g2},
  1557. { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
  1558. FLASH_IMAGE_MAX_SIZE_g2}
  1559. };
  1560. if (adapter->generation == BE_GEN3) {
  1561. pflashcomp = gen3_flash_types;
  1562. filehdr_size = sizeof(struct flash_file_hdr_g3);
  1563. } else {
  1564. pflashcomp = gen2_flash_types;
  1565. filehdr_size = sizeof(struct flash_file_hdr_g2);
  1566. }
  1567. for (i = 0; i < 8; i++) {
  1568. if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
  1569. (!be_flash_redboot(adapter, fw->data,
  1570. pflashcomp[i].offset, pflashcomp[i].size,
  1571. filehdr_size)))
  1572. continue;
  1573. p = fw->data;
  1574. p += filehdr_size + pflashcomp[i].offset
  1575. + (num_of_images * sizeof(struct image_hdr));
  1576. if (p + pflashcomp[i].size > fw->data + fw->size)
  1577. return -1;
  1578. total_bytes = pflashcomp[i].size;
  1579. while (total_bytes) {
  1580. if (total_bytes > 32*1024)
  1581. num_bytes = 32*1024;
  1582. else
  1583. num_bytes = total_bytes;
  1584. total_bytes -= num_bytes;
  1585. if (!total_bytes)
  1586. flash_op = FLASHROM_OPER_FLASH;
  1587. else
  1588. flash_op = FLASHROM_OPER_SAVE;
  1589. memcpy(req->params.data_buf, p, num_bytes);
  1590. p += num_bytes;
  1591. status = be_cmd_write_flashrom(adapter, flash_cmd,
  1592. pflashcomp[i].optype, flash_op, num_bytes);
  1593. if (status) {
  1594. dev_err(&adapter->pdev->dev,
  1595. "cmd to write to flash rom failed.\n");
  1596. return -1;
  1597. }
  1598. yield();
  1599. }
  1600. }
  1601. return 0;
  1602. }
  1603. static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
  1604. {
  1605. if (fhdr == NULL)
  1606. return 0;
  1607. if (fhdr->build[0] == '3')
  1608. return BE_GEN3;
  1609. else if (fhdr->build[0] == '2')
  1610. return BE_GEN2;
  1611. else
  1612. return 0;
  1613. }
  1614. int be_load_fw(struct be_adapter *adapter, u8 *func)
  1615. {
  1616. char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
  1617. const struct firmware *fw;
  1618. struct flash_file_hdr_g2 *fhdr;
  1619. struct flash_file_hdr_g3 *fhdr3;
  1620. struct image_hdr *img_hdr_ptr = NULL;
  1621. struct be_dma_mem flash_cmd;
  1622. int status, i = 0;
  1623. const u8 *p;
  1624. char fw_ver[FW_VER_LEN];
  1625. char fw_cfg;
  1626. status = be_cmd_get_fw_ver(adapter, fw_ver);
  1627. if (status)
  1628. return status;
  1629. fw_cfg = *(fw_ver + 2);
  1630. if (fw_cfg == '0')
  1631. fw_cfg = '1';
  1632. strcpy(fw_file, func);
  1633. status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
  1634. if (status)
  1635. goto fw_exit;
  1636. p = fw->data;
  1637. fhdr = (struct flash_file_hdr_g2 *) p;
  1638. dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
  1639. flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
  1640. flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
  1641. &flash_cmd.dma);
  1642. if (!flash_cmd.va) {
  1643. status = -ENOMEM;
  1644. dev_err(&adapter->pdev->dev,
  1645. "Memory allocation failure while flashing\n");
  1646. goto fw_exit;
  1647. }
  1648. if ((adapter->generation == BE_GEN3) &&
  1649. (get_ufigen_type(fhdr) == BE_GEN3)) {
  1650. fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
  1651. for (i = 0; i < fhdr3->num_imgs; i++) {
  1652. img_hdr_ptr = (struct image_hdr *) (fw->data +
  1653. (sizeof(struct flash_file_hdr_g3) +
  1654. i * sizeof(struct image_hdr)));
  1655. if (img_hdr_ptr->imageid == 1) {
  1656. status = be_flash_data(adapter, fw,
  1657. &flash_cmd, fhdr3->num_imgs);
  1658. }
  1659. }
  1660. } else if ((adapter->generation == BE_GEN2) &&
  1661. (get_ufigen_type(fhdr) == BE_GEN2)) {
  1662. status = be_flash_data(adapter, fw, &flash_cmd, 0);
  1663. } else {
  1664. dev_err(&adapter->pdev->dev,
  1665. "UFI and Interface are not compatible for flashing\n");
  1666. status = -1;
  1667. }
  1668. pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
  1669. flash_cmd.dma);
  1670. if (status) {
  1671. dev_err(&adapter->pdev->dev, "Firmware load error\n");
  1672. goto fw_exit;
  1673. }
  1674. dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
  1675. fw_exit:
  1676. release_firmware(fw);
  1677. return status;
  1678. }
  1679. static struct net_device_ops be_netdev_ops = {
  1680. .ndo_open = be_open,
  1681. .ndo_stop = be_close,
  1682. .ndo_start_xmit = be_xmit,
  1683. .ndo_get_stats = be_get_stats,
  1684. .ndo_set_rx_mode = be_set_multicast_list,
  1685. .ndo_set_mac_address = be_mac_addr_set,
  1686. .ndo_change_mtu = be_change_mtu,
  1687. .ndo_validate_addr = eth_validate_addr,
  1688. .ndo_vlan_rx_register = be_vlan_register,
  1689. .ndo_vlan_rx_add_vid = be_vlan_add_vid,
  1690. .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
  1691. };
  1692. static void be_netdev_init(struct net_device *netdev)
  1693. {
  1694. struct be_adapter *adapter = netdev_priv(netdev);
  1695. netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
  1696. NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
  1697. NETIF_F_GRO;
  1698. netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
  1699. netdev->flags |= IFF_MULTICAST;
  1700. adapter->rx_csum = true;
  1701. /* Default settings for Rx and Tx flow control */
  1702. adapter->rx_fc = true;
  1703. adapter->tx_fc = true;
  1704. netif_set_gso_max_size(netdev, 65535);
  1705. BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
  1706. SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
  1707. netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
  1708. BE_NAPI_WEIGHT);
  1709. netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
  1710. BE_NAPI_WEIGHT);
  1711. netif_carrier_off(netdev);
  1712. netif_stop_queue(netdev);
  1713. }
  1714. static void be_unmap_pci_bars(struct be_adapter *adapter)
  1715. {
  1716. if (adapter->csr)
  1717. iounmap(adapter->csr);
  1718. if (adapter->db)
  1719. iounmap(adapter->db);
  1720. if (adapter->pcicfg)
  1721. iounmap(adapter->pcicfg);
  1722. }
  1723. static int be_map_pci_bars(struct be_adapter *adapter)
  1724. {
  1725. u8 __iomem *addr;
  1726. int pcicfg_reg;
  1727. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
  1728. pci_resource_len(adapter->pdev, 2));
  1729. if (addr == NULL)
  1730. return -ENOMEM;
  1731. adapter->csr = addr;
  1732. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4),
  1733. 128 * 1024);
  1734. if (addr == NULL)
  1735. goto pci_map_err;
  1736. adapter->db = addr;
  1737. if (adapter->generation == BE_GEN2)
  1738. pcicfg_reg = 1;
  1739. else
  1740. pcicfg_reg = 0;
  1741. addr = ioremap_nocache(pci_resource_start(adapter->pdev, pcicfg_reg),
  1742. pci_resource_len(adapter->pdev, pcicfg_reg));
  1743. if (addr == NULL)
  1744. goto pci_map_err;
  1745. adapter->pcicfg = addr;
  1746. return 0;
  1747. pci_map_err:
  1748. be_unmap_pci_bars(adapter);
  1749. return -ENOMEM;
  1750. }
  1751. static void be_ctrl_cleanup(struct be_adapter *adapter)
  1752. {
  1753. struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
  1754. be_unmap_pci_bars(adapter);
  1755. if (mem->va)
  1756. pci_free_consistent(adapter->pdev, mem->size,
  1757. mem->va, mem->dma);
  1758. mem = &adapter->mc_cmd_mem;
  1759. if (mem->va)
  1760. pci_free_consistent(adapter->pdev, mem->size,
  1761. mem->va, mem->dma);
  1762. }
  1763. static int be_ctrl_init(struct be_adapter *adapter)
  1764. {
  1765. struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
  1766. struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
  1767. struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
  1768. int status;
  1769. status = be_map_pci_bars(adapter);
  1770. if (status)
  1771. goto done;
  1772. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  1773. mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
  1774. mbox_mem_alloc->size, &mbox_mem_alloc->dma);
  1775. if (!mbox_mem_alloc->va) {
  1776. status = -ENOMEM;
  1777. goto unmap_pci_bars;
  1778. }
  1779. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  1780. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  1781. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  1782. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  1783. mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
  1784. mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
  1785. &mc_cmd_mem->dma);
  1786. if (mc_cmd_mem->va == NULL) {
  1787. status = -ENOMEM;
  1788. goto free_mbox;
  1789. }
  1790. memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
  1791. spin_lock_init(&adapter->mbox_lock);
  1792. spin_lock_init(&adapter->mcc_lock);
  1793. spin_lock_init(&adapter->mcc_cq_lock);
  1794. return 0;
  1795. free_mbox:
  1796. pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
  1797. mbox_mem_alloc->va, mbox_mem_alloc->dma);
  1798. unmap_pci_bars:
  1799. be_unmap_pci_bars(adapter);
  1800. done:
  1801. return status;
  1802. }
  1803. static void be_stats_cleanup(struct be_adapter *adapter)
  1804. {
  1805. struct be_stats_obj *stats = &adapter->stats;
  1806. struct be_dma_mem *cmd = &stats->cmd;
  1807. if (cmd->va)
  1808. pci_free_consistent(adapter->pdev, cmd->size,
  1809. cmd->va, cmd->dma);
  1810. }
  1811. static int be_stats_init(struct be_adapter *adapter)
  1812. {
  1813. struct be_stats_obj *stats = &adapter->stats;
  1814. struct be_dma_mem *cmd = &stats->cmd;
  1815. cmd->size = sizeof(struct be_cmd_req_get_stats);
  1816. cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
  1817. if (cmd->va == NULL)
  1818. return -1;
  1819. memset(cmd->va, 0, cmd->size);
  1820. return 0;
  1821. }
  1822. static void __devexit be_remove(struct pci_dev *pdev)
  1823. {
  1824. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1825. if (!adapter)
  1826. return;
  1827. unregister_netdev(adapter->netdev);
  1828. be_clear(adapter);
  1829. be_stats_cleanup(adapter);
  1830. be_ctrl_cleanup(adapter);
  1831. be_msix_disable(adapter);
  1832. pci_set_drvdata(pdev, NULL);
  1833. pci_release_regions(pdev);
  1834. pci_disable_device(pdev);
  1835. free_netdev(adapter->netdev);
  1836. }
  1837. static int be_get_config(struct be_adapter *adapter)
  1838. {
  1839. int status;
  1840. u8 mac[ETH_ALEN];
  1841. status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
  1842. if (status)
  1843. return status;
  1844. status = be_cmd_query_fw_cfg(adapter,
  1845. &adapter->port_num, &adapter->cap);
  1846. if (status)
  1847. return status;
  1848. memset(mac, 0, ETH_ALEN);
  1849. status = be_cmd_mac_addr_query(adapter, mac,
  1850. MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
  1851. if (status)
  1852. return status;
  1853. if (!is_valid_ether_addr(mac))
  1854. return -EADDRNOTAVAIL;
  1855. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  1856. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  1857. return 0;
  1858. }
  1859. static int __devinit be_probe(struct pci_dev *pdev,
  1860. const struct pci_device_id *pdev_id)
  1861. {
  1862. int status = 0;
  1863. struct be_adapter *adapter;
  1864. struct net_device *netdev;
  1865. status = pci_enable_device(pdev);
  1866. if (status)
  1867. goto do_none;
  1868. status = pci_request_regions(pdev, DRV_NAME);
  1869. if (status)
  1870. goto disable_dev;
  1871. pci_set_master(pdev);
  1872. netdev = alloc_etherdev(sizeof(struct be_adapter));
  1873. if (netdev == NULL) {
  1874. status = -ENOMEM;
  1875. goto rel_reg;
  1876. }
  1877. adapter = netdev_priv(netdev);
  1878. switch (pdev->device) {
  1879. case BE_DEVICE_ID1:
  1880. case OC_DEVICE_ID1:
  1881. adapter->generation = BE_GEN2;
  1882. break;
  1883. case BE_DEVICE_ID2:
  1884. case OC_DEVICE_ID2:
  1885. adapter->generation = BE_GEN3;
  1886. break;
  1887. default:
  1888. adapter->generation = 0;
  1889. }
  1890. adapter->pdev = pdev;
  1891. pci_set_drvdata(pdev, adapter);
  1892. adapter->netdev = netdev;
  1893. be_netdev_init(netdev);
  1894. SET_NETDEV_DEV(netdev, &pdev->dev);
  1895. be_msix_enable(adapter);
  1896. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  1897. if (!status) {
  1898. netdev->features |= NETIF_F_HIGHDMA;
  1899. } else {
  1900. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1901. if (status) {
  1902. dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
  1903. goto free_netdev;
  1904. }
  1905. }
  1906. status = be_ctrl_init(adapter);
  1907. if (status)
  1908. goto free_netdev;
  1909. /* sync up with fw's ready state */
  1910. status = be_cmd_POST(adapter);
  1911. if (status)
  1912. goto ctrl_clean;
  1913. /* tell fw we're ready to fire cmds */
  1914. status = be_cmd_fw_init(adapter);
  1915. if (status)
  1916. goto ctrl_clean;
  1917. status = be_cmd_reset_function(adapter);
  1918. if (status)
  1919. goto ctrl_clean;
  1920. status = be_stats_init(adapter);
  1921. if (status)
  1922. goto ctrl_clean;
  1923. status = be_get_config(adapter);
  1924. if (status)
  1925. goto stats_clean;
  1926. INIT_DELAYED_WORK(&adapter->work, be_worker);
  1927. status = be_setup(adapter);
  1928. if (status)
  1929. goto stats_clean;
  1930. status = register_netdev(netdev);
  1931. if (status != 0)
  1932. goto unsetup;
  1933. dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
  1934. return 0;
  1935. unsetup:
  1936. be_clear(adapter);
  1937. stats_clean:
  1938. be_stats_cleanup(adapter);
  1939. ctrl_clean:
  1940. be_ctrl_cleanup(adapter);
  1941. free_netdev:
  1942. be_msix_disable(adapter);
  1943. free_netdev(adapter->netdev);
  1944. pci_set_drvdata(pdev, NULL);
  1945. rel_reg:
  1946. pci_release_regions(pdev);
  1947. disable_dev:
  1948. pci_disable_device(pdev);
  1949. do_none:
  1950. dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
  1951. return status;
  1952. }
  1953. static int be_suspend(struct pci_dev *pdev, pm_message_t state)
  1954. {
  1955. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1956. struct net_device *netdev = adapter->netdev;
  1957. if (adapter->wol)
  1958. be_setup_wol(adapter, true);
  1959. netif_device_detach(netdev);
  1960. if (netif_running(netdev)) {
  1961. rtnl_lock();
  1962. be_close(netdev);
  1963. rtnl_unlock();
  1964. }
  1965. be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
  1966. be_clear(adapter);
  1967. pci_save_state(pdev);
  1968. pci_disable_device(pdev);
  1969. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  1970. return 0;
  1971. }
  1972. static int be_resume(struct pci_dev *pdev)
  1973. {
  1974. int status = 0;
  1975. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1976. struct net_device *netdev = adapter->netdev;
  1977. netif_device_detach(netdev);
  1978. status = pci_enable_device(pdev);
  1979. if (status)
  1980. return status;
  1981. pci_set_power_state(pdev, 0);
  1982. pci_restore_state(pdev);
  1983. /* tell fw we're ready to fire cmds */
  1984. status = be_cmd_fw_init(adapter);
  1985. if (status)
  1986. return status;
  1987. be_setup(adapter);
  1988. if (netif_running(netdev)) {
  1989. rtnl_lock();
  1990. be_open(netdev);
  1991. rtnl_unlock();
  1992. }
  1993. netif_device_attach(netdev);
  1994. if (adapter->wol)
  1995. be_setup_wol(adapter, false);
  1996. return 0;
  1997. }
  1998. static struct pci_driver be_driver = {
  1999. .name = DRV_NAME,
  2000. .id_table = be_dev_ids,
  2001. .probe = be_probe,
  2002. .remove = be_remove,
  2003. .suspend = be_suspend,
  2004. .resume = be_resume
  2005. };
  2006. static int __init be_init_module(void)
  2007. {
  2008. if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
  2009. rx_frag_size != 2048) {
  2010. printk(KERN_WARNING DRV_NAME
  2011. " : Module param rx_frag_size must be 2048/4096/8192."
  2012. " Using 2048\n");
  2013. rx_frag_size = 2048;
  2014. }
  2015. return pci_register_driver(&be_driver);
  2016. }
  2017. module_init(be_init_module);
  2018. static void __exit be_exit_module(void)
  2019. {
  2020. pci_unregister_driver(&be_driver);
  2021. }
  2022. module_exit(be_exit_module);