feature.c 80 KB

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  1. /*
  2. * arch/ppc/platforms/pmac_feature.c
  3. *
  4. * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
  5. * Ben. Herrenschmidt (benh@kernel.crashing.org)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. *
  12. * TODO:
  13. *
  14. * - Replace mdelay with some schedule loop if possible
  15. * - Shorten some obfuscated delays on some routines (like modem
  16. * power)
  17. * - Refcount some clocks (see darwin)
  18. * - Split split split...
  19. *
  20. */
  21. #include <linux/config.h>
  22. #include <linux/types.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/kernel.h>
  26. #include <linux/sched.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/adb.h>
  29. #include <linux/pmu.h>
  30. #include <linux/ioport.h>
  31. #include <linux/pci.h>
  32. #include <asm/sections.h>
  33. #include <asm/errno.h>
  34. #include <asm/ohare.h>
  35. #include <asm/heathrow.h>
  36. #include <asm/keylargo.h>
  37. #include <asm/uninorth.h>
  38. #include <asm/io.h>
  39. #include <asm/prom.h>
  40. #include <asm/machdep.h>
  41. #include <asm/pmac_feature.h>
  42. #include <asm/dbdma.h>
  43. #include <asm/pci-bridge.h>
  44. #include <asm/pmac_low_i2c.h>
  45. #undef DEBUG_FEATURE
  46. #ifdef DEBUG_FEATURE
  47. #define DBG(fmt...) printk(KERN_DEBUG fmt)
  48. #else
  49. #define DBG(fmt...)
  50. #endif
  51. #ifdef CONFIG_6xx
  52. extern int powersave_lowspeed;
  53. #endif
  54. extern int powersave_nap;
  55. extern struct device_node *k2_skiplist[2];
  56. /*
  57. * We use a single global lock to protect accesses. Each driver has
  58. * to take care of its own locking
  59. */
  60. DEFINE_SPINLOCK(feature_lock);
  61. #define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
  62. #define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
  63. /*
  64. * Instance of some macio stuffs
  65. */
  66. struct macio_chip macio_chips[MAX_MACIO_CHIPS];
  67. struct macio_chip *macio_find(struct device_node *child, int type)
  68. {
  69. while(child) {
  70. int i;
  71. for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
  72. if (child == macio_chips[i].of_node &&
  73. (!type || macio_chips[i].type == type))
  74. return &macio_chips[i];
  75. child = child->parent;
  76. }
  77. return NULL;
  78. }
  79. EXPORT_SYMBOL_GPL(macio_find);
  80. static const char *macio_names[] =
  81. {
  82. "Unknown",
  83. "Grand Central",
  84. "OHare",
  85. "OHareII",
  86. "Heathrow",
  87. "Gatwick",
  88. "Paddington",
  89. "Keylargo",
  90. "Pangea",
  91. "Intrepid",
  92. "K2",
  93. "Shasta",
  94. };
  95. struct device_node *uninorth_node;
  96. u32 __iomem *uninorth_base;
  97. static u32 uninorth_rev;
  98. static int uninorth_maj;
  99. static void __iomem *u3_ht_base;
  100. /*
  101. * For each motherboard family, we have a table of functions pointers
  102. * that handle the various features.
  103. */
  104. typedef long (*feature_call)(struct device_node *node, long param, long value);
  105. struct feature_table_entry {
  106. unsigned int selector;
  107. feature_call function;
  108. };
  109. struct pmac_mb_def
  110. {
  111. const char* model_string;
  112. const char* model_name;
  113. int model_id;
  114. struct feature_table_entry* features;
  115. unsigned long board_flags;
  116. };
  117. static struct pmac_mb_def pmac_mb;
  118. /*
  119. * Here are the chip specific feature functions
  120. */
  121. static inline int simple_feature_tweak(struct device_node *node, int type,
  122. int reg, u32 mask, int value)
  123. {
  124. struct macio_chip* macio;
  125. unsigned long flags;
  126. macio = macio_find(node, type);
  127. if (!macio)
  128. return -ENODEV;
  129. LOCK(flags);
  130. if (value)
  131. MACIO_BIS(reg, mask);
  132. else
  133. MACIO_BIC(reg, mask);
  134. (void)MACIO_IN32(reg);
  135. UNLOCK(flags);
  136. return 0;
  137. }
  138. #ifndef CONFIG_POWER4
  139. static long ohare_htw_scc_enable(struct device_node *node, long param,
  140. long value)
  141. {
  142. struct macio_chip* macio;
  143. unsigned long chan_mask;
  144. unsigned long fcr;
  145. unsigned long flags;
  146. int htw, trans;
  147. unsigned long rmask;
  148. macio = macio_find(node, 0);
  149. if (!macio)
  150. return -ENODEV;
  151. if (!strcmp(node->name, "ch-a"))
  152. chan_mask = MACIO_FLAG_SCCA_ON;
  153. else if (!strcmp(node->name, "ch-b"))
  154. chan_mask = MACIO_FLAG_SCCB_ON;
  155. else
  156. return -ENODEV;
  157. htw = (macio->type == macio_heathrow || macio->type == macio_paddington
  158. || macio->type == macio_gatwick);
  159. /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
  160. trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
  161. pmac_mb.model_id != PMAC_TYPE_YIKES);
  162. if (value) {
  163. #ifdef CONFIG_ADB_PMU
  164. if ((param & 0xfff) == PMAC_SCC_IRDA)
  165. pmu_enable_irled(1);
  166. #endif /* CONFIG_ADB_PMU */
  167. LOCK(flags);
  168. fcr = MACIO_IN32(OHARE_FCR);
  169. /* Check if scc cell need enabling */
  170. if (!(fcr & OH_SCC_ENABLE)) {
  171. fcr |= OH_SCC_ENABLE;
  172. if (htw) {
  173. /* Side effect: this will also power up the
  174. * modem, but it's too messy to figure out on which
  175. * ports this controls the tranceiver and on which
  176. * it controls the modem
  177. */
  178. if (trans)
  179. fcr &= ~HRW_SCC_TRANS_EN_N;
  180. MACIO_OUT32(OHARE_FCR, fcr);
  181. fcr |= (rmask = HRW_RESET_SCC);
  182. MACIO_OUT32(OHARE_FCR, fcr);
  183. } else {
  184. fcr |= (rmask = OH_SCC_RESET);
  185. MACIO_OUT32(OHARE_FCR, fcr);
  186. }
  187. UNLOCK(flags);
  188. (void)MACIO_IN32(OHARE_FCR);
  189. mdelay(15);
  190. LOCK(flags);
  191. fcr &= ~rmask;
  192. MACIO_OUT32(OHARE_FCR, fcr);
  193. }
  194. if (chan_mask & MACIO_FLAG_SCCA_ON)
  195. fcr |= OH_SCCA_IO;
  196. if (chan_mask & MACIO_FLAG_SCCB_ON)
  197. fcr |= OH_SCCB_IO;
  198. MACIO_OUT32(OHARE_FCR, fcr);
  199. macio->flags |= chan_mask;
  200. UNLOCK(flags);
  201. if (param & PMAC_SCC_FLAG_XMON)
  202. macio->flags |= MACIO_FLAG_SCC_LOCKED;
  203. } else {
  204. if (macio->flags & MACIO_FLAG_SCC_LOCKED)
  205. return -EPERM;
  206. LOCK(flags);
  207. fcr = MACIO_IN32(OHARE_FCR);
  208. if (chan_mask & MACIO_FLAG_SCCA_ON)
  209. fcr &= ~OH_SCCA_IO;
  210. if (chan_mask & MACIO_FLAG_SCCB_ON)
  211. fcr &= ~OH_SCCB_IO;
  212. MACIO_OUT32(OHARE_FCR, fcr);
  213. if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
  214. fcr &= ~OH_SCC_ENABLE;
  215. if (htw && trans)
  216. fcr |= HRW_SCC_TRANS_EN_N;
  217. MACIO_OUT32(OHARE_FCR, fcr);
  218. }
  219. macio->flags &= ~(chan_mask);
  220. UNLOCK(flags);
  221. mdelay(10);
  222. #ifdef CONFIG_ADB_PMU
  223. if ((param & 0xfff) == PMAC_SCC_IRDA)
  224. pmu_enable_irled(0);
  225. #endif /* CONFIG_ADB_PMU */
  226. }
  227. return 0;
  228. }
  229. static long ohare_floppy_enable(struct device_node *node, long param,
  230. long value)
  231. {
  232. return simple_feature_tweak(node, macio_ohare,
  233. OHARE_FCR, OH_FLOPPY_ENABLE, value);
  234. }
  235. static long ohare_mesh_enable(struct device_node *node, long param, long value)
  236. {
  237. return simple_feature_tweak(node, macio_ohare,
  238. OHARE_FCR, OH_MESH_ENABLE, value);
  239. }
  240. static long ohare_ide_enable(struct device_node *node, long param, long value)
  241. {
  242. switch(param) {
  243. case 0:
  244. /* For some reason, setting the bit in set_initial_features()
  245. * doesn't stick. I'm still investigating... --BenH.
  246. */
  247. if (value)
  248. simple_feature_tweak(node, macio_ohare,
  249. OHARE_FCR, OH_IOBUS_ENABLE, 1);
  250. return simple_feature_tweak(node, macio_ohare,
  251. OHARE_FCR, OH_IDE0_ENABLE, value);
  252. case 1:
  253. return simple_feature_tweak(node, macio_ohare,
  254. OHARE_FCR, OH_BAY_IDE_ENABLE, value);
  255. default:
  256. return -ENODEV;
  257. }
  258. }
  259. static long ohare_ide_reset(struct device_node *node, long param, long value)
  260. {
  261. switch(param) {
  262. case 0:
  263. return simple_feature_tweak(node, macio_ohare,
  264. OHARE_FCR, OH_IDE0_RESET_N, !value);
  265. case 1:
  266. return simple_feature_tweak(node, macio_ohare,
  267. OHARE_FCR, OH_IDE1_RESET_N, !value);
  268. default:
  269. return -ENODEV;
  270. }
  271. }
  272. static long ohare_sleep_state(struct device_node *node, long param, long value)
  273. {
  274. struct macio_chip* macio = &macio_chips[0];
  275. if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
  276. return -EPERM;
  277. if (value == 1) {
  278. MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
  279. } else if (value == 0) {
  280. MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
  281. }
  282. return 0;
  283. }
  284. static long heathrow_modem_enable(struct device_node *node, long param,
  285. long value)
  286. {
  287. struct macio_chip* macio;
  288. u8 gpio;
  289. unsigned long flags;
  290. macio = macio_find(node, macio_unknown);
  291. if (!macio)
  292. return -ENODEV;
  293. gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
  294. if (!value) {
  295. LOCK(flags);
  296. MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
  297. UNLOCK(flags);
  298. (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
  299. mdelay(250);
  300. }
  301. if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
  302. pmac_mb.model_id != PMAC_TYPE_YIKES) {
  303. LOCK(flags);
  304. if (value)
  305. MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
  306. else
  307. MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
  308. UNLOCK(flags);
  309. (void)MACIO_IN32(HEATHROW_FCR);
  310. mdelay(250);
  311. }
  312. if (value) {
  313. LOCK(flags);
  314. MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
  315. (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
  316. UNLOCK(flags); mdelay(250); LOCK(flags);
  317. MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
  318. (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
  319. UNLOCK(flags); mdelay(250); LOCK(flags);
  320. MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
  321. (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
  322. UNLOCK(flags); mdelay(250);
  323. }
  324. return 0;
  325. }
  326. static long heathrow_floppy_enable(struct device_node *node, long param,
  327. long value)
  328. {
  329. return simple_feature_tweak(node, macio_unknown,
  330. HEATHROW_FCR,
  331. HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
  332. value);
  333. }
  334. static long heathrow_mesh_enable(struct device_node *node, long param,
  335. long value)
  336. {
  337. struct macio_chip* macio;
  338. unsigned long flags;
  339. macio = macio_find(node, macio_unknown);
  340. if (!macio)
  341. return -ENODEV;
  342. LOCK(flags);
  343. /* Set clear mesh cell enable */
  344. if (value)
  345. MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
  346. else
  347. MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
  348. (void)MACIO_IN32(HEATHROW_FCR);
  349. udelay(10);
  350. /* Set/Clear termination power */
  351. if (value)
  352. MACIO_BIC(HEATHROW_MBCR, 0x04000000);
  353. else
  354. MACIO_BIS(HEATHROW_MBCR, 0x04000000);
  355. (void)MACIO_IN32(HEATHROW_MBCR);
  356. udelay(10);
  357. UNLOCK(flags);
  358. return 0;
  359. }
  360. static long heathrow_ide_enable(struct device_node *node, long param,
  361. long value)
  362. {
  363. switch(param) {
  364. case 0:
  365. return simple_feature_tweak(node, macio_unknown,
  366. HEATHROW_FCR, HRW_IDE0_ENABLE, value);
  367. case 1:
  368. return simple_feature_tweak(node, macio_unknown,
  369. HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
  370. default:
  371. return -ENODEV;
  372. }
  373. }
  374. static long heathrow_ide_reset(struct device_node *node, long param,
  375. long value)
  376. {
  377. switch(param) {
  378. case 0:
  379. return simple_feature_tweak(node, macio_unknown,
  380. HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
  381. case 1:
  382. return simple_feature_tweak(node, macio_unknown,
  383. HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
  384. default:
  385. return -ENODEV;
  386. }
  387. }
  388. static long heathrow_bmac_enable(struct device_node *node, long param,
  389. long value)
  390. {
  391. struct macio_chip* macio;
  392. unsigned long flags;
  393. macio = macio_find(node, 0);
  394. if (!macio)
  395. return -ENODEV;
  396. if (value) {
  397. LOCK(flags);
  398. MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
  399. MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
  400. UNLOCK(flags);
  401. (void)MACIO_IN32(HEATHROW_FCR);
  402. mdelay(10);
  403. LOCK(flags);
  404. MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
  405. UNLOCK(flags);
  406. (void)MACIO_IN32(HEATHROW_FCR);
  407. mdelay(10);
  408. } else {
  409. LOCK(flags);
  410. MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
  411. UNLOCK(flags);
  412. }
  413. return 0;
  414. }
  415. static long heathrow_sound_enable(struct device_node *node, long param,
  416. long value)
  417. {
  418. struct macio_chip* macio;
  419. unsigned long flags;
  420. /* B&W G3 and Yikes don't support that properly (the
  421. * sound appear to never come back after beeing shut down).
  422. */
  423. if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
  424. pmac_mb.model_id == PMAC_TYPE_YIKES)
  425. return 0;
  426. macio = macio_find(node, 0);
  427. if (!macio)
  428. return -ENODEV;
  429. if (value) {
  430. LOCK(flags);
  431. MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
  432. MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
  433. UNLOCK(flags);
  434. (void)MACIO_IN32(HEATHROW_FCR);
  435. } else {
  436. LOCK(flags);
  437. MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
  438. MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
  439. UNLOCK(flags);
  440. }
  441. return 0;
  442. }
  443. static u32 save_fcr[6];
  444. static u32 save_mbcr;
  445. static u32 save_gpio_levels[2];
  446. static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
  447. static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
  448. static u32 save_unin_clock_ctl;
  449. static struct dbdma_regs save_dbdma[13];
  450. static struct dbdma_regs save_alt_dbdma[13];
  451. static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save)
  452. {
  453. int i;
  454. /* Save state & config of DBDMA channels */
  455. for (i = 0; i < 13; i++) {
  456. volatile struct dbdma_regs __iomem * chan = (void __iomem *)
  457. (macio->base + ((0x8000+i*0x100)>>2));
  458. save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
  459. save[i].cmdptr = in_le32(&chan->cmdptr);
  460. save[i].intr_sel = in_le32(&chan->intr_sel);
  461. save[i].br_sel = in_le32(&chan->br_sel);
  462. save[i].wait_sel = in_le32(&chan->wait_sel);
  463. }
  464. }
  465. static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save)
  466. {
  467. int i;
  468. /* Save state & config of DBDMA channels */
  469. for (i = 0; i < 13; i++) {
  470. volatile struct dbdma_regs __iomem * chan = (void __iomem *)
  471. (macio->base + ((0x8000+i*0x100)>>2));
  472. out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
  473. while (in_le32(&chan->status) & ACTIVE)
  474. mb();
  475. out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
  476. out_le32(&chan->cmdptr, save[i].cmdptr);
  477. out_le32(&chan->intr_sel, save[i].intr_sel);
  478. out_le32(&chan->br_sel, save[i].br_sel);
  479. out_le32(&chan->wait_sel, save[i].wait_sel);
  480. }
  481. }
  482. static void heathrow_sleep(struct macio_chip *macio, int secondary)
  483. {
  484. if (secondary) {
  485. dbdma_save(macio, save_alt_dbdma);
  486. save_fcr[2] = MACIO_IN32(0x38);
  487. save_fcr[3] = MACIO_IN32(0x3c);
  488. } else {
  489. dbdma_save(macio, save_dbdma);
  490. save_fcr[0] = MACIO_IN32(0x38);
  491. save_fcr[1] = MACIO_IN32(0x3c);
  492. save_mbcr = MACIO_IN32(0x34);
  493. /* Make sure sound is shut down */
  494. MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
  495. MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
  496. /* This seems to be necessary as well or the fan
  497. * keeps coming up and battery drains fast */
  498. MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
  499. MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
  500. /* Make sure eth is down even if module or sleep
  501. * won't work properly */
  502. MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
  503. }
  504. /* Make sure modem is shut down */
  505. MACIO_OUT8(HRW_GPIO_MODEM_RESET,
  506. MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
  507. MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
  508. MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
  509. /* Let things settle */
  510. (void)MACIO_IN32(HEATHROW_FCR);
  511. }
  512. static void heathrow_wakeup(struct macio_chip *macio, int secondary)
  513. {
  514. if (secondary) {
  515. MACIO_OUT32(0x38, save_fcr[2]);
  516. (void)MACIO_IN32(0x38);
  517. mdelay(1);
  518. MACIO_OUT32(0x3c, save_fcr[3]);
  519. (void)MACIO_IN32(0x38);
  520. mdelay(10);
  521. dbdma_restore(macio, save_alt_dbdma);
  522. } else {
  523. MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
  524. (void)MACIO_IN32(0x38);
  525. mdelay(1);
  526. MACIO_OUT32(0x3c, save_fcr[1]);
  527. (void)MACIO_IN32(0x38);
  528. mdelay(1);
  529. MACIO_OUT32(0x34, save_mbcr);
  530. (void)MACIO_IN32(0x38);
  531. mdelay(10);
  532. dbdma_restore(macio, save_dbdma);
  533. }
  534. }
  535. static long heathrow_sleep_state(struct device_node *node, long param,
  536. long value)
  537. {
  538. if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
  539. return -EPERM;
  540. if (value == 1) {
  541. if (macio_chips[1].type == macio_gatwick)
  542. heathrow_sleep(&macio_chips[0], 1);
  543. heathrow_sleep(&macio_chips[0], 0);
  544. } else if (value == 0) {
  545. heathrow_wakeup(&macio_chips[0], 0);
  546. if (macio_chips[1].type == macio_gatwick)
  547. heathrow_wakeup(&macio_chips[0], 1);
  548. }
  549. return 0;
  550. }
  551. static long core99_scc_enable(struct device_node *node, long param, long value)
  552. {
  553. struct macio_chip* macio;
  554. unsigned long flags;
  555. unsigned long chan_mask;
  556. u32 fcr;
  557. macio = macio_find(node, 0);
  558. if (!macio)
  559. return -ENODEV;
  560. if (!strcmp(node->name, "ch-a"))
  561. chan_mask = MACIO_FLAG_SCCA_ON;
  562. else if (!strcmp(node->name, "ch-b"))
  563. chan_mask = MACIO_FLAG_SCCB_ON;
  564. else
  565. return -ENODEV;
  566. if (value) {
  567. int need_reset_scc = 0;
  568. int need_reset_irda = 0;
  569. LOCK(flags);
  570. fcr = MACIO_IN32(KEYLARGO_FCR0);
  571. /* Check if scc cell need enabling */
  572. if (!(fcr & KL0_SCC_CELL_ENABLE)) {
  573. fcr |= KL0_SCC_CELL_ENABLE;
  574. need_reset_scc = 1;
  575. }
  576. if (chan_mask & MACIO_FLAG_SCCA_ON) {
  577. fcr |= KL0_SCCA_ENABLE;
  578. /* Don't enable line drivers for I2S modem */
  579. if ((param & 0xfff) == PMAC_SCC_I2S1)
  580. fcr &= ~KL0_SCC_A_INTF_ENABLE;
  581. else
  582. fcr |= KL0_SCC_A_INTF_ENABLE;
  583. }
  584. if (chan_mask & MACIO_FLAG_SCCB_ON) {
  585. fcr |= KL0_SCCB_ENABLE;
  586. /* Perform irda specific inits */
  587. if ((param & 0xfff) == PMAC_SCC_IRDA) {
  588. fcr &= ~KL0_SCC_B_INTF_ENABLE;
  589. fcr |= KL0_IRDA_ENABLE;
  590. fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
  591. fcr |= KL0_IRDA_SOURCE1_SEL;
  592. fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
  593. fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
  594. need_reset_irda = 1;
  595. } else
  596. fcr |= KL0_SCC_B_INTF_ENABLE;
  597. }
  598. MACIO_OUT32(KEYLARGO_FCR0, fcr);
  599. macio->flags |= chan_mask;
  600. if (need_reset_scc) {
  601. MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
  602. (void)MACIO_IN32(KEYLARGO_FCR0);
  603. UNLOCK(flags);
  604. mdelay(15);
  605. LOCK(flags);
  606. MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
  607. }
  608. if (need_reset_irda) {
  609. MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
  610. (void)MACIO_IN32(KEYLARGO_FCR0);
  611. UNLOCK(flags);
  612. mdelay(15);
  613. LOCK(flags);
  614. MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
  615. }
  616. UNLOCK(flags);
  617. if (param & PMAC_SCC_FLAG_XMON)
  618. macio->flags |= MACIO_FLAG_SCC_LOCKED;
  619. } else {
  620. if (macio->flags & MACIO_FLAG_SCC_LOCKED)
  621. return -EPERM;
  622. LOCK(flags);
  623. fcr = MACIO_IN32(KEYLARGO_FCR0);
  624. if (chan_mask & MACIO_FLAG_SCCA_ON)
  625. fcr &= ~KL0_SCCA_ENABLE;
  626. if (chan_mask & MACIO_FLAG_SCCB_ON) {
  627. fcr &= ~KL0_SCCB_ENABLE;
  628. /* Perform irda specific clears */
  629. if ((param & 0xfff) == PMAC_SCC_IRDA) {
  630. fcr &= ~KL0_IRDA_ENABLE;
  631. fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
  632. fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
  633. fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
  634. }
  635. }
  636. MACIO_OUT32(KEYLARGO_FCR0, fcr);
  637. if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
  638. fcr &= ~KL0_SCC_CELL_ENABLE;
  639. MACIO_OUT32(KEYLARGO_FCR0, fcr);
  640. }
  641. macio->flags &= ~(chan_mask);
  642. UNLOCK(flags);
  643. mdelay(10);
  644. }
  645. return 0;
  646. }
  647. static long
  648. core99_modem_enable(struct device_node *node, long param, long value)
  649. {
  650. struct macio_chip* macio;
  651. u8 gpio;
  652. unsigned long flags;
  653. /* Hack for internal USB modem */
  654. if (node == NULL) {
  655. if (macio_chips[0].type != macio_keylargo)
  656. return -ENODEV;
  657. node = macio_chips[0].of_node;
  658. }
  659. macio = macio_find(node, 0);
  660. if (!macio)
  661. return -ENODEV;
  662. gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
  663. gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
  664. gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
  665. if (!value) {
  666. LOCK(flags);
  667. MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
  668. UNLOCK(flags);
  669. (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
  670. mdelay(250);
  671. }
  672. LOCK(flags);
  673. if (value) {
  674. MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
  675. UNLOCK(flags);
  676. (void)MACIO_IN32(KEYLARGO_FCR2);
  677. mdelay(250);
  678. } else {
  679. MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
  680. UNLOCK(flags);
  681. }
  682. if (value) {
  683. LOCK(flags);
  684. MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
  685. (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
  686. UNLOCK(flags); mdelay(250); LOCK(flags);
  687. MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
  688. (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
  689. UNLOCK(flags); mdelay(250); LOCK(flags);
  690. MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
  691. (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
  692. UNLOCK(flags); mdelay(250);
  693. }
  694. return 0;
  695. }
  696. static long
  697. pangea_modem_enable(struct device_node *node, long param, long value)
  698. {
  699. struct macio_chip* macio;
  700. u8 gpio;
  701. unsigned long flags;
  702. /* Hack for internal USB modem */
  703. if (node == NULL) {
  704. if (macio_chips[0].type != macio_pangea &&
  705. macio_chips[0].type != macio_intrepid)
  706. return -ENODEV;
  707. node = macio_chips[0].of_node;
  708. }
  709. macio = macio_find(node, 0);
  710. if (!macio)
  711. return -ENODEV;
  712. gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
  713. gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
  714. gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
  715. if (!value) {
  716. LOCK(flags);
  717. MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
  718. UNLOCK(flags);
  719. (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
  720. mdelay(250);
  721. }
  722. LOCK(flags);
  723. if (value) {
  724. MACIO_OUT8(KL_GPIO_MODEM_POWER,
  725. KEYLARGO_GPIO_OUTPUT_ENABLE);
  726. UNLOCK(flags);
  727. (void)MACIO_IN32(KEYLARGO_FCR2);
  728. mdelay(250);
  729. } else {
  730. MACIO_OUT8(KL_GPIO_MODEM_POWER,
  731. KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
  732. UNLOCK(flags);
  733. }
  734. if (value) {
  735. LOCK(flags);
  736. MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
  737. (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
  738. UNLOCK(flags); mdelay(250); LOCK(flags);
  739. MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
  740. (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
  741. UNLOCK(flags); mdelay(250); LOCK(flags);
  742. MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
  743. (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
  744. UNLOCK(flags); mdelay(250);
  745. }
  746. return 0;
  747. }
  748. static long
  749. core99_ata100_enable(struct device_node *node, long value)
  750. {
  751. unsigned long flags;
  752. struct pci_dev *pdev = NULL;
  753. u8 pbus, pid;
  754. if (uninorth_rev < 0x24)
  755. return -ENODEV;
  756. LOCK(flags);
  757. if (value)
  758. UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
  759. else
  760. UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
  761. (void)UN_IN(UNI_N_CLOCK_CNTL);
  762. UNLOCK(flags);
  763. udelay(20);
  764. if (value) {
  765. if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
  766. pdev = pci_find_slot(pbus, pid);
  767. if (pdev == NULL)
  768. return 0;
  769. pci_enable_device(pdev);
  770. pci_set_master(pdev);
  771. }
  772. return 0;
  773. }
  774. static long
  775. core99_ide_enable(struct device_node *node, long param, long value)
  776. {
  777. /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
  778. * based ata-100
  779. */
  780. switch(param) {
  781. case 0:
  782. return simple_feature_tweak(node, macio_unknown,
  783. KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
  784. case 1:
  785. return simple_feature_tweak(node, macio_unknown,
  786. KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
  787. case 2:
  788. return simple_feature_tweak(node, macio_unknown,
  789. KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
  790. case 3:
  791. return core99_ata100_enable(node, value);
  792. default:
  793. return -ENODEV;
  794. }
  795. }
  796. static long
  797. core99_ide_reset(struct device_node *node, long param, long value)
  798. {
  799. switch(param) {
  800. case 0:
  801. return simple_feature_tweak(node, macio_unknown,
  802. KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
  803. case 1:
  804. return simple_feature_tweak(node, macio_unknown,
  805. KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
  806. case 2:
  807. return simple_feature_tweak(node, macio_unknown,
  808. KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
  809. default:
  810. return -ENODEV;
  811. }
  812. }
  813. static long
  814. core99_gmac_enable(struct device_node *node, long param, long value)
  815. {
  816. unsigned long flags;
  817. LOCK(flags);
  818. if (value)
  819. UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
  820. else
  821. UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
  822. (void)UN_IN(UNI_N_CLOCK_CNTL);
  823. UNLOCK(flags);
  824. udelay(20);
  825. return 0;
  826. }
  827. static long
  828. core99_gmac_phy_reset(struct device_node *node, long param, long value)
  829. {
  830. unsigned long flags;
  831. struct macio_chip *macio;
  832. macio = &macio_chips[0];
  833. if (macio->type != macio_keylargo && macio->type != macio_pangea &&
  834. macio->type != macio_intrepid)
  835. return -ENODEV;
  836. LOCK(flags);
  837. MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
  838. (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
  839. UNLOCK(flags);
  840. mdelay(10);
  841. LOCK(flags);
  842. MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
  843. KEYLARGO_GPIO_OUTOUT_DATA);
  844. UNLOCK(flags);
  845. mdelay(10);
  846. return 0;
  847. }
  848. static long
  849. core99_sound_chip_enable(struct device_node *node, long param, long value)
  850. {
  851. struct macio_chip* macio;
  852. unsigned long flags;
  853. macio = macio_find(node, 0);
  854. if (!macio)
  855. return -ENODEV;
  856. /* Do a better probe code, screamer G4 desktops &
  857. * iMacs can do that too, add a recalibrate in
  858. * the driver as well
  859. */
  860. if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
  861. pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
  862. LOCK(flags);
  863. if (value)
  864. MACIO_OUT8(KL_GPIO_SOUND_POWER,
  865. KEYLARGO_GPIO_OUTPUT_ENABLE |
  866. KEYLARGO_GPIO_OUTOUT_DATA);
  867. else
  868. MACIO_OUT8(KL_GPIO_SOUND_POWER,
  869. KEYLARGO_GPIO_OUTPUT_ENABLE);
  870. (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
  871. UNLOCK(flags);
  872. }
  873. return 0;
  874. }
  875. static long
  876. core99_airport_enable(struct device_node *node, long param, long value)
  877. {
  878. struct macio_chip* macio;
  879. unsigned long flags;
  880. int state;
  881. macio = macio_find(node, 0);
  882. if (!macio)
  883. return -ENODEV;
  884. /* Hint: we allow passing of macio itself for the sake of the
  885. * sleep code
  886. */
  887. if (node != macio->of_node &&
  888. (!node->parent || node->parent != macio->of_node))
  889. return -ENODEV;
  890. state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
  891. if (value == state)
  892. return 0;
  893. if (value) {
  894. /* This code is a reproduction of OF enable-cardslot
  895. * and init-wireless methods, slightly hacked until
  896. * I got it working.
  897. */
  898. LOCK(flags);
  899. MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
  900. (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
  901. UNLOCK(flags);
  902. mdelay(10);
  903. LOCK(flags);
  904. MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
  905. (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
  906. UNLOCK(flags);
  907. mdelay(10);
  908. LOCK(flags);
  909. MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
  910. (void)MACIO_IN32(KEYLARGO_FCR2);
  911. udelay(10);
  912. MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
  913. (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
  914. udelay(10);
  915. MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
  916. (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
  917. udelay(10);
  918. MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
  919. (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
  920. udelay(10);
  921. MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
  922. (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
  923. udelay(10);
  924. MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
  925. (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
  926. UNLOCK(flags);
  927. udelay(10);
  928. MACIO_OUT32(0x1c000, 0);
  929. mdelay(1);
  930. MACIO_OUT8(0x1a3e0, 0x41);
  931. (void)MACIO_IN8(0x1a3e0);
  932. udelay(10);
  933. LOCK(flags);
  934. MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
  935. (void)MACIO_IN32(KEYLARGO_FCR2);
  936. UNLOCK(flags);
  937. mdelay(100);
  938. macio->flags |= MACIO_FLAG_AIRPORT_ON;
  939. } else {
  940. LOCK(flags);
  941. MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
  942. (void)MACIO_IN32(KEYLARGO_FCR2);
  943. MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
  944. MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
  945. MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
  946. MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
  947. MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
  948. (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
  949. UNLOCK(flags);
  950. macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
  951. }
  952. return 0;
  953. }
  954. #ifdef CONFIG_SMP
  955. static long
  956. core99_reset_cpu(struct device_node *node, long param, long value)
  957. {
  958. unsigned int reset_io = 0;
  959. unsigned long flags;
  960. struct macio_chip *macio;
  961. struct device_node *np;
  962. const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
  963. KL_GPIO_RESET_CPU1,
  964. KL_GPIO_RESET_CPU2,
  965. KL_GPIO_RESET_CPU3 };
  966. macio = &macio_chips[0];
  967. if (macio->type != macio_keylargo)
  968. return -ENODEV;
  969. np = find_path_device("/cpus");
  970. if (np == NULL)
  971. return -ENODEV;
  972. for (np = np->child; np != NULL; np = np->sibling) {
  973. u32 *num = (u32 *)get_property(np, "reg", NULL);
  974. u32 *rst = (u32 *)get_property(np, "soft-reset", NULL);
  975. if (num == NULL || rst == NULL)
  976. continue;
  977. if (param == *num) {
  978. reset_io = *rst;
  979. break;
  980. }
  981. }
  982. if (np == NULL || reset_io == 0)
  983. reset_io = dflt_reset_lines[param];
  984. LOCK(flags);
  985. MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
  986. (void)MACIO_IN8(reset_io);
  987. udelay(1);
  988. MACIO_OUT8(reset_io, 0);
  989. (void)MACIO_IN8(reset_io);
  990. UNLOCK(flags);
  991. return 0;
  992. }
  993. #endif /* CONFIG_SMP */
  994. static long
  995. core99_usb_enable(struct device_node *node, long param, long value)
  996. {
  997. struct macio_chip *macio;
  998. unsigned long flags;
  999. char *prop;
  1000. int number;
  1001. u32 reg;
  1002. macio = &macio_chips[0];
  1003. if (macio->type != macio_keylargo && macio->type != macio_pangea &&
  1004. macio->type != macio_intrepid)
  1005. return -ENODEV;
  1006. prop = (char *)get_property(node, "AAPL,clock-id", NULL);
  1007. if (!prop)
  1008. return -ENODEV;
  1009. if (strncmp(prop, "usb0u048", 8) == 0)
  1010. number = 0;
  1011. else if (strncmp(prop, "usb1u148", 8) == 0)
  1012. number = 2;
  1013. else if (strncmp(prop, "usb2u248", 8) == 0)
  1014. number = 4;
  1015. else
  1016. return -ENODEV;
  1017. /* Sorry for the brute-force locking, but this is only used during
  1018. * sleep and the timing seem to be critical
  1019. */
  1020. LOCK(flags);
  1021. if (value) {
  1022. /* Turn ON */
  1023. if (number == 0) {
  1024. MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
  1025. (void)MACIO_IN32(KEYLARGO_FCR0);
  1026. UNLOCK(flags);
  1027. mdelay(1);
  1028. LOCK(flags);
  1029. MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
  1030. } else if (number == 2) {
  1031. MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
  1032. UNLOCK(flags);
  1033. (void)MACIO_IN32(KEYLARGO_FCR0);
  1034. mdelay(1);
  1035. LOCK(flags);
  1036. MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
  1037. } else if (number == 4) {
  1038. MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
  1039. UNLOCK(flags);
  1040. (void)MACIO_IN32(KEYLARGO_FCR1);
  1041. mdelay(1);
  1042. LOCK(flags);
  1043. MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
  1044. }
  1045. if (number < 4) {
  1046. reg = MACIO_IN32(KEYLARGO_FCR4);
  1047. reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
  1048. KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
  1049. reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
  1050. KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
  1051. MACIO_OUT32(KEYLARGO_FCR4, reg);
  1052. (void)MACIO_IN32(KEYLARGO_FCR4);
  1053. udelay(10);
  1054. } else {
  1055. reg = MACIO_IN32(KEYLARGO_FCR3);
  1056. reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
  1057. KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
  1058. reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
  1059. KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
  1060. MACIO_OUT32(KEYLARGO_FCR3, reg);
  1061. (void)MACIO_IN32(KEYLARGO_FCR3);
  1062. udelay(10);
  1063. }
  1064. if (macio->type == macio_intrepid) {
  1065. /* wait for clock stopped bits to clear */
  1066. u32 test0 = 0, test1 = 0;
  1067. u32 status0, status1;
  1068. int timeout = 1000;
  1069. UNLOCK(flags);
  1070. switch (number) {
  1071. case 0:
  1072. test0 = UNI_N_CLOCK_STOPPED_USB0;
  1073. test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
  1074. break;
  1075. case 2:
  1076. test0 = UNI_N_CLOCK_STOPPED_USB1;
  1077. test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
  1078. break;
  1079. case 4:
  1080. test0 = UNI_N_CLOCK_STOPPED_USB2;
  1081. test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
  1082. break;
  1083. }
  1084. do {
  1085. if (--timeout <= 0) {
  1086. printk(KERN_ERR "core99_usb_enable: "
  1087. "Timeout waiting for clocks\n");
  1088. break;
  1089. }
  1090. mdelay(1);
  1091. status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
  1092. status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
  1093. } while ((status0 & test0) | (status1 & test1));
  1094. LOCK(flags);
  1095. }
  1096. } else {
  1097. /* Turn OFF */
  1098. if (number < 4) {
  1099. reg = MACIO_IN32(KEYLARGO_FCR4);
  1100. reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
  1101. KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
  1102. reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
  1103. KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
  1104. MACIO_OUT32(KEYLARGO_FCR4, reg);
  1105. (void)MACIO_IN32(KEYLARGO_FCR4);
  1106. udelay(1);
  1107. } else {
  1108. reg = MACIO_IN32(KEYLARGO_FCR3);
  1109. reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
  1110. KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
  1111. reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
  1112. KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
  1113. MACIO_OUT32(KEYLARGO_FCR3, reg);
  1114. (void)MACIO_IN32(KEYLARGO_FCR3);
  1115. udelay(1);
  1116. }
  1117. if (number == 0) {
  1118. if (macio->type != macio_intrepid)
  1119. MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
  1120. (void)MACIO_IN32(KEYLARGO_FCR0);
  1121. udelay(1);
  1122. MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
  1123. (void)MACIO_IN32(KEYLARGO_FCR0);
  1124. } else if (number == 2) {
  1125. if (macio->type != macio_intrepid)
  1126. MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
  1127. (void)MACIO_IN32(KEYLARGO_FCR0);
  1128. udelay(1);
  1129. MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
  1130. (void)MACIO_IN32(KEYLARGO_FCR0);
  1131. } else if (number == 4) {
  1132. udelay(1);
  1133. MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
  1134. (void)MACIO_IN32(KEYLARGO_FCR1);
  1135. }
  1136. udelay(1);
  1137. }
  1138. UNLOCK(flags);
  1139. return 0;
  1140. }
  1141. static long
  1142. core99_firewire_enable(struct device_node *node, long param, long value)
  1143. {
  1144. unsigned long flags;
  1145. struct macio_chip *macio;
  1146. macio = &macio_chips[0];
  1147. if (macio->type != macio_keylargo && macio->type != macio_pangea &&
  1148. macio->type != macio_intrepid)
  1149. return -ENODEV;
  1150. if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
  1151. return -ENODEV;
  1152. LOCK(flags);
  1153. if (value) {
  1154. UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
  1155. (void)UN_IN(UNI_N_CLOCK_CNTL);
  1156. } else {
  1157. UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
  1158. (void)UN_IN(UNI_N_CLOCK_CNTL);
  1159. }
  1160. UNLOCK(flags);
  1161. mdelay(1);
  1162. return 0;
  1163. }
  1164. static long
  1165. core99_firewire_cable_power(struct device_node *node, long param, long value)
  1166. {
  1167. unsigned long flags;
  1168. struct macio_chip *macio;
  1169. /* Trick: we allow NULL node */
  1170. if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
  1171. return -ENODEV;
  1172. macio = &macio_chips[0];
  1173. if (macio->type != macio_keylargo && macio->type != macio_pangea &&
  1174. macio->type != macio_intrepid)
  1175. return -ENODEV;
  1176. if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
  1177. return -ENODEV;
  1178. LOCK(flags);
  1179. if (value) {
  1180. MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
  1181. MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
  1182. udelay(10);
  1183. } else {
  1184. MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
  1185. MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
  1186. }
  1187. UNLOCK(flags);
  1188. mdelay(1);
  1189. return 0;
  1190. }
  1191. static long
  1192. intrepid_aack_delay_enable(struct device_node *node, long param, long value)
  1193. {
  1194. unsigned long flags;
  1195. if (uninorth_rev < 0xd2)
  1196. return -ENODEV;
  1197. LOCK(flags);
  1198. if (param)
  1199. UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
  1200. else
  1201. UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
  1202. UNLOCK(flags);
  1203. return 0;
  1204. }
  1205. #endif /* CONFIG_POWER4 */
  1206. static long
  1207. core99_read_gpio(struct device_node *node, long param, long value)
  1208. {
  1209. struct macio_chip *macio = &macio_chips[0];
  1210. return MACIO_IN8(param);
  1211. }
  1212. static long
  1213. core99_write_gpio(struct device_node *node, long param, long value)
  1214. {
  1215. struct macio_chip *macio = &macio_chips[0];
  1216. MACIO_OUT8(param, (u8)(value & 0xff));
  1217. return 0;
  1218. }
  1219. #ifdef CONFIG_POWER4
  1220. static long g5_gmac_enable(struct device_node *node, long param, long value)
  1221. {
  1222. struct macio_chip *macio = &macio_chips[0];
  1223. unsigned long flags;
  1224. if (node == NULL)
  1225. return -ENODEV;
  1226. LOCK(flags);
  1227. if (value) {
  1228. MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
  1229. mb();
  1230. k2_skiplist[0] = NULL;
  1231. } else {
  1232. k2_skiplist[0] = node;
  1233. mb();
  1234. MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
  1235. }
  1236. UNLOCK(flags);
  1237. mdelay(1);
  1238. return 0;
  1239. }
  1240. static long g5_fw_enable(struct device_node *node, long param, long value)
  1241. {
  1242. struct macio_chip *macio = &macio_chips[0];
  1243. unsigned long flags;
  1244. if (node == NULL)
  1245. return -ENODEV;
  1246. LOCK(flags);
  1247. if (value) {
  1248. MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
  1249. mb();
  1250. k2_skiplist[1] = NULL;
  1251. } else {
  1252. k2_skiplist[1] = node;
  1253. mb();
  1254. MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
  1255. }
  1256. UNLOCK(flags);
  1257. mdelay(1);
  1258. return 0;
  1259. }
  1260. static long g5_mpic_enable(struct device_node *node, long param, long value)
  1261. {
  1262. unsigned long flags;
  1263. struct device_node *parent = of_get_parent(node);
  1264. int is_u3;
  1265. if (parent == NULL)
  1266. return 0;
  1267. is_u3 = strcmp(parent->name, "u3") == 0 ||
  1268. strcmp(parent->name, "u4") == 0;
  1269. of_node_put(parent);
  1270. if (!is_u3)
  1271. return 0;
  1272. LOCK(flags);
  1273. UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
  1274. UNLOCK(flags);
  1275. return 0;
  1276. }
  1277. static long g5_eth_phy_reset(struct device_node *node, long param, long value)
  1278. {
  1279. struct macio_chip *macio = &macio_chips[0];
  1280. struct device_node *phy;
  1281. int need_reset;
  1282. /*
  1283. * We must not reset the combo PHYs, only the BCM5221 found in
  1284. * the iMac G5.
  1285. */
  1286. phy = of_get_next_child(node, NULL);
  1287. if (!phy)
  1288. return -ENODEV;
  1289. need_reset = device_is_compatible(phy, "B5221");
  1290. of_node_put(phy);
  1291. if (!need_reset)
  1292. return 0;
  1293. /* PHY reset is GPIO 29, not in device-tree unfortunately */
  1294. MACIO_OUT8(K2_GPIO_EXTINT_0 + 29,
  1295. KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
  1296. /* Thankfully, this is now always called at a time when we can
  1297. * schedule by sungem.
  1298. */
  1299. msleep(10);
  1300. MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0);
  1301. return 0;
  1302. }
  1303. static long g5_i2s_enable(struct device_node *node, long param, long value)
  1304. {
  1305. /* Very crude implementation for now */
  1306. struct macio_chip *macio = &macio_chips[0];
  1307. unsigned long flags;
  1308. int cell;
  1309. u32 fcrs[3][3] = {
  1310. { 0,
  1311. K2_FCR1_I2S0_CELL_ENABLE |
  1312. K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE,
  1313. KL3_I2S0_CLK18_ENABLE
  1314. },
  1315. { KL0_SCC_A_INTF_ENABLE,
  1316. K2_FCR1_I2S1_CELL_ENABLE |
  1317. K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE,
  1318. KL3_I2S1_CLK18_ENABLE
  1319. },
  1320. { KL0_SCC_B_INTF_ENABLE,
  1321. SH_FCR1_I2S2_CELL_ENABLE |
  1322. SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE,
  1323. SH_FCR3_I2S2_CLK18_ENABLE
  1324. },
  1325. };
  1326. if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
  1327. return -ENODEV;
  1328. if (strncmp(node->name, "i2s-", 4))
  1329. return -ENODEV;
  1330. cell = node->name[4] - 'a';
  1331. switch(cell) {
  1332. case 0:
  1333. case 1:
  1334. break;
  1335. case 2:
  1336. if (macio->type == macio_shasta)
  1337. break;
  1338. default:
  1339. return -ENODEV;
  1340. }
  1341. LOCK(flags);
  1342. if (value) {
  1343. MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]);
  1344. MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]);
  1345. MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]);
  1346. } else {
  1347. MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]);
  1348. MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]);
  1349. MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]);
  1350. }
  1351. udelay(10);
  1352. UNLOCK(flags);
  1353. return 0;
  1354. }
  1355. #ifdef CONFIG_SMP
  1356. static long g5_reset_cpu(struct device_node *node, long param, long value)
  1357. {
  1358. unsigned int reset_io = 0;
  1359. unsigned long flags;
  1360. struct macio_chip *macio;
  1361. struct device_node *np;
  1362. macio = &macio_chips[0];
  1363. if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
  1364. return -ENODEV;
  1365. np = find_path_device("/cpus");
  1366. if (np == NULL)
  1367. return -ENODEV;
  1368. for (np = np->child; np != NULL; np = np->sibling) {
  1369. u32 *num = (u32 *)get_property(np, "reg", NULL);
  1370. u32 *rst = (u32 *)get_property(np, "soft-reset", NULL);
  1371. if (num == NULL || rst == NULL)
  1372. continue;
  1373. if (param == *num) {
  1374. reset_io = *rst;
  1375. break;
  1376. }
  1377. }
  1378. if (np == NULL || reset_io == 0)
  1379. return -ENODEV;
  1380. LOCK(flags);
  1381. MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
  1382. (void)MACIO_IN8(reset_io);
  1383. udelay(1);
  1384. MACIO_OUT8(reset_io, 0);
  1385. (void)MACIO_IN8(reset_io);
  1386. UNLOCK(flags);
  1387. return 0;
  1388. }
  1389. #endif /* CONFIG_SMP */
  1390. /*
  1391. * This can be called from pmac_smp so isn't static
  1392. *
  1393. * This takes the second CPU off the bus on dual CPU machines
  1394. * running UP
  1395. */
  1396. void g5_phy_disable_cpu1(void)
  1397. {
  1398. if (uninorth_maj == 3)
  1399. UN_OUT(U3_API_PHY_CONFIG_1, 0);
  1400. }
  1401. #endif /* CONFIG_POWER4 */
  1402. #ifndef CONFIG_POWER4
  1403. #ifdef CONFIG_PM
  1404. static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode)
  1405. {
  1406. u32 temp;
  1407. if (sleep_mode) {
  1408. mdelay(1);
  1409. MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
  1410. (void)MACIO_IN32(KEYLARGO_FCR0);
  1411. mdelay(1);
  1412. }
  1413. MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
  1414. KL0_SCC_CELL_ENABLE |
  1415. KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
  1416. KL0_IRDA_CLK19_ENABLE);
  1417. MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
  1418. MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
  1419. MACIO_BIC(KEYLARGO_FCR1,
  1420. KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
  1421. KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
  1422. KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
  1423. KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
  1424. KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
  1425. KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
  1426. KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
  1427. KL1_UIDE_ENABLE);
  1428. MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
  1429. MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
  1430. temp = MACIO_IN32(KEYLARGO_FCR3);
  1431. if (macio->rev >= 2) {
  1432. temp |= KL3_SHUTDOWN_PLL2X;
  1433. if (sleep_mode)
  1434. temp |= KL3_SHUTDOWN_PLL_TOTAL;
  1435. }
  1436. temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
  1437. KL3_SHUTDOWN_PLLKW35;
  1438. if (sleep_mode)
  1439. temp |= KL3_SHUTDOWN_PLLKW12;
  1440. temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
  1441. | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
  1442. if (sleep_mode)
  1443. temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
  1444. MACIO_OUT32(KEYLARGO_FCR3, temp);
  1445. /* Flush posted writes & wait a bit */
  1446. (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
  1447. }
  1448. static void pangea_shutdown(struct macio_chip *macio, int sleep_mode)
  1449. {
  1450. u32 temp;
  1451. MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
  1452. KL0_SCC_CELL_ENABLE |
  1453. KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
  1454. MACIO_BIC(KEYLARGO_FCR1,
  1455. KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
  1456. KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
  1457. KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
  1458. KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
  1459. KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
  1460. KL1_UIDE_ENABLE);
  1461. if (pmac_mb.board_flags & PMAC_MB_MOBILE)
  1462. MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
  1463. MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
  1464. temp = MACIO_IN32(KEYLARGO_FCR3);
  1465. temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
  1466. KL3_SHUTDOWN_PLLKW35;
  1467. temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
  1468. | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
  1469. if (sleep_mode)
  1470. temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
  1471. MACIO_OUT32(KEYLARGO_FCR3, temp);
  1472. /* Flush posted writes & wait a bit */
  1473. (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
  1474. }
  1475. static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode)
  1476. {
  1477. u32 temp;
  1478. MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
  1479. KL0_SCC_CELL_ENABLE);
  1480. MACIO_BIC(KEYLARGO_FCR1,
  1481. KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
  1482. KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
  1483. KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
  1484. KL1_EIDE0_ENABLE);
  1485. if (pmac_mb.board_flags & PMAC_MB_MOBILE)
  1486. MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
  1487. temp = MACIO_IN32(KEYLARGO_FCR3);
  1488. temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
  1489. KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
  1490. if (sleep_mode)
  1491. temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
  1492. MACIO_OUT32(KEYLARGO_FCR3, temp);
  1493. /* Flush posted writes & wait a bit */
  1494. (void)MACIO_IN32(KEYLARGO_FCR0);
  1495. mdelay(10);
  1496. }
  1497. static int
  1498. core99_sleep(void)
  1499. {
  1500. struct macio_chip *macio;
  1501. int i;
  1502. macio = &macio_chips[0];
  1503. if (macio->type != macio_keylargo && macio->type != macio_pangea &&
  1504. macio->type != macio_intrepid)
  1505. return -ENODEV;
  1506. /* We power off the wireless slot in case it was not done
  1507. * by the driver. We don't power it on automatically however
  1508. */
  1509. if (macio->flags & MACIO_FLAG_AIRPORT_ON)
  1510. core99_airport_enable(macio->of_node, 0, 0);
  1511. /* We power off the FW cable. Should be done by the driver... */
  1512. if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
  1513. core99_firewire_enable(NULL, 0, 0);
  1514. core99_firewire_cable_power(NULL, 0, 0);
  1515. }
  1516. /* We make sure int. modem is off (in case driver lost it) */
  1517. if (macio->type == macio_keylargo)
  1518. core99_modem_enable(macio->of_node, 0, 0);
  1519. else
  1520. pangea_modem_enable(macio->of_node, 0, 0);
  1521. /* We make sure the sound is off as well */
  1522. core99_sound_chip_enable(macio->of_node, 0, 0);
  1523. /*
  1524. * Save various bits of KeyLargo
  1525. */
  1526. /* Save the state of the various GPIOs */
  1527. save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
  1528. save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
  1529. for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
  1530. save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
  1531. for (i=0; i<KEYLARGO_GPIO_CNT; i++)
  1532. save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
  1533. /* Save the FCRs */
  1534. if (macio->type == macio_keylargo)
  1535. save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
  1536. save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
  1537. save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
  1538. save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
  1539. save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
  1540. save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
  1541. if (macio->type == macio_pangea || macio->type == macio_intrepid)
  1542. save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
  1543. /* Save state & config of DBDMA channels */
  1544. dbdma_save(macio, save_dbdma);
  1545. /*
  1546. * Turn off as much as we can
  1547. */
  1548. if (macio->type == macio_pangea)
  1549. pangea_shutdown(macio, 1);
  1550. else if (macio->type == macio_intrepid)
  1551. intrepid_shutdown(macio, 1);
  1552. else if (macio->type == macio_keylargo)
  1553. keylargo_shutdown(macio, 1);
  1554. /*
  1555. * Put the host bridge to sleep
  1556. */
  1557. save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
  1558. /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
  1559. * enabled !
  1560. */
  1561. UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
  1562. ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
  1563. udelay(100);
  1564. UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
  1565. UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
  1566. mdelay(10);
  1567. /*
  1568. * FIXME: A bit of black magic with OpenPIC (don't ask me why)
  1569. */
  1570. if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
  1571. MACIO_BIS(0x506e0, 0x00400000);
  1572. MACIO_BIS(0x506e0, 0x80000000);
  1573. }
  1574. return 0;
  1575. }
  1576. static int
  1577. core99_wake_up(void)
  1578. {
  1579. struct macio_chip *macio;
  1580. int i;
  1581. macio = &macio_chips[0];
  1582. if (macio->type != macio_keylargo && macio->type != macio_pangea &&
  1583. macio->type != macio_intrepid)
  1584. return -ENODEV;
  1585. /*
  1586. * Wakeup the host bridge
  1587. */
  1588. UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
  1589. udelay(10);
  1590. UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
  1591. udelay(10);
  1592. /*
  1593. * Restore KeyLargo
  1594. */
  1595. if (macio->type == macio_keylargo) {
  1596. MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
  1597. (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
  1598. }
  1599. MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
  1600. (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
  1601. MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
  1602. (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
  1603. MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
  1604. (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
  1605. MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
  1606. (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
  1607. MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
  1608. (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
  1609. if (macio->type == macio_pangea || macio->type == macio_intrepid) {
  1610. MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
  1611. (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
  1612. }
  1613. dbdma_restore(macio, save_dbdma);
  1614. MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
  1615. MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
  1616. for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
  1617. MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
  1618. for (i=0; i<KEYLARGO_GPIO_CNT; i++)
  1619. MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
  1620. /* FIXME more black magic with OpenPIC ... */
  1621. if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
  1622. MACIO_BIC(0x506e0, 0x00400000);
  1623. MACIO_BIC(0x506e0, 0x80000000);
  1624. }
  1625. UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
  1626. udelay(100);
  1627. return 0;
  1628. }
  1629. #endif /* CONFIG_PM */
  1630. static long
  1631. core99_sleep_state(struct device_node *node, long param, long value)
  1632. {
  1633. /* Param == 1 means to enter the "fake sleep" mode that is
  1634. * used for CPU speed switch
  1635. */
  1636. if (param == 1) {
  1637. if (value == 1) {
  1638. UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
  1639. UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
  1640. } else {
  1641. UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
  1642. udelay(10);
  1643. UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
  1644. udelay(10);
  1645. }
  1646. return 0;
  1647. }
  1648. if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
  1649. return -EPERM;
  1650. #ifdef CONFIG_PM
  1651. if (value == 1)
  1652. return core99_sleep();
  1653. else if (value == 0)
  1654. return core99_wake_up();
  1655. #endif /* CONFIG_PM */
  1656. return 0;
  1657. }
  1658. #endif /* CONFIG_POWER4 */
  1659. static long
  1660. generic_dev_can_wake(struct device_node *node, long param, long value)
  1661. {
  1662. /* Todo: eventually check we are really dealing with on-board
  1663. * video device ...
  1664. */
  1665. if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
  1666. pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
  1667. return 0;
  1668. }
  1669. static long generic_get_mb_info(struct device_node *node, long param, long value)
  1670. {
  1671. switch(param) {
  1672. case PMAC_MB_INFO_MODEL:
  1673. return pmac_mb.model_id;
  1674. case PMAC_MB_INFO_FLAGS:
  1675. return pmac_mb.board_flags;
  1676. case PMAC_MB_INFO_NAME:
  1677. /* hack hack hack... but should work */
  1678. *((const char **)value) = pmac_mb.model_name;
  1679. return 0;
  1680. }
  1681. return -EINVAL;
  1682. }
  1683. /*
  1684. * Table definitions
  1685. */
  1686. /* Used on any machine
  1687. */
  1688. static struct feature_table_entry any_features[] = {
  1689. { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
  1690. { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
  1691. { 0, NULL }
  1692. };
  1693. #ifndef CONFIG_POWER4
  1694. /* OHare based motherboards. Currently, we only use these on the
  1695. * 2400,3400 and 3500 series powerbooks. Some older desktops seem
  1696. * to have issues with turning on/off those asic cells
  1697. */
  1698. static struct feature_table_entry ohare_features[] = {
  1699. { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
  1700. { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
  1701. { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
  1702. { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
  1703. { PMAC_FTR_IDE_RESET, ohare_ide_reset},
  1704. { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
  1705. { 0, NULL }
  1706. };
  1707. /* Heathrow desktop machines (Beige G3).
  1708. * Separated as some features couldn't be properly tested
  1709. * and the serial port control bits appear to confuse it.
  1710. */
  1711. static struct feature_table_entry heathrow_desktop_features[] = {
  1712. { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
  1713. { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
  1714. { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
  1715. { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
  1716. { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
  1717. { 0, NULL }
  1718. };
  1719. /* Heathrow based laptop, that is the Wallstreet and mainstreet
  1720. * powerbooks.
  1721. */
  1722. static struct feature_table_entry heathrow_laptop_features[] = {
  1723. { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
  1724. { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
  1725. { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
  1726. { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
  1727. { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
  1728. { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
  1729. { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
  1730. { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
  1731. { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
  1732. { 0, NULL }
  1733. };
  1734. /* Paddington based machines
  1735. * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
  1736. */
  1737. static struct feature_table_entry paddington_features[] = {
  1738. { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
  1739. { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
  1740. { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
  1741. { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
  1742. { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
  1743. { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
  1744. { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
  1745. { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
  1746. { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
  1747. { 0, NULL }
  1748. };
  1749. /* Core99 & MacRISC 2 machines (all machines released since the
  1750. * iBook (included), that is all AGP machines, except pangea
  1751. * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
  1752. * used on iBook2 & iMac "flow power".
  1753. */
  1754. static struct feature_table_entry core99_features[] = {
  1755. { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
  1756. { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
  1757. { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
  1758. { PMAC_FTR_IDE_RESET, core99_ide_reset },
  1759. { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
  1760. { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
  1761. { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
  1762. { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
  1763. { PMAC_FTR_USB_ENABLE, core99_usb_enable },
  1764. { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
  1765. { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
  1766. #ifdef CONFIG_PM
  1767. { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
  1768. #endif
  1769. #ifdef CONFIG_SMP
  1770. { PMAC_FTR_RESET_CPU, core99_reset_cpu },
  1771. #endif /* CONFIG_SMP */
  1772. { PMAC_FTR_READ_GPIO, core99_read_gpio },
  1773. { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
  1774. { 0, NULL }
  1775. };
  1776. /* RackMac
  1777. */
  1778. static struct feature_table_entry rackmac_features[] = {
  1779. { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
  1780. { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
  1781. { PMAC_FTR_IDE_RESET, core99_ide_reset },
  1782. { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
  1783. { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
  1784. { PMAC_FTR_USB_ENABLE, core99_usb_enable },
  1785. { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
  1786. { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
  1787. { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
  1788. #ifdef CONFIG_SMP
  1789. { PMAC_FTR_RESET_CPU, core99_reset_cpu },
  1790. #endif /* CONFIG_SMP */
  1791. { PMAC_FTR_READ_GPIO, core99_read_gpio },
  1792. { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
  1793. { 0, NULL }
  1794. };
  1795. /* Pangea features
  1796. */
  1797. static struct feature_table_entry pangea_features[] = {
  1798. { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
  1799. { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
  1800. { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
  1801. { PMAC_FTR_IDE_RESET, core99_ide_reset },
  1802. { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
  1803. { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
  1804. { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
  1805. { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
  1806. { PMAC_FTR_USB_ENABLE, core99_usb_enable },
  1807. { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
  1808. { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
  1809. { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
  1810. { PMAC_FTR_READ_GPIO, core99_read_gpio },
  1811. { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
  1812. { 0, NULL }
  1813. };
  1814. /* Intrepid features
  1815. */
  1816. static struct feature_table_entry intrepid_features[] = {
  1817. { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
  1818. { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
  1819. { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
  1820. { PMAC_FTR_IDE_RESET, core99_ide_reset },
  1821. { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
  1822. { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
  1823. { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
  1824. { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
  1825. { PMAC_FTR_USB_ENABLE, core99_usb_enable },
  1826. { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
  1827. { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
  1828. { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
  1829. { PMAC_FTR_READ_GPIO, core99_read_gpio },
  1830. { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
  1831. { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable },
  1832. { 0, NULL }
  1833. };
  1834. #else /* CONFIG_POWER4 */
  1835. /* G5 features
  1836. */
  1837. static struct feature_table_entry g5_features[] = {
  1838. { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
  1839. { PMAC_FTR_1394_ENABLE, g5_fw_enable },
  1840. { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
  1841. { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset },
  1842. { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable },
  1843. #ifdef CONFIG_SMP
  1844. { PMAC_FTR_RESET_CPU, g5_reset_cpu },
  1845. #endif /* CONFIG_SMP */
  1846. { PMAC_FTR_READ_GPIO, core99_read_gpio },
  1847. { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
  1848. { 0, NULL }
  1849. };
  1850. #endif /* CONFIG_POWER4 */
  1851. static struct pmac_mb_def pmac_mb_defs[] = {
  1852. #ifndef CONFIG_POWER4
  1853. /*
  1854. * Desktops
  1855. */
  1856. { "AAPL,8500", "PowerMac 8500/8600",
  1857. PMAC_TYPE_PSURGE, NULL,
  1858. 0
  1859. },
  1860. { "AAPL,9500", "PowerMac 9500/9600",
  1861. PMAC_TYPE_PSURGE, NULL,
  1862. 0
  1863. },
  1864. { "AAPL,7200", "PowerMac 7200",
  1865. PMAC_TYPE_PSURGE, NULL,
  1866. 0
  1867. },
  1868. { "AAPL,7300", "PowerMac 7200/7300",
  1869. PMAC_TYPE_PSURGE, NULL,
  1870. 0
  1871. },
  1872. { "AAPL,7500", "PowerMac 7500",
  1873. PMAC_TYPE_PSURGE, NULL,
  1874. 0
  1875. },
  1876. { "AAPL,ShinerESB", "Apple Network Server",
  1877. PMAC_TYPE_ANS, NULL,
  1878. 0
  1879. },
  1880. { "AAPL,e407", "Alchemy",
  1881. PMAC_TYPE_ALCHEMY, NULL,
  1882. 0
  1883. },
  1884. { "AAPL,e411", "Gazelle",
  1885. PMAC_TYPE_GAZELLE, NULL,
  1886. 0
  1887. },
  1888. { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
  1889. PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
  1890. 0
  1891. },
  1892. { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
  1893. PMAC_TYPE_SILK, heathrow_desktop_features,
  1894. 0
  1895. },
  1896. { "PowerMac1,1", "Blue&White G3",
  1897. PMAC_TYPE_YOSEMITE, paddington_features,
  1898. 0
  1899. },
  1900. { "PowerMac1,2", "PowerMac G4 PCI Graphics",
  1901. PMAC_TYPE_YIKES, paddington_features,
  1902. 0
  1903. },
  1904. { "PowerMac2,1", "iMac FireWire",
  1905. PMAC_TYPE_FW_IMAC, core99_features,
  1906. PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
  1907. },
  1908. { "PowerMac2,2", "iMac FireWire",
  1909. PMAC_TYPE_FW_IMAC, core99_features,
  1910. PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
  1911. },
  1912. { "PowerMac3,1", "PowerMac G4 AGP Graphics",
  1913. PMAC_TYPE_SAWTOOTH, core99_features,
  1914. PMAC_MB_OLD_CORE99
  1915. },
  1916. { "PowerMac3,2", "PowerMac G4 AGP Graphics",
  1917. PMAC_TYPE_SAWTOOTH, core99_features,
  1918. PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
  1919. },
  1920. { "PowerMac3,3", "PowerMac G4 AGP Graphics",
  1921. PMAC_TYPE_SAWTOOTH, core99_features,
  1922. PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
  1923. },
  1924. { "PowerMac3,4", "PowerMac G4 Silver",
  1925. PMAC_TYPE_QUICKSILVER, core99_features,
  1926. PMAC_MB_MAY_SLEEP
  1927. },
  1928. { "PowerMac3,5", "PowerMac G4 Silver",
  1929. PMAC_TYPE_QUICKSILVER, core99_features,
  1930. PMAC_MB_MAY_SLEEP
  1931. },
  1932. { "PowerMac3,6", "PowerMac G4 Windtunnel",
  1933. PMAC_TYPE_WINDTUNNEL, core99_features,
  1934. PMAC_MB_MAY_SLEEP,
  1935. },
  1936. { "PowerMac4,1", "iMac \"Flower Power\"",
  1937. PMAC_TYPE_PANGEA_IMAC, pangea_features,
  1938. PMAC_MB_MAY_SLEEP
  1939. },
  1940. { "PowerMac4,2", "Flat panel iMac",
  1941. PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
  1942. PMAC_MB_CAN_SLEEP
  1943. },
  1944. { "PowerMac4,4", "eMac",
  1945. PMAC_TYPE_EMAC, core99_features,
  1946. PMAC_MB_MAY_SLEEP
  1947. },
  1948. { "PowerMac5,1", "PowerMac G4 Cube",
  1949. PMAC_TYPE_CUBE, core99_features,
  1950. PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
  1951. },
  1952. { "PowerMac6,1", "Flat panel iMac",
  1953. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  1954. PMAC_MB_MAY_SLEEP,
  1955. },
  1956. { "PowerMac6,3", "Flat panel iMac",
  1957. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  1958. PMAC_MB_MAY_SLEEP,
  1959. },
  1960. { "PowerMac6,4", "eMac",
  1961. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  1962. PMAC_MB_MAY_SLEEP,
  1963. },
  1964. { "PowerMac10,1", "Mac mini",
  1965. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  1966. PMAC_MB_MAY_SLEEP,
  1967. },
  1968. { "iMac,1", "iMac (first generation)",
  1969. PMAC_TYPE_ORIG_IMAC, paddington_features,
  1970. 0
  1971. },
  1972. /*
  1973. * Xserve's
  1974. */
  1975. { "RackMac1,1", "XServe",
  1976. PMAC_TYPE_RACKMAC, rackmac_features,
  1977. 0,
  1978. },
  1979. { "RackMac1,2", "XServe rev. 2",
  1980. PMAC_TYPE_RACKMAC, rackmac_features,
  1981. 0,
  1982. },
  1983. /*
  1984. * Laptops
  1985. */
  1986. { "AAPL,3400/2400", "PowerBook 3400",
  1987. PMAC_TYPE_HOOPER, ohare_features,
  1988. PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
  1989. },
  1990. { "AAPL,3500", "PowerBook 3500",
  1991. PMAC_TYPE_KANGA, ohare_features,
  1992. PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
  1993. },
  1994. { "AAPL,PowerBook1998", "PowerBook Wallstreet",
  1995. PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
  1996. PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
  1997. },
  1998. { "PowerBook1,1", "PowerBook 101 (Lombard)",
  1999. PMAC_TYPE_101_PBOOK, paddington_features,
  2000. PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
  2001. },
  2002. { "PowerBook2,1", "iBook (first generation)",
  2003. PMAC_TYPE_ORIG_IBOOK, core99_features,
  2004. PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
  2005. },
  2006. { "PowerBook2,2", "iBook FireWire",
  2007. PMAC_TYPE_FW_IBOOK, core99_features,
  2008. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
  2009. PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
  2010. },
  2011. { "PowerBook3,1", "PowerBook Pismo",
  2012. PMAC_TYPE_PISMO, core99_features,
  2013. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
  2014. PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
  2015. },
  2016. { "PowerBook3,2", "PowerBook Titanium",
  2017. PMAC_TYPE_TITANIUM, core99_features,
  2018. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
  2019. },
  2020. { "PowerBook3,3", "PowerBook Titanium II",
  2021. PMAC_TYPE_TITANIUM2, core99_features,
  2022. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
  2023. },
  2024. { "PowerBook3,4", "PowerBook Titanium III",
  2025. PMAC_TYPE_TITANIUM3, core99_features,
  2026. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
  2027. },
  2028. { "PowerBook3,5", "PowerBook Titanium IV",
  2029. PMAC_TYPE_TITANIUM4, core99_features,
  2030. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
  2031. },
  2032. { "PowerBook4,1", "iBook 2",
  2033. PMAC_TYPE_IBOOK2, pangea_features,
  2034. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
  2035. },
  2036. { "PowerBook4,2", "iBook 2",
  2037. PMAC_TYPE_IBOOK2, pangea_features,
  2038. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
  2039. },
  2040. { "PowerBook4,3", "iBook 2 rev. 2",
  2041. PMAC_TYPE_IBOOK2, pangea_features,
  2042. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
  2043. },
  2044. { "PowerBook5,1", "PowerBook G4 17\"",
  2045. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2046. PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2047. },
  2048. { "PowerBook5,2", "PowerBook G4 15\"",
  2049. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2050. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2051. },
  2052. { "PowerBook5,3", "PowerBook G4 17\"",
  2053. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2054. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2055. },
  2056. { "PowerBook5,4", "PowerBook G4 15\"",
  2057. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2058. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2059. },
  2060. { "PowerBook5,5", "PowerBook G4 17\"",
  2061. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2062. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2063. },
  2064. { "PowerBook5,6", "PowerBook G4 15\"",
  2065. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2066. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2067. },
  2068. { "PowerBook5,7", "PowerBook G4 17\"",
  2069. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2070. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2071. },
  2072. { "PowerBook5,8", "PowerBook G4 15\"",
  2073. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2074. PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
  2075. },
  2076. { "PowerBook5,9", "PowerBook G4 17\"",
  2077. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2078. PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
  2079. },
  2080. { "PowerBook6,1", "PowerBook G4 12\"",
  2081. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2082. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2083. },
  2084. { "PowerBook6,2", "PowerBook G4",
  2085. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2086. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2087. },
  2088. { "PowerBook6,3", "iBook G4",
  2089. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2090. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2091. },
  2092. { "PowerBook6,4", "PowerBook G4 12\"",
  2093. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2094. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2095. },
  2096. { "PowerBook6,5", "iBook G4",
  2097. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2098. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2099. },
  2100. { "PowerBook6,7", "iBook G4",
  2101. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2102. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2103. },
  2104. { "PowerBook6,8", "PowerBook G4 12\"",
  2105. PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
  2106. PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
  2107. },
  2108. #else /* CONFIG_POWER4 */
  2109. { "PowerMac7,2", "PowerMac G5",
  2110. PMAC_TYPE_POWERMAC_G5, g5_features,
  2111. 0,
  2112. },
  2113. #ifdef CONFIG_PPC64
  2114. { "PowerMac7,3", "PowerMac G5",
  2115. PMAC_TYPE_POWERMAC_G5, g5_features,
  2116. 0,
  2117. },
  2118. { "PowerMac8,1", "iMac G5",
  2119. PMAC_TYPE_IMAC_G5, g5_features,
  2120. 0,
  2121. },
  2122. { "PowerMac9,1", "PowerMac G5",
  2123. PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
  2124. 0,
  2125. },
  2126. { "PowerMac11,2", "PowerMac G5 Dual Core",
  2127. PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
  2128. 0,
  2129. },
  2130. { "PowerMac12,1", "iMac G5 (iSight)",
  2131. PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
  2132. 0,
  2133. },
  2134. { "RackMac3,1", "XServe G5",
  2135. PMAC_TYPE_XSERVE_G5, g5_features,
  2136. 0,
  2137. },
  2138. #endif /* CONFIG_PPC64 */
  2139. #endif /* CONFIG_POWER4 */
  2140. };
  2141. /*
  2142. * The toplevel feature_call callback
  2143. */
  2144. long pmac_do_feature_call(unsigned int selector, ...)
  2145. {
  2146. struct device_node *node;
  2147. long param, value;
  2148. int i;
  2149. feature_call func = NULL;
  2150. va_list args;
  2151. if (pmac_mb.features)
  2152. for (i=0; pmac_mb.features[i].function; i++)
  2153. if (pmac_mb.features[i].selector == selector) {
  2154. func = pmac_mb.features[i].function;
  2155. break;
  2156. }
  2157. if (!func)
  2158. for (i=0; any_features[i].function; i++)
  2159. if (any_features[i].selector == selector) {
  2160. func = any_features[i].function;
  2161. break;
  2162. }
  2163. if (!func)
  2164. return -ENODEV;
  2165. va_start(args, selector);
  2166. node = (struct device_node*)va_arg(args, void*);
  2167. param = va_arg(args, long);
  2168. value = va_arg(args, long);
  2169. va_end(args);
  2170. return func(node, param, value);
  2171. }
  2172. static int __init probe_motherboard(void)
  2173. {
  2174. int i;
  2175. struct macio_chip *macio = &macio_chips[0];
  2176. const char *model = NULL;
  2177. struct device_node *dt;
  2178. /* Lookup known motherboard type in device-tree. First try an
  2179. * exact match on the "model" property, then try a "compatible"
  2180. * match is none is found.
  2181. */
  2182. dt = find_devices("device-tree");
  2183. if (dt != NULL)
  2184. model = (const char *) get_property(dt, "model", NULL);
  2185. for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
  2186. if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
  2187. pmac_mb = pmac_mb_defs[i];
  2188. goto found;
  2189. }
  2190. }
  2191. for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
  2192. if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
  2193. pmac_mb = pmac_mb_defs[i];
  2194. goto found;
  2195. }
  2196. }
  2197. /* Fallback to selection depending on mac-io chip type */
  2198. switch(macio->type) {
  2199. #ifndef CONFIG_POWER4
  2200. case macio_grand_central:
  2201. pmac_mb.model_id = PMAC_TYPE_PSURGE;
  2202. pmac_mb.model_name = "Unknown PowerSurge";
  2203. break;
  2204. case macio_ohare:
  2205. pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
  2206. pmac_mb.model_name = "Unknown OHare-based";
  2207. break;
  2208. case macio_heathrow:
  2209. pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
  2210. pmac_mb.model_name = "Unknown Heathrow-based";
  2211. pmac_mb.features = heathrow_desktop_features;
  2212. break;
  2213. case macio_paddington:
  2214. pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
  2215. pmac_mb.model_name = "Unknown Paddington-based";
  2216. pmac_mb.features = paddington_features;
  2217. break;
  2218. case macio_keylargo:
  2219. pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
  2220. pmac_mb.model_name = "Unknown Keylargo-based";
  2221. pmac_mb.features = core99_features;
  2222. break;
  2223. case macio_pangea:
  2224. pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
  2225. pmac_mb.model_name = "Unknown Pangea-based";
  2226. pmac_mb.features = pangea_features;
  2227. break;
  2228. case macio_intrepid:
  2229. pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
  2230. pmac_mb.model_name = "Unknown Intrepid-based";
  2231. pmac_mb.features = intrepid_features;
  2232. break;
  2233. #else /* CONFIG_POWER4 */
  2234. case macio_keylargo2:
  2235. pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
  2236. pmac_mb.model_name = "Unknown K2-based";
  2237. pmac_mb.features = g5_features;
  2238. break;
  2239. case macio_shasta:
  2240. pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA;
  2241. pmac_mb.model_name = "Unknown Shasta-based";
  2242. pmac_mb.features = g5_features;
  2243. break;
  2244. #endif /* CONFIG_POWER4 */
  2245. default:
  2246. return -ENODEV;
  2247. }
  2248. found:
  2249. #ifndef CONFIG_POWER4
  2250. /* Fixup Hooper vs. Comet */
  2251. if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
  2252. u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
  2253. if (!mach_id_ptr)
  2254. return -ENODEV;
  2255. /* Here, I used to disable the media-bay on comet. It
  2256. * appears this is wrong, the floppy connector is actually
  2257. * a kind of media-bay and works with the current driver.
  2258. */
  2259. if (__raw_readl(mach_id_ptr) & 0x20000000UL)
  2260. pmac_mb.model_id = PMAC_TYPE_COMET;
  2261. iounmap(mach_id_ptr);
  2262. }
  2263. /* Set default value of powersave_nap on machines that support it.
  2264. * It appears that uninorth rev 3 has a problem with it, we don't
  2265. * enable it on those. In theory, the flush-on-lock property is
  2266. * supposed to be set when not supported, but I'm not very confident
  2267. * that all Apple OF revs did it properly, I do it the paranoid way.
  2268. */
  2269. while (uninorth_base && uninorth_rev > 3) {
  2270. struct device_node *np = find_path_device("/cpus");
  2271. if (!np || !np->child) {
  2272. printk(KERN_WARNING "Can't find CPU(s) in device tree !\n");
  2273. break;
  2274. }
  2275. np = np->child;
  2276. /* Nap mode not supported on SMP */
  2277. if (np->sibling)
  2278. break;
  2279. /* Nap mode not supported if flush-on-lock property is present */
  2280. if (get_property(np, "flush-on-lock", NULL))
  2281. break;
  2282. powersave_nap = 1;
  2283. printk(KERN_INFO "Processor NAP mode on idle enabled.\n");
  2284. break;
  2285. }
  2286. /* On CPUs that support it (750FX), lowspeed by default during
  2287. * NAP mode
  2288. */
  2289. powersave_lowspeed = 1;
  2290. #else /* CONFIG_POWER4 */
  2291. powersave_nap = 1;
  2292. #endif /* CONFIG_POWER4 */
  2293. /* Check for "mobile" machine */
  2294. if (model && (strncmp(model, "PowerBook", 9) == 0
  2295. || strncmp(model, "iBook", 5) == 0))
  2296. pmac_mb.board_flags |= PMAC_MB_MOBILE;
  2297. printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
  2298. return 0;
  2299. }
  2300. /* Initialize the Core99 UniNorth host bridge and memory controller
  2301. */
  2302. static void __init probe_uninorth(void)
  2303. {
  2304. u32 *addrp;
  2305. phys_addr_t address;
  2306. unsigned long actrl;
  2307. /* Locate core99 Uni-N */
  2308. uninorth_node = of_find_node_by_name(NULL, "uni-n");
  2309. /* Locate G5 u3 */
  2310. if (uninorth_node == NULL) {
  2311. uninorth_node = of_find_node_by_name(NULL, "u3");
  2312. uninorth_maj = 3;
  2313. }
  2314. /* Locate G5 u4 */
  2315. if (uninorth_node == NULL) {
  2316. uninorth_node = of_find_node_by_name(NULL, "u4");
  2317. uninorth_maj = 4;
  2318. }
  2319. if (uninorth_node == NULL)
  2320. return;
  2321. addrp = (u32 *)get_property(uninorth_node, "reg", NULL);
  2322. if (addrp == NULL)
  2323. return;
  2324. address = of_translate_address(uninorth_node, addrp);
  2325. if (address == 0)
  2326. return;
  2327. uninorth_base = ioremap(address, 0x40000);
  2328. uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
  2329. if (uninorth_maj == 3 || uninorth_maj == 4)
  2330. u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
  2331. printk(KERN_INFO "Found %s memory controller & host bridge"
  2332. " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
  2333. uninorth_maj == 4 ? "U4" : "UniNorth",
  2334. (unsigned int)address, uninorth_rev);
  2335. printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
  2336. /* Set the arbitrer QAck delay according to what Apple does
  2337. */
  2338. if (uninorth_rev < 0x11) {
  2339. actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
  2340. actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
  2341. UNI_N_ARB_CTRL_QACK_DELAY) <<
  2342. UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
  2343. UN_OUT(UNI_N_ARB_CTRL, actrl);
  2344. }
  2345. /* Some more magic as done by them in recent MacOS X on UniNorth
  2346. * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
  2347. * memory timeout
  2348. */
  2349. if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) ||
  2350. uninorth_rev == 0xc0)
  2351. UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
  2352. }
  2353. static void __init probe_one_macio(const char *name, const char *compat, int type)
  2354. {
  2355. struct device_node* node;
  2356. int i;
  2357. volatile u32 __iomem *base;
  2358. u32 *addrp, *revp;
  2359. phys_addr_t addr;
  2360. u64 size;
  2361. for (node = NULL; (node = of_find_node_by_name(node, name)) != NULL;) {
  2362. if (!compat)
  2363. break;
  2364. if (device_is_compatible(node, compat))
  2365. break;
  2366. }
  2367. if (!node)
  2368. return;
  2369. for(i=0; i<MAX_MACIO_CHIPS; i++) {
  2370. if (!macio_chips[i].of_node)
  2371. break;
  2372. if (macio_chips[i].of_node == node)
  2373. return;
  2374. }
  2375. if (i >= MAX_MACIO_CHIPS) {
  2376. printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
  2377. printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name);
  2378. return;
  2379. }
  2380. addrp = of_get_pci_address(node, 0, &size, NULL);
  2381. if (addrp == NULL) {
  2382. printk(KERN_ERR "pmac_feature: %s: can't find base !\n",
  2383. node->full_name);
  2384. return;
  2385. }
  2386. addr = of_translate_address(node, addrp);
  2387. if (addr == 0) {
  2388. printk(KERN_ERR "pmac_feature: %s, can't translate base !\n",
  2389. node->full_name);
  2390. return;
  2391. }
  2392. base = ioremap(addr, (unsigned long)size);
  2393. if (!base) {
  2394. printk(KERN_ERR "pmac_feature: %s, can't map mac-io chip !\n",
  2395. node->full_name);
  2396. return;
  2397. }
  2398. if (type == macio_keylargo || type == macio_keylargo2) {
  2399. u32 *did = (u32 *)get_property(node, "device-id", NULL);
  2400. if (*did == 0x00000025)
  2401. type = macio_pangea;
  2402. if (*did == 0x0000003e)
  2403. type = macio_intrepid;
  2404. if (*did == 0x0000004f)
  2405. type = macio_shasta;
  2406. }
  2407. macio_chips[i].of_node = node;
  2408. macio_chips[i].type = type;
  2409. macio_chips[i].base = base;
  2410. macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON;
  2411. macio_chips[i].name = macio_names[type];
  2412. revp = (u32 *)get_property(node, "revision-id", NULL);
  2413. if (revp)
  2414. macio_chips[i].rev = *revp;
  2415. printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
  2416. macio_names[type], macio_chips[i].rev, macio_chips[i].base);
  2417. }
  2418. static int __init
  2419. probe_macios(void)
  2420. {
  2421. /* Warning, ordering is important */
  2422. probe_one_macio("gc", NULL, macio_grand_central);
  2423. probe_one_macio("ohare", NULL, macio_ohare);
  2424. probe_one_macio("pci106b,7", NULL, macio_ohareII);
  2425. probe_one_macio("mac-io", "keylargo", macio_keylargo);
  2426. probe_one_macio("mac-io", "paddington", macio_paddington);
  2427. probe_one_macio("mac-io", "gatwick", macio_gatwick);
  2428. probe_one_macio("mac-io", "heathrow", macio_heathrow);
  2429. probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
  2430. /* Make sure the "main" macio chip appear first */
  2431. if (macio_chips[0].type == macio_gatwick
  2432. && macio_chips[1].type == macio_heathrow) {
  2433. struct macio_chip temp = macio_chips[0];
  2434. macio_chips[0] = macio_chips[1];
  2435. macio_chips[1] = temp;
  2436. }
  2437. if (macio_chips[0].type == macio_ohareII
  2438. && macio_chips[1].type == macio_ohare) {
  2439. struct macio_chip temp = macio_chips[0];
  2440. macio_chips[0] = macio_chips[1];
  2441. macio_chips[1] = temp;
  2442. }
  2443. macio_chips[0].lbus.index = 0;
  2444. macio_chips[1].lbus.index = 1;
  2445. return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
  2446. }
  2447. static void __init
  2448. initial_serial_shutdown(struct device_node *np)
  2449. {
  2450. int len;
  2451. struct slot_names_prop {
  2452. int count;
  2453. char name[1];
  2454. } *slots;
  2455. char *conn;
  2456. int port_type = PMAC_SCC_ASYNC;
  2457. int modem = 0;
  2458. slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
  2459. conn = get_property(np, "AAPL,connector", &len);
  2460. if (conn && (strcmp(conn, "infrared") == 0))
  2461. port_type = PMAC_SCC_IRDA;
  2462. else if (device_is_compatible(np, "cobalt"))
  2463. modem = 1;
  2464. else if (slots && slots->count > 0) {
  2465. if (strcmp(slots->name, "IrDA") == 0)
  2466. port_type = PMAC_SCC_IRDA;
  2467. else if (strcmp(slots->name, "Modem") == 0)
  2468. modem = 1;
  2469. }
  2470. if (modem)
  2471. pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
  2472. pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
  2473. }
  2474. static void __init
  2475. set_initial_features(void)
  2476. {
  2477. struct device_node *np;
  2478. /* That hack appears to be necessary for some StarMax motherboards
  2479. * but I'm not too sure it was audited for side-effects on other
  2480. * ohare based machines...
  2481. * Since I still have difficulties figuring the right way to
  2482. * differenciate them all and since that hack was there for a long
  2483. * time, I'll keep it around
  2484. */
  2485. if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) {
  2486. struct macio_chip *macio = &macio_chips[0];
  2487. MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
  2488. } else if (macio_chips[0].type == macio_ohare) {
  2489. struct macio_chip *macio = &macio_chips[0];
  2490. MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
  2491. } else if (macio_chips[1].type == macio_ohare) {
  2492. struct macio_chip *macio = &macio_chips[1];
  2493. MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
  2494. }
  2495. #ifdef CONFIG_POWER4
  2496. if (macio_chips[0].type == macio_keylargo2 ||
  2497. macio_chips[0].type == macio_shasta) {
  2498. #ifndef CONFIG_SMP
  2499. /* On SMP machines running UP, we have the second CPU eating
  2500. * bus cycles. We need to take it off the bus. This is done
  2501. * from pmac_smp for SMP kernels running on one CPU
  2502. */
  2503. np = of_find_node_by_type(NULL, "cpu");
  2504. if (np != NULL)
  2505. np = of_find_node_by_type(np, "cpu");
  2506. if (np != NULL) {
  2507. g5_phy_disable_cpu1();
  2508. of_node_put(np);
  2509. }
  2510. #endif /* CONFIG_SMP */
  2511. /* Enable GMAC for now for PCI probing. It will be disabled
  2512. * later on after PCI probe
  2513. */
  2514. np = of_find_node_by_name(NULL, "ethernet");
  2515. while(np) {
  2516. if (device_is_compatible(np, "K2-GMAC"))
  2517. g5_gmac_enable(np, 0, 1);
  2518. np = of_find_node_by_name(np, "ethernet");
  2519. }
  2520. /* Enable FW before PCI probe. Will be disabled later on
  2521. * Note: We should have a batter way to check that we are
  2522. * dealing with uninorth internal cell and not a PCI cell
  2523. * on the external PCI. The code below works though.
  2524. */
  2525. np = of_find_node_by_name(NULL, "firewire");
  2526. while(np) {
  2527. if (device_is_compatible(np, "pci106b,5811")) {
  2528. macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
  2529. g5_fw_enable(np, 0, 1);
  2530. }
  2531. np = of_find_node_by_name(np, "firewire");
  2532. }
  2533. }
  2534. #else /* CONFIG_POWER4 */
  2535. if (macio_chips[0].type == macio_keylargo ||
  2536. macio_chips[0].type == macio_pangea ||
  2537. macio_chips[0].type == macio_intrepid) {
  2538. /* Enable GMAC for now for PCI probing. It will be disabled
  2539. * later on after PCI probe
  2540. */
  2541. np = of_find_node_by_name(NULL, "ethernet");
  2542. while(np) {
  2543. if (np->parent
  2544. && device_is_compatible(np->parent, "uni-north")
  2545. && device_is_compatible(np, "gmac"))
  2546. core99_gmac_enable(np, 0, 1);
  2547. np = of_find_node_by_name(np, "ethernet");
  2548. }
  2549. /* Enable FW before PCI probe. Will be disabled later on
  2550. * Note: We should have a batter way to check that we are
  2551. * dealing with uninorth internal cell and not a PCI cell
  2552. * on the external PCI. The code below works though.
  2553. */
  2554. np = of_find_node_by_name(NULL, "firewire");
  2555. while(np) {
  2556. if (np->parent
  2557. && device_is_compatible(np->parent, "uni-north")
  2558. && (device_is_compatible(np, "pci106b,18") ||
  2559. device_is_compatible(np, "pci106b,30") ||
  2560. device_is_compatible(np, "pci11c1,5811"))) {
  2561. macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
  2562. core99_firewire_enable(np, 0, 1);
  2563. }
  2564. np = of_find_node_by_name(np, "firewire");
  2565. }
  2566. /* Enable ATA-100 before PCI probe. */
  2567. np = of_find_node_by_name(NULL, "ata-6");
  2568. while(np) {
  2569. if (np->parent
  2570. && device_is_compatible(np->parent, "uni-north")
  2571. && device_is_compatible(np, "kauai-ata")) {
  2572. core99_ata100_enable(np, 1);
  2573. }
  2574. np = of_find_node_by_name(np, "ata-6");
  2575. }
  2576. /* Switch airport off */
  2577. np = find_devices("radio");
  2578. while(np) {
  2579. if (np && np->parent == macio_chips[0].of_node) {
  2580. macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
  2581. core99_airport_enable(np, 0, 0);
  2582. }
  2583. np = np->next;
  2584. }
  2585. }
  2586. /* On all machines that support sound PM, switch sound off */
  2587. if (macio_chips[0].of_node)
  2588. pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
  2589. macio_chips[0].of_node, 0, 0);
  2590. /* While on some desktop G3s, we turn it back on */
  2591. if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
  2592. && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
  2593. pmac_mb.model_id == PMAC_TYPE_SILK)) {
  2594. struct macio_chip *macio = &macio_chips[0];
  2595. MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
  2596. MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
  2597. }
  2598. #endif /* CONFIG_POWER4 */
  2599. /* On all machines, switch modem & serial ports off */
  2600. np = find_devices("ch-a");
  2601. while(np) {
  2602. initial_serial_shutdown(np);
  2603. np = np->next;
  2604. }
  2605. np = find_devices("ch-b");
  2606. while(np) {
  2607. initial_serial_shutdown(np);
  2608. np = np->next;
  2609. }
  2610. }
  2611. void __init
  2612. pmac_feature_init(void)
  2613. {
  2614. /* Detect the UniNorth memory controller */
  2615. probe_uninorth();
  2616. /* Probe mac-io controllers */
  2617. if (probe_macios()) {
  2618. printk(KERN_WARNING "No mac-io chip found\n");
  2619. return;
  2620. }
  2621. /* Probe machine type */
  2622. if (probe_motherboard())
  2623. printk(KERN_WARNING "Unknown PowerMac !\n");
  2624. /* Set some initial features (turn off some chips that will
  2625. * be later turned on)
  2626. */
  2627. set_initial_features();
  2628. }
  2629. #if 0
  2630. static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
  2631. {
  2632. int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
  2633. int bits[8] = { 8,16,0,32,2,4,0,0 };
  2634. int freq = (frq >> 8) & 0xf;
  2635. if (freqs[freq] == 0)
  2636. printk("%s: Unknown HT link frequency %x\n", name, freq);
  2637. else
  2638. printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
  2639. name, freqs[freq],
  2640. bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
  2641. }
  2642. void __init pmac_check_ht_link(void)
  2643. {
  2644. u32 ufreq, freq, ucfg, cfg;
  2645. struct device_node *pcix_node;
  2646. u8 px_bus, px_devfn;
  2647. struct pci_controller *px_hose;
  2648. (void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND);
  2649. ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG);
  2650. ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ);
  2651. dump_HT_speeds("U3 HyperTransport", cfg, freq);
  2652. pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
  2653. if (pcix_node == NULL) {
  2654. printk("No PCI-X bridge found\n");
  2655. return;
  2656. }
  2657. if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
  2658. printk("PCI-X bridge found but not matched to pci\n");
  2659. return;
  2660. }
  2661. px_hose = pci_find_hose_for_OF_device(pcix_node);
  2662. if (px_hose == NULL) {
  2663. printk("PCI-X bridge found but not matched to host\n");
  2664. return;
  2665. }
  2666. early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
  2667. early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
  2668. dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
  2669. early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
  2670. early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
  2671. dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
  2672. }
  2673. #endif /* 0 */
  2674. /*
  2675. * Early video resume hook
  2676. */
  2677. static void (*pmac_early_vresume_proc)(void *data);
  2678. static void *pmac_early_vresume_data;
  2679. void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
  2680. {
  2681. if (_machine != _MACH_Pmac)
  2682. return;
  2683. preempt_disable();
  2684. pmac_early_vresume_proc = proc;
  2685. pmac_early_vresume_data = data;
  2686. preempt_enable();
  2687. }
  2688. EXPORT_SYMBOL(pmac_set_early_video_resume);
  2689. void pmac_call_early_video_resume(void)
  2690. {
  2691. if (pmac_early_vresume_proc)
  2692. pmac_early_vresume_proc(pmac_early_vresume_data);
  2693. }
  2694. /*
  2695. * AGP related suspend/resume code
  2696. */
  2697. static struct pci_dev *pmac_agp_bridge;
  2698. static int (*pmac_agp_suspend)(struct pci_dev *bridge);
  2699. static int (*pmac_agp_resume)(struct pci_dev *bridge);
  2700. void pmac_register_agp_pm(struct pci_dev *bridge,
  2701. int (*suspend)(struct pci_dev *bridge),
  2702. int (*resume)(struct pci_dev *bridge))
  2703. {
  2704. if (suspend || resume) {
  2705. pmac_agp_bridge = bridge;
  2706. pmac_agp_suspend = suspend;
  2707. pmac_agp_resume = resume;
  2708. return;
  2709. }
  2710. if (bridge != pmac_agp_bridge)
  2711. return;
  2712. pmac_agp_suspend = pmac_agp_resume = NULL;
  2713. return;
  2714. }
  2715. EXPORT_SYMBOL(pmac_register_agp_pm);
  2716. void pmac_suspend_agp_for_card(struct pci_dev *dev)
  2717. {
  2718. if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
  2719. return;
  2720. if (pmac_agp_bridge->bus != dev->bus)
  2721. return;
  2722. pmac_agp_suspend(pmac_agp_bridge);
  2723. }
  2724. EXPORT_SYMBOL(pmac_suspend_agp_for_card);
  2725. void pmac_resume_agp_for_card(struct pci_dev *dev)
  2726. {
  2727. if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
  2728. return;
  2729. if (pmac_agp_bridge->bus != dev->bus)
  2730. return;
  2731. pmac_agp_resume(pmac_agp_bridge);
  2732. }
  2733. EXPORT_SYMBOL(pmac_resume_agp_for_card);