clock.c 31 KB

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  1. /*
  2. * arch/arm/mach-lpc32xx/clock.c
  3. *
  4. * Author: Kevin Wells <kevin.wells@nxp.com>
  5. *
  6. * Copyright (C) 2010 NXP Semiconductors
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. /*
  19. * LPC32xx clock management driver overview
  20. *
  21. * The LPC32XX contains a number of high level system clocks that can be
  22. * generated from different sources. These system clocks are used to
  23. * generate the CPU and bus rates and the individual peripheral clocks in
  24. * the system. When Linux is started by the boot loader, the system
  25. * clocks are already running. Stopping a system clock during normal
  26. * Linux operation should never be attempted, as peripherals that require
  27. * those clocks will quit working (ie, DRAM).
  28. *
  29. * The LPC32xx high level clock tree looks as follows. Clocks marked with
  30. * an asterisk are always on and cannot be disabled. Clocks marked with
  31. * an ampersand can only be disabled in CPU suspend mode. Clocks marked
  32. * with a caret are always on if it is the selected clock for the SYSCLK
  33. * source. The clock that isn't used for SYSCLK can be enabled and
  34. * disabled normally.
  35. * 32KHz oscillator*
  36. * / | \
  37. * RTC* PLL397^ TOUCH
  38. * /
  39. * Main oscillator^ /
  40. * | \ /
  41. * | SYSCLK&
  42. * | \
  43. * | \
  44. * USB_PLL HCLK_PLL&
  45. * | | |
  46. * USB host/device PCLK& |
  47. * | |
  48. * Peripherals
  49. *
  50. * The CPU and chip bus rates are derived from the HCLK PLL, which can
  51. * generate various clock rates up to 266MHz and beyond. The internal bus
  52. * rates (PCLK and HCLK) are generated from dividers based on the HCLK
  53. * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
  54. * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
  55. * level clocks are based on either HCLK or PCLK, but have their own
  56. * dividers as part of the IP itself. Because of this, the system clock
  57. * rates should not be changed.
  58. *
  59. * The HCLK PLL is clocked from SYSCLK, which can be derived from the
  60. * main oscillator or PLL397. PLL397 generates a rate that is 397 times
  61. * the 32KHz oscillator rate. The main oscillator runs at the selected
  62. * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
  63. * is normally 13MHz, but depends on the selection of external crystals
  64. * or oscillators. If USB operation is required, the main oscillator must
  65. * be used in the system.
  66. *
  67. * Switching SYSCLK between sources during normal Linux operation is not
  68. * supported. SYSCLK is preset in the bootloader. Because of the
  69. * complexities of clock management during clock frequency changes,
  70. * there are some limitations to the clock driver explained below:
  71. * - The PLL397 and main oscillator can be enabled and disabled by the
  72. * clk_enable() and clk_disable() functions unless SYSCLK is based
  73. * on that clock. This allows the other oscillator that isn't driving
  74. * the HCLK PLL to be used as another system clock that can be routed
  75. * to an external pin.
  76. * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
  77. * this driver.
  78. * - HCLK and PCLK rates cannot be changed as part of this driver.
  79. * - Most peripherals have their own dividers are part of the peripheral
  80. * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
  81. * will also impact the individual peripheral rates.
  82. */
  83. #include <linux/export.h>
  84. #include <linux/kernel.h>
  85. #include <linux/list.h>
  86. #include <linux/errno.h>
  87. #include <linux/device.h>
  88. #include <linux/err.h>
  89. #include <linux/clk.h>
  90. #include <linux/amba/bus.h>
  91. #include <linux/amba/clcd.h>
  92. #include <linux/clkdev.h>
  93. #include <mach/hardware.h>
  94. #include <mach/platform.h>
  95. #include "clock.h"
  96. #include "common.h"
  97. static DEFINE_SPINLOCK(global_clkregs_lock);
  98. static struct clk clk_armpll;
  99. static struct clk clk_usbpll;
  100. /*
  101. * Post divider values for PLLs based on selected register value
  102. */
  103. static const u32 pll_postdivs[4] = {1, 2, 4, 8};
  104. static unsigned long local_return_parent_rate(struct clk *clk)
  105. {
  106. /*
  107. * If a clock has a rate of 0, then it inherits it's parent
  108. * clock rate
  109. */
  110. while (clk->rate == 0)
  111. clk = clk->parent;
  112. return clk->rate;
  113. }
  114. /* 32KHz clock has a fixed rate and is not stoppable */
  115. static struct clk osc_32KHz = {
  116. .rate = LPC32XX_CLOCK_OSC_FREQ,
  117. .get_rate = local_return_parent_rate,
  118. };
  119. static int local_pll397_enable(struct clk *clk, int enable)
  120. {
  121. u32 reg;
  122. unsigned long timeout = jiffies + msecs_to_jiffies(10);
  123. reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
  124. if (enable == 0) {
  125. reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
  126. __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
  127. } else {
  128. /* Enable PLL397 */
  129. reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
  130. __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
  131. /* Wait for PLL397 lock */
  132. while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
  133. LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
  134. time_before(jiffies, timeout))
  135. cpu_relax();
  136. if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
  137. LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
  138. return -ENODEV;
  139. }
  140. return 0;
  141. }
  142. static int local_oscmain_enable(struct clk *clk, int enable)
  143. {
  144. u32 reg;
  145. unsigned long timeout = jiffies + msecs_to_jiffies(10);
  146. reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
  147. if (enable == 0) {
  148. reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
  149. __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
  150. } else {
  151. /* Enable main oscillator */
  152. reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
  153. __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
  154. /* Wait for main oscillator to start */
  155. while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
  156. LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
  157. time_before(jiffies, timeout))
  158. cpu_relax();
  159. if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
  160. LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
  161. return -ENODEV;
  162. }
  163. return 0;
  164. }
  165. static struct clk osc_pll397 = {
  166. .parent = &osc_32KHz,
  167. .enable = local_pll397_enable,
  168. .rate = LPC32XX_CLOCK_OSC_FREQ * 397,
  169. .get_rate = local_return_parent_rate,
  170. };
  171. static struct clk osc_main = {
  172. .enable = local_oscmain_enable,
  173. .rate = LPC32XX_MAIN_OSC_FREQ,
  174. .get_rate = local_return_parent_rate,
  175. };
  176. static struct clk clk_sys;
  177. /*
  178. * Convert a PLL register value to a PLL output frequency
  179. */
  180. u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
  181. {
  182. struct clk_pll_setup pllcfg;
  183. pllcfg.cco_bypass_b15 = 0;
  184. pllcfg.direct_output_b14 = 0;
  185. pllcfg.fdbk_div_ctrl_b13 = 0;
  186. if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
  187. pllcfg.cco_bypass_b15 = 1;
  188. if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
  189. pllcfg.direct_output_b14 = 1;
  190. if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
  191. pllcfg.fdbk_div_ctrl_b13 = 1;
  192. pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
  193. pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
  194. pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
  195. return clk_check_pll_setup(inputclk, &pllcfg);
  196. }
  197. /*
  198. * Setup the HCLK PLL with a PLL structure
  199. */
  200. static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
  201. {
  202. u32 tv, tmp = 0;
  203. if (PllSetup->analog_on != 0)
  204. tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
  205. if (PllSetup->cco_bypass_b15 != 0)
  206. tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
  207. if (PllSetup->direct_output_b14 != 0)
  208. tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
  209. if (PllSetup->fdbk_div_ctrl_b13 != 0)
  210. tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
  211. tv = ffs(PllSetup->pll_p) - 1;
  212. if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
  213. return 0;
  214. tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
  215. tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
  216. tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
  217. return tmp;
  218. }
  219. /*
  220. * Update the ARM core PLL frequency rate variable from the actual PLL setting
  221. */
  222. static void local_update_armpll_rate(void)
  223. {
  224. u32 clkin, pllreg;
  225. clkin = clk_armpll.parent->rate;
  226. pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
  227. clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
  228. }
  229. /*
  230. * Find a PLL configuration for the selected input frequency
  231. */
  232. static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
  233. struct clk_pll_setup *pllsetup)
  234. {
  235. u32 ifreq, freqtol, m, n, p, fclkout;
  236. /* Determine frequency tolerance limits */
  237. freqtol = target_freq / 250;
  238. ifreq = pllin_freq;
  239. /* Is direct bypass mode possible? */
  240. if (abs(pllin_freq - target_freq) <= freqtol) {
  241. pllsetup->analog_on = 0;
  242. pllsetup->cco_bypass_b15 = 1;
  243. pllsetup->direct_output_b14 = 1;
  244. pllsetup->fdbk_div_ctrl_b13 = 1;
  245. pllsetup->pll_p = pll_postdivs[0];
  246. pllsetup->pll_n = 1;
  247. pllsetup->pll_m = 1;
  248. return clk_check_pll_setup(ifreq, pllsetup);
  249. } else if (target_freq <= ifreq) {
  250. pllsetup->analog_on = 0;
  251. pllsetup->cco_bypass_b15 = 1;
  252. pllsetup->direct_output_b14 = 0;
  253. pllsetup->fdbk_div_ctrl_b13 = 1;
  254. pllsetup->pll_n = 1;
  255. pllsetup->pll_m = 1;
  256. for (p = 0; p <= 3; p++) {
  257. pllsetup->pll_p = pll_postdivs[p];
  258. fclkout = clk_check_pll_setup(ifreq, pllsetup);
  259. if (abs(target_freq - fclkout) <= freqtol)
  260. return fclkout;
  261. }
  262. }
  263. /* Is direct mode possible? */
  264. pllsetup->analog_on = 1;
  265. pllsetup->cco_bypass_b15 = 0;
  266. pllsetup->direct_output_b14 = 1;
  267. pllsetup->fdbk_div_ctrl_b13 = 0;
  268. pllsetup->pll_p = pll_postdivs[0];
  269. for (m = 1; m <= 256; m++) {
  270. for (n = 1; n <= 4; n++) {
  271. /* Compute output frequency for this value */
  272. pllsetup->pll_n = n;
  273. pllsetup->pll_m = m;
  274. fclkout = clk_check_pll_setup(ifreq,
  275. pllsetup);
  276. if (abs(target_freq - fclkout) <=
  277. freqtol)
  278. return fclkout;
  279. }
  280. }
  281. /* Is integer mode possible? */
  282. pllsetup->analog_on = 1;
  283. pllsetup->cco_bypass_b15 = 0;
  284. pllsetup->direct_output_b14 = 0;
  285. pllsetup->fdbk_div_ctrl_b13 = 1;
  286. for (m = 1; m <= 256; m++) {
  287. for (n = 1; n <= 4; n++) {
  288. for (p = 0; p < 4; p++) {
  289. /* Compute output frequency */
  290. pllsetup->pll_p = pll_postdivs[p];
  291. pllsetup->pll_n = n;
  292. pllsetup->pll_m = m;
  293. fclkout = clk_check_pll_setup(
  294. ifreq, pllsetup);
  295. if (abs(target_freq - fclkout) <= freqtol)
  296. return fclkout;
  297. }
  298. }
  299. }
  300. /* Try non-integer mode */
  301. pllsetup->analog_on = 1;
  302. pllsetup->cco_bypass_b15 = 0;
  303. pllsetup->direct_output_b14 = 0;
  304. pllsetup->fdbk_div_ctrl_b13 = 0;
  305. for (m = 1; m <= 256; m++) {
  306. for (n = 1; n <= 4; n++) {
  307. for (p = 0; p < 4; p++) {
  308. /* Compute output frequency */
  309. pllsetup->pll_p = pll_postdivs[p];
  310. pllsetup->pll_n = n;
  311. pllsetup->pll_m = m;
  312. fclkout = clk_check_pll_setup(
  313. ifreq, pllsetup);
  314. if (abs(target_freq - fclkout) <= freqtol)
  315. return fclkout;
  316. }
  317. }
  318. }
  319. return 0;
  320. }
  321. static struct clk clk_armpll = {
  322. .parent = &clk_sys,
  323. .get_rate = local_return_parent_rate,
  324. };
  325. /*
  326. * Setup the USB PLL with a PLL structure
  327. */
  328. static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
  329. {
  330. u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
  331. reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
  332. reg |= tmp;
  333. __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
  334. return clk_check_pll_setup(clk_usbpll.parent->rate,
  335. pHCLKPllSetup);
  336. }
  337. static int local_usbpll_enable(struct clk *clk, int enable)
  338. {
  339. u32 reg;
  340. int ret = -ENODEV;
  341. unsigned long timeout = jiffies + msecs_to_jiffies(10);
  342. reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
  343. if (enable == 0) {
  344. reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
  345. LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
  346. __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
  347. } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
  348. reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
  349. __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
  350. /* Wait for PLL lock */
  351. while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
  352. reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
  353. if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
  354. ret = 0;
  355. }
  356. if (ret == 0) {
  357. reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
  358. __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
  359. }
  360. }
  361. return ret;
  362. }
  363. static unsigned long local_usbpll_round_rate(struct clk *clk,
  364. unsigned long rate)
  365. {
  366. u32 clkin, usbdiv;
  367. struct clk_pll_setup pllsetup;
  368. /*
  369. * Unlike other clocks, this clock has a KHz input rate, so bump
  370. * it up to work with the PLL function
  371. */
  372. rate = rate * 1000;
  373. clkin = clk->parent->rate;
  374. usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
  375. LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
  376. clkin = clkin / usbdiv;
  377. /* Try to find a good rate setup */
  378. if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
  379. return 0;
  380. return clk_check_pll_setup(clkin, &pllsetup);
  381. }
  382. static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
  383. {
  384. u32 clkin, reg, usbdiv;
  385. struct clk_pll_setup pllsetup;
  386. /*
  387. * Unlike other clocks, this clock has a KHz input rate, so bump
  388. * it up to work with the PLL function
  389. */
  390. rate = rate * 1000;
  391. clkin = clk->get_rate(clk);
  392. usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
  393. LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
  394. clkin = clkin / usbdiv;
  395. /* Try to find a good rate setup */
  396. if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
  397. return -EINVAL;
  398. local_usbpll_enable(clk, 0);
  399. reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
  400. reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
  401. __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
  402. pllsetup.analog_on = 1;
  403. local_clk_usbpll_setup(&pllsetup);
  404. clk->rate = clk_check_pll_setup(clkin, &pllsetup);
  405. reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
  406. reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
  407. __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
  408. return 0;
  409. }
  410. static struct clk clk_usbpll = {
  411. .parent = &osc_main,
  412. .set_rate = local_usbpll_set_rate,
  413. .enable = local_usbpll_enable,
  414. .rate = 48000, /* In KHz */
  415. .get_rate = local_return_parent_rate,
  416. .round_rate = local_usbpll_round_rate,
  417. };
  418. static u32 clk_get_hclk_div(void)
  419. {
  420. static const u32 hclkdivs[4] = {1, 2, 4, 4};
  421. return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
  422. __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
  423. }
  424. static struct clk clk_hclk = {
  425. .parent = &clk_armpll,
  426. .get_rate = local_return_parent_rate,
  427. };
  428. static struct clk clk_pclk = {
  429. .parent = &clk_armpll,
  430. .get_rate = local_return_parent_rate,
  431. };
  432. static int local_onoff_enable(struct clk *clk, int enable)
  433. {
  434. u32 tmp;
  435. tmp = __raw_readl(clk->enable_reg);
  436. if (enable == 0)
  437. tmp &= ~clk->enable_mask;
  438. else
  439. tmp |= clk->enable_mask;
  440. __raw_writel(tmp, clk->enable_reg);
  441. return 0;
  442. }
  443. /* Peripheral clock sources */
  444. static struct clk clk_timer0 = {
  445. .parent = &clk_pclk,
  446. .enable = local_onoff_enable,
  447. .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
  448. .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
  449. .get_rate = local_return_parent_rate,
  450. };
  451. static struct clk clk_timer1 = {
  452. .parent = &clk_pclk,
  453. .enable = local_onoff_enable,
  454. .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
  455. .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
  456. .get_rate = local_return_parent_rate,
  457. };
  458. static struct clk clk_timer2 = {
  459. .parent = &clk_pclk,
  460. .enable = local_onoff_enable,
  461. .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
  462. .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
  463. .get_rate = local_return_parent_rate,
  464. };
  465. static struct clk clk_timer3 = {
  466. .parent = &clk_pclk,
  467. .enable = local_onoff_enable,
  468. .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
  469. .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
  470. .get_rate = local_return_parent_rate,
  471. };
  472. static struct clk clk_wdt = {
  473. .parent = &clk_pclk,
  474. .enable = local_onoff_enable,
  475. .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
  476. .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
  477. .get_rate = local_return_parent_rate,
  478. };
  479. static struct clk clk_vfp9 = {
  480. .parent = &clk_pclk,
  481. .enable = local_onoff_enable,
  482. .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
  483. .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
  484. .get_rate = local_return_parent_rate,
  485. };
  486. static struct clk clk_dma = {
  487. .parent = &clk_hclk,
  488. .enable = local_onoff_enable,
  489. .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
  490. .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
  491. .get_rate = local_return_parent_rate,
  492. };
  493. static struct clk clk_uart3 = {
  494. .parent = &clk_pclk,
  495. .enable = local_onoff_enable,
  496. .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
  497. .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
  498. .get_rate = local_return_parent_rate,
  499. };
  500. static struct clk clk_uart4 = {
  501. .parent = &clk_pclk,
  502. .enable = local_onoff_enable,
  503. .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
  504. .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
  505. .get_rate = local_return_parent_rate,
  506. };
  507. static struct clk clk_uart5 = {
  508. .parent = &clk_pclk,
  509. .enable = local_onoff_enable,
  510. .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
  511. .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
  512. .get_rate = local_return_parent_rate,
  513. };
  514. static struct clk clk_uart6 = {
  515. .parent = &clk_pclk,
  516. .enable = local_onoff_enable,
  517. .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
  518. .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
  519. .get_rate = local_return_parent_rate,
  520. };
  521. static struct clk clk_i2c0 = {
  522. .parent = &clk_hclk,
  523. .enable = local_onoff_enable,
  524. .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
  525. .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
  526. .get_rate = local_return_parent_rate,
  527. };
  528. static struct clk clk_i2c1 = {
  529. .parent = &clk_hclk,
  530. .enable = local_onoff_enable,
  531. .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
  532. .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
  533. .get_rate = local_return_parent_rate,
  534. };
  535. static struct clk clk_i2c2 = {
  536. .parent = &clk_pclk,
  537. .enable = local_onoff_enable,
  538. .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4),
  539. .enable_mask = 0x4,
  540. .get_rate = local_return_parent_rate,
  541. };
  542. static struct clk clk_ssp0 = {
  543. .parent = &clk_hclk,
  544. .enable = local_onoff_enable,
  545. .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
  546. .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
  547. .get_rate = local_return_parent_rate,
  548. };
  549. static struct clk clk_ssp1 = {
  550. .parent = &clk_hclk,
  551. .enable = local_onoff_enable,
  552. .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
  553. .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
  554. .get_rate = local_return_parent_rate,
  555. };
  556. static struct clk clk_kscan = {
  557. .parent = &osc_32KHz,
  558. .enable = local_onoff_enable,
  559. .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL,
  560. .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
  561. .get_rate = local_return_parent_rate,
  562. };
  563. static struct clk clk_nand = {
  564. .parent = &clk_hclk,
  565. .enable = local_onoff_enable,
  566. .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
  567. .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
  568. .get_rate = local_return_parent_rate,
  569. };
  570. static struct clk clk_i2s0 = {
  571. .parent = &clk_hclk,
  572. .enable = local_onoff_enable,
  573. .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
  574. .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
  575. .get_rate = local_return_parent_rate,
  576. };
  577. static struct clk clk_i2s1 = {
  578. .parent = &clk_hclk,
  579. .enable = local_onoff_enable,
  580. .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
  581. .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
  582. .get_rate = local_return_parent_rate,
  583. };
  584. static struct clk clk_net = {
  585. .parent = &clk_hclk,
  586. .enable = local_onoff_enable,
  587. .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL,
  588. .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
  589. LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
  590. LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
  591. .get_rate = local_return_parent_rate,
  592. };
  593. static struct clk clk_rtc = {
  594. .parent = &osc_32KHz,
  595. .rate = 1, /* 1 Hz */
  596. .get_rate = local_return_parent_rate,
  597. };
  598. static struct clk clk_usbd = {
  599. .parent = &clk_usbpll,
  600. .enable = local_onoff_enable,
  601. .enable_reg = LPC32XX_CLKPWR_USB_CTRL,
  602. .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
  603. .get_rate = local_return_parent_rate,
  604. };
  605. static int tsc_onoff_enable(struct clk *clk, int enable)
  606. {
  607. u32 tmp;
  608. /* Make sure 32KHz clock is the selected clock */
  609. tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
  610. tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
  611. __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
  612. if (enable == 0)
  613. __raw_writel(0, clk->enable_reg);
  614. else
  615. __raw_writel(clk->enable_mask, clk->enable_reg);
  616. return 0;
  617. }
  618. static struct clk clk_tsc = {
  619. .parent = &osc_32KHz,
  620. .enable = tsc_onoff_enable,
  621. .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
  622. .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
  623. .get_rate = local_return_parent_rate,
  624. };
  625. static int adc_onoff_enable(struct clk *clk, int enable)
  626. {
  627. u32 tmp;
  628. u32 divider;
  629. /* Use PERIPH_CLOCK */
  630. tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
  631. tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
  632. /*
  633. * Set clock divider so that we have equal to or less than
  634. * 4.5MHz clock at ADC
  635. */
  636. divider = clk->get_rate(clk) / 4500000 + 1;
  637. tmp |= divider;
  638. __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
  639. /* synchronize rate of this clock w/ actual HW setting */
  640. clk->rate = clk->get_rate(clk->parent) / divider;
  641. if (enable == 0)
  642. __raw_writel(0, clk->enable_reg);
  643. else
  644. __raw_writel(clk->enable_mask, clk->enable_reg);
  645. return 0;
  646. }
  647. static struct clk clk_adc = {
  648. .parent = &clk_pclk,
  649. .enable = adc_onoff_enable,
  650. .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
  651. .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
  652. .get_rate = local_return_parent_rate,
  653. };
  654. static int mmc_onoff_enable(struct clk *clk, int enable)
  655. {
  656. u32 tmp;
  657. tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
  658. ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
  659. /* If rate is 0, disable clock */
  660. if (enable != 0)
  661. tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
  662. __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
  663. return 0;
  664. }
  665. static unsigned long mmc_get_rate(struct clk *clk)
  666. {
  667. u32 div, rate, oldclk;
  668. /* The MMC clock must be on when accessing an MMC register */
  669. oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
  670. __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
  671. LPC32XX_CLKPWR_MS_CTRL);
  672. div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
  673. __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
  674. /* Get the parent clock rate */
  675. rate = clk->parent->get_rate(clk->parent);
  676. /* Get the MMC controller clock divider value */
  677. div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
  678. if (!div)
  679. div = 1;
  680. return rate / div;
  681. }
  682. static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
  683. {
  684. unsigned long div, prate;
  685. /* Get the parent clock rate */
  686. prate = clk->parent->get_rate(clk->parent);
  687. if (rate >= prate)
  688. return prate;
  689. div = prate / rate;
  690. if (div > 0xf)
  691. div = 0xf;
  692. return prate / div;
  693. }
  694. static int mmc_set_rate(struct clk *clk, unsigned long rate)
  695. {
  696. u32 oldclk, tmp;
  697. unsigned long prate, div, crate = mmc_round_rate(clk, rate);
  698. prate = clk->parent->get_rate(clk->parent);
  699. div = prate / crate;
  700. /* The MMC clock must be on when accessing an MMC register */
  701. oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
  702. __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
  703. LPC32XX_CLKPWR_MS_CTRL);
  704. tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
  705. ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
  706. tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
  707. __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
  708. __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
  709. return 0;
  710. }
  711. static struct clk clk_mmc = {
  712. .parent = &clk_armpll,
  713. .set_rate = mmc_set_rate,
  714. .get_rate = mmc_get_rate,
  715. .round_rate = mmc_round_rate,
  716. .enable = mmc_onoff_enable,
  717. .enable_reg = LPC32XX_CLKPWR_MS_CTRL,
  718. .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
  719. };
  720. static unsigned long clcd_get_rate(struct clk *clk)
  721. {
  722. u32 tmp, div, rate, oldclk;
  723. /* The LCD clock must be on when accessing an LCD register */
  724. oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
  725. __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
  726. LPC32XX_CLKPWR_LCDCLK_CTRL);
  727. tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
  728. __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
  729. rate = clk->parent->get_rate(clk->parent);
  730. /* Only supports internal clocking */
  731. if (tmp & TIM2_BCD)
  732. return rate;
  733. div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
  734. tmp = rate / (2 + div);
  735. return tmp;
  736. }
  737. static int clcd_set_rate(struct clk *clk, unsigned long rate)
  738. {
  739. u32 tmp, prate, div, oldclk;
  740. /* The LCD clock must be on when accessing an LCD register */
  741. oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
  742. __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
  743. LPC32XX_CLKPWR_LCDCLK_CTRL);
  744. tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
  745. prate = clk->parent->get_rate(clk->parent);
  746. if (rate < prate) {
  747. /* Find closest divider */
  748. div = prate / rate;
  749. if (div >= 2) {
  750. div -= 2;
  751. tmp &= ~TIM2_BCD;
  752. }
  753. tmp &= ~(0xF800001F);
  754. tmp |= (div & 0x1F);
  755. tmp |= (((div >> 5) & 0x1F) << 27);
  756. }
  757. __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
  758. __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
  759. return 0;
  760. }
  761. static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
  762. {
  763. u32 prate, div;
  764. prate = clk->parent->get_rate(clk->parent);
  765. if (rate >= prate)
  766. rate = prate;
  767. else {
  768. div = prate / rate;
  769. if (div > 0x3ff)
  770. div = 0x3ff;
  771. rate = prate / div;
  772. }
  773. return rate;
  774. }
  775. static struct clk clk_lcd = {
  776. .parent = &clk_hclk,
  777. .set_rate = clcd_set_rate,
  778. .get_rate = clcd_get_rate,
  779. .round_rate = clcd_round_rate,
  780. .enable = local_onoff_enable,
  781. .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL,
  782. .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
  783. };
  784. static void local_clk_disable(struct clk *clk)
  785. {
  786. /* Don't attempt to disable clock if it has no users */
  787. if (clk->usecount > 0) {
  788. clk->usecount--;
  789. /* Only disable clock when it has no more users */
  790. if ((clk->usecount == 0) && (clk->enable))
  791. clk->enable(clk, 0);
  792. /* Check parent clocks, they may need to be disabled too */
  793. if (clk->parent)
  794. local_clk_disable(clk->parent);
  795. }
  796. }
  797. static int local_clk_enable(struct clk *clk)
  798. {
  799. int ret = 0;
  800. /* Enable parent clocks first and update use counts */
  801. if (clk->parent)
  802. ret = local_clk_enable(clk->parent);
  803. if (!ret) {
  804. /* Only enable clock if it's currently disabled */
  805. if ((clk->usecount == 0) && (clk->enable))
  806. ret = clk->enable(clk, 1);
  807. if (!ret)
  808. clk->usecount++;
  809. else if (clk->parent)
  810. local_clk_disable(clk->parent);
  811. }
  812. return ret;
  813. }
  814. /*
  815. * clk_enable - inform the system when the clock source should be running.
  816. */
  817. int clk_enable(struct clk *clk)
  818. {
  819. int ret;
  820. unsigned long flags;
  821. spin_lock_irqsave(&global_clkregs_lock, flags);
  822. ret = local_clk_enable(clk);
  823. spin_unlock_irqrestore(&global_clkregs_lock, flags);
  824. return ret;
  825. }
  826. EXPORT_SYMBOL(clk_enable);
  827. /*
  828. * clk_disable - inform the system when the clock source is no longer required
  829. */
  830. void clk_disable(struct clk *clk)
  831. {
  832. unsigned long flags;
  833. spin_lock_irqsave(&global_clkregs_lock, flags);
  834. local_clk_disable(clk);
  835. spin_unlock_irqrestore(&global_clkregs_lock, flags);
  836. }
  837. EXPORT_SYMBOL(clk_disable);
  838. /*
  839. * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
  840. */
  841. unsigned long clk_get_rate(struct clk *clk)
  842. {
  843. return clk->get_rate(clk);
  844. }
  845. EXPORT_SYMBOL(clk_get_rate);
  846. /*
  847. * clk_set_rate - set the clock rate for a clock source
  848. */
  849. int clk_set_rate(struct clk *clk, unsigned long rate)
  850. {
  851. int ret = -EINVAL;
  852. /*
  853. * Most system clocks can only be enabled or disabled, with
  854. * the actual rate set as part of the peripheral dividers
  855. * instead of high level clock control
  856. */
  857. if (clk->set_rate)
  858. ret = clk->set_rate(clk, rate);
  859. return ret;
  860. }
  861. EXPORT_SYMBOL(clk_set_rate);
  862. /*
  863. * clk_round_rate - adjust a rate to the exact rate a clock can provide
  864. */
  865. long clk_round_rate(struct clk *clk, unsigned long rate)
  866. {
  867. if (clk->round_rate)
  868. rate = clk->round_rate(clk, rate);
  869. else
  870. rate = clk->get_rate(clk);
  871. return rate;
  872. }
  873. EXPORT_SYMBOL(clk_round_rate);
  874. /*
  875. * clk_set_parent - set the parent clock source for this clock
  876. */
  877. int clk_set_parent(struct clk *clk, struct clk *parent)
  878. {
  879. /* Clock re-parenting is not supported */
  880. return -EINVAL;
  881. }
  882. EXPORT_SYMBOL(clk_set_parent);
  883. /*
  884. * clk_get_parent - get the parent clock source for this clock
  885. */
  886. struct clk *clk_get_parent(struct clk *clk)
  887. {
  888. return clk->parent;
  889. }
  890. EXPORT_SYMBOL(clk_get_parent);
  891. #define _REGISTER_CLOCK(d, n, c) \
  892. { \
  893. .dev_id = (d), \
  894. .con_id = (n), \
  895. .clk = &(c), \
  896. },
  897. static struct clk_lookup lookups[] = {
  898. _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
  899. _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
  900. _REGISTER_CLOCK(NULL, "osc_main", osc_main)
  901. _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
  902. _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
  903. _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
  904. _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
  905. _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
  906. _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
  907. _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
  908. _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
  909. _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
  910. _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
  911. _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
  912. _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
  913. _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
  914. _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
  915. _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
  916. _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
  917. _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
  918. _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
  919. _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
  920. _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
  921. _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
  922. _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
  923. _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
  924. _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
  925. _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
  926. _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
  927. _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
  928. _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
  929. _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
  930. _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
  931. _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
  932. _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
  933. };
  934. static int __init clk_init(void)
  935. {
  936. int i;
  937. for (i = 0; i < ARRAY_SIZE(lookups); i++)
  938. clkdev_add(&lookups[i]);
  939. /*
  940. * Setup muxed SYSCLK for HCLK PLL base -this selects the
  941. * parent clock used for the ARM PLL and is used to derive
  942. * the many system clock rates in the device.
  943. */
  944. if (clk_is_sysclk_mainosc() != 0)
  945. clk_sys.parent = &osc_main;
  946. else
  947. clk_sys.parent = &osc_pll397;
  948. clk_sys.rate = clk_sys.parent->rate;
  949. /* Compute the current ARM PLL and USB PLL frequencies */
  950. local_update_armpll_rate();
  951. /* Compute HCLK and PCLK bus rates */
  952. clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
  953. clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
  954. /*
  955. * Enable system clocks - this step is somewhat formal, as the
  956. * clocks are already running, but it does get the clock data
  957. * inline with the actual system state. Never disable these
  958. * clocks as they will only stop if the system is going to sleep.
  959. * In that case, the chip/system power management functions will
  960. * handle clock gating.
  961. */
  962. if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
  963. printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
  964. /*
  965. * Timers 0 and 1 were enabled and are being used by the high
  966. * resolution tick function prior to this driver being initialized.
  967. * Tag them now as used.
  968. */
  969. if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
  970. printk(KERN_ERR "Error enabling timer tick clocks\n");
  971. return 0;
  972. }
  973. core_initcall(clk_init);