mac53c94.c 15 KB

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  1. /*
  2. * SCSI low-level driver for the 53c94 SCSI bus adaptor found
  3. * on Power Macintosh computers, controlling the external SCSI chain.
  4. * We assume the 53c94 is connected to a DBDMA (descriptor-based DMA)
  5. * controller.
  6. *
  7. * Paul Mackerras, August 1996.
  8. * Copyright (C) 1996 Paul Mackerras.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/delay.h>
  12. #include <linux/types.h>
  13. #include <linux/string.h>
  14. #include <linux/slab.h>
  15. #include <linux/blkdev.h>
  16. #include <linux/proc_fs.h>
  17. #include <linux/stat.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/interrupt.h>
  20. #include <asm/dbdma.h>
  21. #include <asm/io.h>
  22. #include <asm/pgtable.h>
  23. #include <asm/prom.h>
  24. #include <asm/system.h>
  25. #include <asm/pci-bridge.h>
  26. #include <asm/macio.h>
  27. #include <scsi/scsi.h>
  28. #include <scsi/scsi_cmnd.h>
  29. #include <scsi/scsi_device.h>
  30. #include <scsi/scsi_host.h>
  31. #include "mac53c94.h"
  32. enum fsc_phase {
  33. idle,
  34. selecting,
  35. dataing,
  36. completing,
  37. busfreeing,
  38. };
  39. struct fsc_state {
  40. struct mac53c94_regs __iomem *regs;
  41. int intr;
  42. struct dbdma_regs __iomem *dma;
  43. int dmaintr;
  44. int clk_freq;
  45. struct Scsi_Host *host;
  46. struct scsi_cmnd *request_q;
  47. struct scsi_cmnd *request_qtail;
  48. struct scsi_cmnd *current_req; /* req we're currently working on */
  49. enum fsc_phase phase; /* what we're currently trying to do */
  50. struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
  51. void *dma_cmd_space;
  52. struct pci_dev *pdev;
  53. dma_addr_t dma_addr;
  54. struct macio_dev *mdev;
  55. };
  56. static void mac53c94_init(struct fsc_state *);
  57. static void mac53c94_start(struct fsc_state *);
  58. static void mac53c94_interrupt(int, void *, struct pt_regs *);
  59. static irqreturn_t do_mac53c94_interrupt(int, void *, struct pt_regs *);
  60. static void cmd_done(struct fsc_state *, int result);
  61. static void set_dma_cmds(struct fsc_state *, struct scsi_cmnd *);
  62. static int mac53c94_queue(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  63. {
  64. struct fsc_state *state;
  65. #if 0
  66. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  67. int i;
  68. printk(KERN_DEBUG "mac53c94_queue %p: command is", cmd);
  69. for (i = 0; i < cmd->cmd_len; ++i)
  70. printk(" %.2x", cmd->cmnd[i]);
  71. printk("\n" KERN_DEBUG "use_sg=%d request_bufflen=%d request_buffer=%p\n",
  72. cmd->use_sg, cmd->request_bufflen, cmd->request_buffer);
  73. }
  74. #endif
  75. cmd->scsi_done = done;
  76. cmd->host_scribble = NULL;
  77. state = (struct fsc_state *) cmd->device->host->hostdata;
  78. if (state->request_q == NULL)
  79. state->request_q = cmd;
  80. else
  81. state->request_qtail->host_scribble = (void *) cmd;
  82. state->request_qtail = cmd;
  83. if (state->phase == idle)
  84. mac53c94_start(state);
  85. return 0;
  86. }
  87. static int mac53c94_host_reset(struct scsi_cmnd *cmd)
  88. {
  89. struct fsc_state *state = (struct fsc_state *) cmd->device->host->hostdata;
  90. struct mac53c94_regs __iomem *regs = state->regs;
  91. struct dbdma_regs __iomem *dma = state->dma;
  92. writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control);
  93. writeb(CMD_SCSI_RESET, &regs->command); /* assert RST */
  94. udelay(100); /* leave it on for a while (>= 25us) */
  95. writeb(CMD_RESET, &regs->command);
  96. udelay(20);
  97. mac53c94_init(state);
  98. writeb(CMD_NOP, &regs->command);
  99. return SUCCESS;
  100. }
  101. static void mac53c94_init(struct fsc_state *state)
  102. {
  103. struct mac53c94_regs __iomem *regs = state->regs;
  104. struct dbdma_regs __iomem *dma = state->dma;
  105. int x;
  106. writeb(state->host->this_id | CF1_PAR_ENABLE, &regs->config1);
  107. writeb(TIMO_VAL(250), &regs->sel_timeout); /* 250ms */
  108. writeb(CLKF_VAL(state->clk_freq), &regs->clk_factor);
  109. writeb(CF2_FEATURE_EN, &regs->config2);
  110. writeb(0, &regs->config3);
  111. writeb(0, &regs->sync_period);
  112. writeb(0, &regs->sync_offset);
  113. x = readb(&regs->interrupt);
  114. writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control);
  115. }
  116. /*
  117. * Start the next command for a 53C94.
  118. * Should be called with interrupts disabled.
  119. */
  120. static void mac53c94_start(struct fsc_state *state)
  121. {
  122. struct scsi_cmnd *cmd;
  123. struct mac53c94_regs __iomem *regs = state->regs;
  124. int i;
  125. if (state->phase != idle || state->current_req != NULL)
  126. panic("inappropriate mac53c94_start (state=%p)", state);
  127. if (state->request_q == NULL)
  128. return;
  129. state->current_req = cmd = state->request_q;
  130. state->request_q = (struct scsi_cmnd *) cmd->host_scribble;
  131. /* Off we go */
  132. writeb(0, &regs->count_lo);
  133. writeb(0, &regs->count_mid);
  134. writeb(0, &regs->count_hi);
  135. writeb(CMD_NOP + CMD_DMA_MODE, &regs->command);
  136. udelay(1);
  137. writeb(CMD_FLUSH, &regs->command);
  138. udelay(1);
  139. writeb(cmd->device->id, &regs->dest_id);
  140. writeb(0, &regs->sync_period);
  141. writeb(0, &regs->sync_offset);
  142. /* load the command into the FIFO */
  143. for (i = 0; i < cmd->cmd_len; ++i)
  144. writeb(cmd->cmnd[i], &regs->fifo);
  145. /* do select without ATN XXX */
  146. writeb(CMD_SELECT, &regs->command);
  147. state->phase = selecting;
  148. if (cmd->use_sg > 0 || cmd->request_bufflen != 0)
  149. set_dma_cmds(state, cmd);
  150. }
  151. static irqreturn_t do_mac53c94_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
  152. {
  153. unsigned long flags;
  154. struct Scsi_Host *dev = ((struct fsc_state *) dev_id)->current_req->device->host;
  155. spin_lock_irqsave(dev->host_lock, flags);
  156. mac53c94_interrupt(irq, dev_id, ptregs);
  157. spin_unlock_irqrestore(dev->host_lock, flags);
  158. return IRQ_HANDLED;
  159. }
  160. static void mac53c94_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
  161. {
  162. struct fsc_state *state = (struct fsc_state *) dev_id;
  163. struct mac53c94_regs __iomem *regs = state->regs;
  164. struct dbdma_regs __iomem *dma = state->dma;
  165. struct scsi_cmnd *cmd = state->current_req;
  166. int nb, stat, seq, intr;
  167. static int mac53c94_errors;
  168. /*
  169. * Apparently, reading the interrupt register unlatches
  170. * the status and sequence step registers.
  171. */
  172. seq = readb(&regs->seqstep);
  173. stat = readb(&regs->status);
  174. intr = readb(&regs->interrupt);
  175. #if 0
  176. printk(KERN_DEBUG "mac53c94_intr, intr=%x stat=%x seq=%x phase=%d\n",
  177. intr, stat, seq, state->phase);
  178. #endif
  179. if (intr & INTR_RESET) {
  180. /* SCSI bus was reset */
  181. printk(KERN_INFO "external SCSI bus reset detected\n");
  182. writeb(CMD_NOP, &regs->command);
  183. writel(RUN << 16, &dma->control); /* stop dma */
  184. cmd_done(state, DID_RESET << 16);
  185. return;
  186. }
  187. if (intr & INTR_ILL_CMD) {
  188. printk(KERN_ERR "53c94: invalid cmd, intr=%x stat=%x seq=%x phase=%d\n",
  189. intr, stat, seq, state->phase);
  190. cmd_done(state, DID_ERROR << 16);
  191. return;
  192. }
  193. if (stat & STAT_ERROR) {
  194. #if 0
  195. /* XXX these seem to be harmless? */
  196. printk("53c94: bad error, intr=%x stat=%x seq=%x phase=%d\n",
  197. intr, stat, seq, state->phase);
  198. #endif
  199. ++mac53c94_errors;
  200. writeb(CMD_NOP + CMD_DMA_MODE, &regs->command);
  201. }
  202. if (cmd == 0) {
  203. printk(KERN_DEBUG "53c94: interrupt with no command active?\n");
  204. return;
  205. }
  206. if (stat & STAT_PARITY) {
  207. printk(KERN_ERR "mac53c94: parity error\n");
  208. cmd_done(state, DID_PARITY << 16);
  209. return;
  210. }
  211. switch (state->phase) {
  212. case selecting:
  213. if (intr & INTR_DISCONNECT) {
  214. /* selection timed out */
  215. cmd_done(state, DID_BAD_TARGET << 16);
  216. return;
  217. }
  218. if (intr != INTR_BUS_SERV + INTR_DONE) {
  219. printk(KERN_DEBUG "got intr %x during selection\n", intr);
  220. cmd_done(state, DID_ERROR << 16);
  221. return;
  222. }
  223. if ((seq & SS_MASK) != SS_DONE) {
  224. printk(KERN_DEBUG "seq step %x after command\n", seq);
  225. cmd_done(state, DID_ERROR << 16);
  226. return;
  227. }
  228. writeb(CMD_NOP, &regs->command);
  229. /* set DMA controller going if any data to transfer */
  230. if ((stat & (STAT_MSG|STAT_CD)) == 0
  231. && (cmd->use_sg > 0 || cmd->request_bufflen != 0)) {
  232. nb = cmd->SCp.this_residual;
  233. if (nb > 0xfff0)
  234. nb = 0xfff0;
  235. cmd->SCp.this_residual -= nb;
  236. writeb(nb, &regs->count_lo);
  237. writeb(nb >> 8, &regs->count_mid);
  238. writeb(CMD_DMA_MODE + CMD_NOP, &regs->command);
  239. writel(virt_to_phys(state->dma_cmds), &dma->cmdptr);
  240. writel((RUN << 16) | RUN, &dma->control);
  241. writeb(CMD_DMA_MODE + CMD_XFER_DATA, &regs->command);
  242. state->phase = dataing;
  243. break;
  244. } else if ((stat & STAT_PHASE) == STAT_CD + STAT_IO) {
  245. /* up to status phase already */
  246. writeb(CMD_I_COMPLETE, &regs->command);
  247. state->phase = completing;
  248. } else {
  249. printk(KERN_DEBUG "in unexpected phase %x after cmd\n",
  250. stat & STAT_PHASE);
  251. cmd_done(state, DID_ERROR << 16);
  252. return;
  253. }
  254. break;
  255. case dataing:
  256. if (intr != INTR_BUS_SERV) {
  257. printk(KERN_DEBUG "got intr %x before status\n", intr);
  258. cmd_done(state, DID_ERROR << 16);
  259. return;
  260. }
  261. if (cmd->SCp.this_residual != 0
  262. && (stat & (STAT_MSG|STAT_CD)) == 0) {
  263. /* Set up the count regs to transfer more */
  264. nb = cmd->SCp.this_residual;
  265. if (nb > 0xfff0)
  266. nb = 0xfff0;
  267. cmd->SCp.this_residual -= nb;
  268. writeb(nb, &regs->count_lo);
  269. writeb(nb >> 8, &regs->count_mid);
  270. writeb(CMD_DMA_MODE + CMD_NOP, &regs->command);
  271. writeb(CMD_DMA_MODE + CMD_XFER_DATA, &regs->command);
  272. break;
  273. }
  274. if ((stat & STAT_PHASE) != STAT_CD + STAT_IO) {
  275. printk(KERN_DEBUG "intr %x before data xfer complete\n", intr);
  276. }
  277. writel(RUN << 16, &dma->control); /* stop dma */
  278. if (cmd->use_sg != 0) {
  279. pci_unmap_sg(state->pdev,
  280. (struct scatterlist *)cmd->request_buffer,
  281. cmd->use_sg, cmd->sc_data_direction);
  282. } else {
  283. pci_unmap_single(state->pdev, state->dma_addr,
  284. cmd->request_bufflen, cmd->sc_data_direction);
  285. }
  286. /* should check dma status */
  287. writeb(CMD_I_COMPLETE, &regs->command);
  288. state->phase = completing;
  289. break;
  290. case completing:
  291. if (intr != INTR_DONE) {
  292. printk(KERN_DEBUG "got intr %x on completion\n", intr);
  293. cmd_done(state, DID_ERROR << 16);
  294. return;
  295. }
  296. cmd->SCp.Status = readb(&regs->fifo);
  297. cmd->SCp.Message = readb(&regs->fifo);
  298. cmd->result = CMD_ACCEPT_MSG;
  299. writeb(CMD_ACCEPT_MSG, &regs->command);
  300. state->phase = busfreeing;
  301. break;
  302. case busfreeing:
  303. if (intr != INTR_DISCONNECT) {
  304. printk(KERN_DEBUG "got intr %x when expected disconnect\n", intr);
  305. }
  306. cmd_done(state, (DID_OK << 16) + (cmd->SCp.Message << 8)
  307. + cmd->SCp.Status);
  308. break;
  309. default:
  310. printk(KERN_DEBUG "don't know about phase %d\n", state->phase);
  311. }
  312. }
  313. static void cmd_done(struct fsc_state *state, int result)
  314. {
  315. struct scsi_cmnd *cmd;
  316. cmd = state->current_req;
  317. if (cmd != 0) {
  318. cmd->result = result;
  319. (*cmd->scsi_done)(cmd);
  320. state->current_req = NULL;
  321. }
  322. state->phase = idle;
  323. mac53c94_start(state);
  324. }
  325. /*
  326. * Set up DMA commands for transferring data.
  327. */
  328. static void set_dma_cmds(struct fsc_state *state, struct scsi_cmnd *cmd)
  329. {
  330. int i, dma_cmd, total;
  331. struct scatterlist *scl;
  332. struct dbdma_cmd *dcmds;
  333. dma_addr_t dma_addr;
  334. u32 dma_len;
  335. dma_cmd = cmd->sc_data_direction == DMA_TO_DEVICE ?
  336. OUTPUT_MORE : INPUT_MORE;
  337. dcmds = state->dma_cmds;
  338. if (cmd->use_sg > 0) {
  339. int nseg;
  340. total = 0;
  341. scl = (struct scatterlist *) cmd->buffer;
  342. nseg = pci_map_sg(state->pdev, scl, cmd->use_sg,
  343. cmd->sc_data_direction);
  344. for (i = 0; i < nseg; ++i) {
  345. dma_addr = sg_dma_address(scl);
  346. dma_len = sg_dma_len(scl);
  347. if (dma_len > 0xffff)
  348. panic("mac53c94: scatterlist element >= 64k");
  349. total += dma_len;
  350. st_le16(&dcmds->req_count, dma_len);
  351. st_le16(&dcmds->command, dma_cmd);
  352. st_le32(&dcmds->phy_addr, dma_addr);
  353. dcmds->xfer_status = 0;
  354. ++scl;
  355. ++dcmds;
  356. }
  357. } else {
  358. total = cmd->request_bufflen;
  359. if (total > 0xffff)
  360. panic("mac53c94: transfer size >= 64k");
  361. dma_addr = pci_map_single(state->pdev, cmd->request_buffer,
  362. total, cmd->sc_data_direction);
  363. state->dma_addr = dma_addr;
  364. st_le16(&dcmds->req_count, total);
  365. st_le32(&dcmds->phy_addr, dma_addr);
  366. dcmds->xfer_status = 0;
  367. ++dcmds;
  368. }
  369. dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
  370. st_le16(&dcmds[-1].command, dma_cmd);
  371. st_le16(&dcmds->command, DBDMA_STOP);
  372. cmd->SCp.this_residual = total;
  373. }
  374. static struct scsi_host_template mac53c94_template = {
  375. .proc_name = "53c94",
  376. .name = "53C94",
  377. .queuecommand = mac53c94_queue,
  378. .eh_host_reset_handler = mac53c94_host_reset,
  379. .can_queue = 1,
  380. .this_id = 7,
  381. .sg_tablesize = SG_ALL,
  382. .cmd_per_lun = 1,
  383. .use_clustering = DISABLE_CLUSTERING,
  384. };
  385. static int mac53c94_probe(struct macio_dev *mdev, const struct of_match *match)
  386. {
  387. struct device_node *node = macio_get_of_node(mdev);
  388. struct pci_dev *pdev = macio_get_pci_dev(mdev);
  389. struct fsc_state *state;
  390. struct Scsi_Host *host;
  391. void *dma_cmd_space;
  392. unsigned char *clkprop;
  393. int proplen;
  394. if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
  395. printk(KERN_ERR "mac53c94: expected 2 addrs and intrs (got %d/%d)\n",
  396. node->n_addrs, node->n_intrs);
  397. return -ENODEV;
  398. }
  399. if (macio_request_resources(mdev, "mac53c94") != 0) {
  400. printk(KERN_ERR "mac53c94: unable to request memory resources");
  401. return -EBUSY;
  402. }
  403. host = scsi_host_alloc(&mac53c94_template, sizeof(struct fsc_state));
  404. if (host == NULL) {
  405. printk(KERN_ERR "mac53c94: couldn't register host");
  406. goto out_release;
  407. }
  408. state = (struct fsc_state *) host->hostdata;
  409. macio_set_drvdata(mdev, state);
  410. state->host = host;
  411. state->pdev = pdev;
  412. state->mdev = mdev;
  413. state->regs = (struct mac53c94_regs __iomem *)
  414. ioremap(macio_resource_start(mdev, 0), 0x1000);
  415. state->intr = macio_irq(mdev, 0);
  416. state->dma = (struct dbdma_regs __iomem *)
  417. ioremap(macio_resource_start(mdev, 1), 0x1000);
  418. state->dmaintr = macio_irq(mdev, 1);
  419. if (state->regs == NULL || state->dma == NULL) {
  420. printk(KERN_ERR "mac53c94: ioremap failed for %s\n",
  421. node->full_name);
  422. goto out_free;
  423. }
  424. clkprop = get_property(node, "clock-frequency", &proplen);
  425. if (clkprop == NULL || proplen != sizeof(int)) {
  426. printk(KERN_ERR "%s: can't get clock frequency, "
  427. "assuming 25MHz\n", node->full_name);
  428. state->clk_freq = 25000000;
  429. } else
  430. state->clk_freq = *(int *)clkprop;
  431. /* Space for dma command list: +1 for stop command,
  432. * +1 to allow for aligning.
  433. * XXX FIXME: Use DMA consistent routines
  434. */
  435. dma_cmd_space = kmalloc((host->sg_tablesize + 2) *
  436. sizeof(struct dbdma_cmd), GFP_KERNEL);
  437. if (dma_cmd_space == 0) {
  438. printk(KERN_ERR "mac53c94: couldn't allocate dma "
  439. "command space for %s\n", node->full_name);
  440. goto out_free;
  441. }
  442. state->dma_cmds = (struct dbdma_cmd *)DBDMA_ALIGN(dma_cmd_space);
  443. memset(state->dma_cmds, 0, (host->sg_tablesize + 1)
  444. * sizeof(struct dbdma_cmd));
  445. state->dma_cmd_space = dma_cmd_space;
  446. mac53c94_init(state);
  447. if (request_irq(state->intr, do_mac53c94_interrupt, 0, "53C94", state)) {
  448. printk(KERN_ERR "mac53C94: can't get irq %d for %s\n",
  449. state->intr, node->full_name);
  450. goto out_free_dma;
  451. }
  452. /* XXX FIXME: handle failure */
  453. scsi_add_host(host, &mdev->ofdev.dev);
  454. scsi_scan_host(host);
  455. return 0;
  456. out_free_dma:
  457. kfree(state->dma_cmd_space);
  458. out_free:
  459. if (state->dma != NULL)
  460. iounmap(state->dma);
  461. if (state->regs != NULL)
  462. iounmap(state->regs);
  463. scsi_host_put(host);
  464. out_release:
  465. macio_release_resources(mdev);
  466. return -ENODEV;
  467. }
  468. static int mac53c94_remove(struct macio_dev *mdev)
  469. {
  470. struct fsc_state *fp = (struct fsc_state *)macio_get_drvdata(mdev);
  471. struct Scsi_Host *host = fp->host;
  472. scsi_remove_host(host);
  473. free_irq(fp->intr, fp);
  474. if (fp->regs)
  475. iounmap((void *) fp->regs);
  476. if (fp->dma)
  477. iounmap((void *) fp->dma);
  478. kfree(fp->dma_cmd_space);
  479. scsi_host_put(host);
  480. macio_release_resources(mdev);
  481. return 0;
  482. }
  483. static struct of_match mac53c94_match[] =
  484. {
  485. {
  486. .name = "53c94",
  487. .type = OF_ANY_MATCH,
  488. .compatible = OF_ANY_MATCH
  489. },
  490. {},
  491. };
  492. static struct macio_driver mac53c94_driver =
  493. {
  494. .name = "mac53c94",
  495. .match_table = mac53c94_match,
  496. .probe = mac53c94_probe,
  497. .remove = mac53c94_remove,
  498. };
  499. static int __init init_mac53c94(void)
  500. {
  501. return macio_register_driver(&mac53c94_driver);
  502. }
  503. static void __exit exit_mac53c94(void)
  504. {
  505. return macio_unregister_driver(&mac53c94_driver);
  506. }
  507. module_init(init_mac53c94);
  508. module_exit(exit_mac53c94);
  509. MODULE_DESCRIPTION("PowerMac 53c94 SCSI driver");
  510. MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>");
  511. MODULE_LICENSE("GPL");